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Merge "fix(intel): implement soc and lwsoc bridge control for burst speed" into integration

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Mark Dykes 2024-10-18 00:37:34 +02:00 • committed by TrustedFirmware Code Review
commit 6ff74c1bf5
2 changed files with 23 additions and 0 deletions
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3
plat/intel/soc/agilex5/include/agilex5_system_manager.h
View file

@ -25,6 +25,7 @@
#define SOCFPGA_SYSMGR_TSN_0_ACE 0x50 #define SOCFPGA_SYSMGR_TSN_0_ACE 0x50
#define SOCFPGA_SYSMGR_TSN_1_ACE 0x54 #define SOCFPGA_SYSMGR_TSN_1_ACE 0x54
#define SOCFPGA_SYSMGR_TSN_2_ACE 0x58 #define SOCFPGA_SYSMGR_TSN_2_ACE 0x58
#define SOCFPGA_SYSMGR_FPGA_BRIDGE_CTRL 0x5C
#define SOCFPGA_SYSMGR_FPGAINTF_EN_1 0x68 #define SOCFPGA_SYSMGR_FPGAINTF_EN_1 0x68
#define SOCFPGA_SYSMGR_FPGAINTF_EN_2 0x6C #define SOCFPGA_SYSMGR_FPGAINTF_EN_2 0x6C
#define SOCFPGA_SYSMGR_FPGAINTF_EN_3 0x70 #define SOCFPGA_SYSMGR_FPGAINTF_EN_3 0x70
@ -189,6 +190,8 @@
#define SYSMGR_SDMMC_SMPLSEL(x) (((x) & 0x7) << 4) #define SYSMGR_SDMMC_SMPLSEL(x) (((x) & 0x7) << 4)
#define SYSMGR_F2S_BRIDGE_CTRL_EN BIT(0) #define SYSMGR_F2S_BRIDGE_CTRL_EN BIT(0)
#define SYSMGR_SOC_BRIDGE_CTRL_EN BIT(0)
#define SYSMGR_LWSOC_BRIDGE_CTRL_EN BIT(1)
#define IDLE_DATA_LWSOC2FPGA BIT(4) #define IDLE_DATA_LWSOC2FPGA BIT(4)
#define IDLE_DATA_SOC2FPGA BIT(0) #define IDLE_DATA_SOC2FPGA BIT(0)
#define IDLE_DATA_MASK (IDLE_DATA_LWSOC2FPGA \ #define IDLE_DATA_MASK (IDLE_DATA_LWSOC2FPGA \

20
plat/intel/soc/common/soc/socfpga_reset_manager.c
View file

@ -484,6 +484,11 @@ int socfpga_bridges_enable(uint32_t mask)
(~brg_lst & (RSTMGR_BRGMODRST_SOC2FPGA (~brg_lst & (RSTMGR_BRGMODRST_SOC2FPGA
| RSTMGR_BRGMODRST_LWHPS2FPGA)) | RSTMGR_BRGMODRST_LWHPS2FPGA))
| RSTMGR_BRGMODRST_SOC2FPGA); | RSTMGR_BRGMODRST_SOC2FPGA);
/* Set System Manager soc bridge control register[soc2fpga_ready_latency_enable] = 1 */
VERBOSE("Set SOC soc2fpga_ready_latency_enable ...\n");
mmio_setbits_32(SOCFPGA_SYSMGR(FPGA_BRIDGE_CTRL),
SYSMGR_SOC_BRIDGE_CTRL_EN);
} }
/**************** LWSOCFPGA ****************/ /**************** LWSOCFPGA ****************/
@ -567,6 +572,11 @@ int socfpga_bridges_enable(uint32_t mask)
((~brg_lst & (RSTMGR_BRGMODRST_SOC2FPGA ((~brg_lst & (RSTMGR_BRGMODRST_SOC2FPGA
| RSTMGR_BRGMODRST_LWHPS2FPGA))) | RSTMGR_BRGMODRST_LWHPS2FPGA)))
| RSTMGR_BRGMODRST_LWHPS2FPGA); | RSTMGR_BRGMODRST_LWHPS2FPGA);
/* Set System Manager lwsoc bridge control register[lwsoc2fpga_ready_latency_enable] = 1 */
VERBOSE("Set LWSOC lwsoc2fpga_ready_latency_enable ...\n");
mmio_setbits_32(SOCFPGA_SYSMGR(FPGA_BRIDGE_CTRL),
SYSMGR_LWSOC_BRIDGE_CTRL_EN);
} }
#else #else
if (brg_mask != 0U) { if (brg_mask != 0U) {
@ -955,6 +965,11 @@ int socfpga_bridges_disable(uint32_t mask)
mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST), mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST),
RSTMGR_BRGMODRST_SOC2FPGA); RSTMGR_BRGMODRST_SOC2FPGA);
/* Clear System Manager soc bridge control register[soc2fpga_ready_latency_enable] = 1 */
VERBOSE("Clear SOC soc2fpga_ready_latency_enable ...\n");
mmio_clrbits_32(SOCFPGA_SYSMGR(FPGA_BRIDGE_CTRL),
SYSMGR_SOC_BRIDGE_CTRL_EN);
udelay(1000); udelay(1000);
} }
@ -988,6 +1003,11 @@ int socfpga_bridges_disable(uint32_t mask)
mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST), mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST),
RSTMGR_BRGMODRST_LWHPS2FPGA); RSTMGR_BRGMODRST_LWHPS2FPGA);
/* Clear System Manager lwsoc bridge control register[lwsoc2fpga_ready_latency_enable] = 1 */
VERBOSE("Clear LWSOC lwsoc2fpga_ready_latency_enable ...\n");
mmio_clrbits_32(SOCFPGA_SYSMGR(FPGA_BRIDGE_CTRL),
SYSMGR_LWSOC_BRIDGE_CTRL_EN);
udelay(1000); udelay(1000);
} }
#else #else