Djam/arm-trusted-firmware
1
0
Fork 0
mirror of https://github.com/ARM-software/arm-trusted-firmware.git synced 2025-04-16 09:34:18 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

ARMv7: introduce Cortex-A7

Browse source 
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
This commit is contained in:
Etienne Carriere 2017-11-05 22:56:34 +01:00
parent d56a846121
commit 6ff43c2639
2 changed files with 95 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

20
include/lib/cpus/aarch32/cortex_a7.h Normal file
View file

@ -0,0 +1,20 @@
/*
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __CORTEX_A7_H__
#define __CORTEX_A7_H__
/*******************************************************************************
* Cortex-A7 midr with version/revision set to 0
******************************************************************************/
#define CORTEX_A7_MIDR 0x410FC070
/*******************************************************************************
* CPU Auxiliary Control register specific definitions.
******************************************************************************/
#define CORTEX_A7_ACTLR_SMP_BIT (1 << 6)
#endif /* __CORTEX_A7_H__ */

75
lib/cpus/aarch32/cortex_a7.S Normal file
View file

@ -0,0 +1,75 @@
/*
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch.h>
#include <asm_macros.S>
#include <assert_macros.S>
#include <cortex_a7.h>
#include <cpu_macros.S>
.macro assert_cache_enabled
#if ENABLE_ASSERTIONS
ldcopr r0, SCTLR
tst r0, #SCTLR_C_BIT
ASM_ASSERT(eq)
#endif
.endm
func cortex_a7_disable_smp
ldcopr r0, ACTLR
bic r0, #CORTEX_A7_ACTLR_SMP_BIT
stcopr r0, ACTLR
isb
dsb sy
bx lr
endfunc cortex_a7_disable_smp
func cortex_a7_enable_smp
ldcopr r0, ACTLR
orr r0, #CORTEX_A7_ACTLR_SMP_BIT
stcopr r0, ACTLR
isb
bx lr
endfunc cortex_a7_enable_smp
func cortex_a7_reset_func
b cortex_a7_enable_smp
endfunc cortex_a7_reset_func
func cortex_a7_core_pwr_dwn
push {r12, lr}
assert_cache_enabled
/* Flush L1 cache */
mov r0, #DC_OP_CISW
bl dcsw_op_level1
/* Exit cluster coherency */
pop {r12, lr}
b cortex_a7_disable_smp
endfunc cortex_a7_core_pwr_dwn
func cortex_a7_cluster_pwr_dwn
push {r12, lr}
assert_cache_enabled
/* Flush L1 caches */
mov r0, #DC_OP_CISW
bl dcsw_op_level1
bl plat_disable_acp
/* Exit cluster coherency */
pop {r12, lr}
b cortex_a7_disable_smp
endfunc cortex_a7_cluster_pwr_dwn
declare_cpu_ops cortex_a7, CORTEX_A7_MIDR, \
cortex_a7_reset_func, \
cortex_a7_core_pwr_dwn, \
cortex_a7_cluster_pwr_dwn