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AArch32: Add ARM platform changes in BL2
This patch adds ARM platform changes in BL2 for AArch32 state. It instantiates a descriptor array for ARM platforms describing image and entrypoint information for `SCP_BL2`, `BL32` and `BL33`. It also enables building of BL2 for ARCH=aarch32. Change-Id: I60dc7a284311eceba401fc789311c50ac746c51e
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5 changed files with 117 additions and 4 deletions
4
Makefile
4
Makefile
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@ -522,13 +522,13 @@ NEED_BL1 := yes
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include bl1/bl1.mk
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endif
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# For AArch32, BL31 is not applicable, and BL2 & BL2U are not supported at present.
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ifneq (${ARCH},aarch32)
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ifdef BL2_SOURCES
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NEED_BL2 := yes
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include bl2/bl2.mk
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endif
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# For AArch32, BL31 is not applicable, and BL2U is not supported at present.
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ifneq (${ARCH},aarch32)
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ifdef BL2U_SOURCES
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NEED_BL2U := yes
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include bl2u/bl2u.mk
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@ -126,7 +126,7 @@ BL1_SOURCES += drivers/io/io_semihosting.c \
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BL2_SOURCES += drivers/io/io_semihosting.c \
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drivers/delay_timer/delay_timer.c \
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lib/semihosting/semihosting.c \
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lib/semihosting/aarch64/semihosting_call.S \
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lib/semihosting/${ARCH}/semihosting_call.S \
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plat/arm/board/fvp/fvp_bl2_setup.c \
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plat/arm/board/fvp/fvp_err.c \
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plat/arm/board/fvp/fvp_io_storage.c \
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106
plat/arm/common/aarch32/arm_bl2_mem_params_desc.c
Normal file
106
plat/arm/common/aarch32/arm_bl2_mem_params_desc.c
Normal file
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@ -0,0 +1,106 @@
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/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <bl_common.h>
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#include <desc_image_load.h>
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#include <platform.h>
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#include <platform_def.h>
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/*******************************************************************************
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* Following descriptor provides BL image/ep information that gets used
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* by BL2 to load the images and also subset of this information is
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* passed to next BL image. The image loading sequence is managed by
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* populating the images in required loading order. The image execution
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* sequence is managed by populating the `next_handoff_image_id` with
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* the next executable image id.
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******************************************************************************/
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static bl_mem_params_node_t bl2_mem_params_descs[] = {
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#ifdef SCP_BL2_BASE
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/* Fill SCP_BL2 related information if it exists */
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{
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.image_id = SCP_BL2_IMAGE_ID,
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SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY,
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VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
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SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
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VERSION_2, image_info_t, 0),
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.image_info.image_base = SCP_BL2_BASE,
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.image_info.image_max_size = PLAT_CSS_MAX_SCP_BL2_SIZE,
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.next_handoff_image_id = INVALID_IMAGE_ID,
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},
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#endif /* SCP_BL2_BASE */
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/* Fill BL32 related information */
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{
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.image_id = BL32_IMAGE_ID,
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SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
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VERSION_2, entry_point_info_t,
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SECURE | EXECUTABLE | EP_FIRST_EXE),
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.ep_info.pc = BL32_BASE,
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.ep_info.spsr = SPSR_MODE32(MODE32_mon, SPSR_T_ARM,
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SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS),
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SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
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VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP),
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.image_info.image_base = BL32_BASE,
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.image_info.image_max_size = BL32_LIMIT - BL32_BASE,
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.next_handoff_image_id = BL33_IMAGE_ID,
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},
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/* Fill BL33 related information */
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{
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.image_id = BL33_IMAGE_ID,
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SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
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VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE),
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#ifdef PRELOADED_BL33_BASE
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.ep_info.pc = PRELOADED_BL33_BASE,
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SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
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VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
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#else
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.ep_info.pc = PLAT_ARM_NS_IMAGE_OFFSET,
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SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
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VERSION_2, image_info_t, 0),
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.image_info.image_base = PLAT_ARM_NS_IMAGE_OFFSET,
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.image_info.image_max_size = ARM_DRAM1_SIZE,
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#endif /* PRELOADED_BL33_BASE */
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.next_handoff_image_id = INVALID_IMAGE_ID,
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}
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};
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REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs)
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@ -246,7 +246,12 @@ void arm_bl2_plat_arch_setup(void)
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BL2_COHERENT_RAM_LIMIT
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#endif
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);
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#ifdef AARCH32
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enable_mmu_secure(0);
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#else
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enable_mmu_el1(0);
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#endif
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}
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void bl2_plat_arch_setup(void)
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@ -266,9 +271,11 @@ int bl2_plat_handle_post_image_load(unsigned int image_id)
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assert(bl_mem_params);
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switch (image_id) {
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#ifdef AARCH64
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case BL32_IMAGE_ID:
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bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl32_entry();
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break;
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#endif
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case BL33_IMAGE_ID:
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/* BL33 expects to receive the primary CPU MPID (through r0) */
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@ -128,7 +128,7 @@ BL2_SOURCES += drivers/io/io_fip.c \
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drivers/io/io_storage.c \
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plat/arm/common/arm_bl2_setup.c \
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plat/arm/common/arm_io_storage.c \
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plat/common/aarch64/platform_up_stack.S
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plat/common/${ARCH}/platform_up_stack.S
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ifeq (${LOAD_IMAGE_V2},1)
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BL2_SOURCES += plat/arm/common/${ARCH}/arm_bl2_mem_params_desc.c\
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plat/arm/common/arm_image_load.c \
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