fix(cpus): workaround for Cortex-A510 erratum 2080326

Cortex-A510 erratum 2080326 is a Cat B erratum that applies
to all revisions <= r0p2 and is fixed in r0p3.
The workaround sequence helps perform a DSB after each TLBI
instruction and can be applied only for version r0p2 and has
minimal performance impact.
The workaround is not applicable for versions < r0p2.

SDEN documentation:
https://developer.arm.com/documentation/SDEN1873361/latest

Change-Id: Ib9bce8b711c25a79f7b2f891ae6f8b366fc80ddd
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

docs/design/cpu-specific-build-macros.rst

@@ -761,6 +761,11 @@ For Cortex-A510, the following errata build flags are defined :
    in r0p3. The issue is also present in r0p0 and r0p1 but there is no
    workaround for those revisions.
 
+-  ``ERRATA_A510_2080326``: This applies errata 2080326 workaround to
+   Cortex-A510 CPU. This needs to be enabled only for revision r0p2 and is
+   fixed in r0p3. This issue is also present in r0p0 and r0p1 but there is no
+   workaround for those revisions.
+
 -  ``ERRATA_A510_2250311``: This applies errata 2250311 workaround to
    Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2,
    r0p3 and r1p0, it is fixed in r1p1. This workaround disables MPMM even if

lib/cpus/aarch64/cortex_a510.S

@@ -57,6 +57,30 @@ workaround_reset_end cortex_a510, ERRATUM(2042739)
 
 check_erratum_ls cortex_a510, ERRATUM(2042739), CPU_REV(0, 2)
 
+workaround_reset_start cortex_a510, ERRATUM(2080326), ERRATA_A510_2080326
+	/* Apply workaround */
+	mov x0, #1
+	msr S3_6_C15_C4_0, x0
+	isb
+
+	mov x0, #0x0100
+	movk x0, #0x0E08, lsl #16
+	msr S3_6_C15_C4_2, x0
+
+	mov x0, #0x0300
+	movk x0, #0x0F1F, lsl #16
+	movk x0, #0x0008, lsl #32
+	msr S3_6_C15_C4_3, x0
+
+	mov x0, #0x03F1
+	movk x0, #0x00C0, lsl #16
+	msr S3_6_C15_C4_1, x0
+
+	isb
+workaround_reset_end cortex_a510, ERRATUM(2080326)
+
+check_erratum_range cortex_a510, ERRATUM(2080326), CPU_REV(0, 2), CPU_REV(0, 2)
+
 workaround_reset_start cortex_a510, ERRATUM(2172148), ERRATA_A510_2172148
 	/*
 	 * Force L2 allocation of transient lines by setting

lib/cpus/cpu-ops.mk

@@ -769,6 +769,11 @@ CPU_FLAG_LIST += ERRATA_A510_2042739
 # present in r0p0 and r0p1 but there is no workaround for those revisions.
 CPU_FLAG_LIST += ERRATA_A510_2041909
 
+# Flag to aply erratum 2080326 workaround during reset. This erratum applies
+# to revision r0p2 of the Cortex-A510 cpu and is fixed in r0p3. The issue is
+# also present in r0p0 and r0p1 but there is no workaround for those revisions.
+CPU_FLAG_LIST += ERRATA_A510_2080326
+
 # Flag to apply erratum 2250311 workaround during reset. This erratum applies
 # to revisions r0p0, r0p1, r0p2, r0p3 and r1p0, and is fixed in r1p1.
 CPU_FLAG_LIST += ERRATA_A510_2250311

services/std_svc/errata_abi/errata_abi_main.c

@@ -384,15 +384,16 @@ struct em_cpu_list cpu_list[] = {
 		[0] = {1922240, 0x00, 0x00, ERRATA_A510_1922240},
 		[1] = {2041909, 0x02, 0x02, ERRATA_A510_2041909},
 		[2] = {2042739, 0x00, 0x02, ERRATA_A510_2042739},
-		[3] = {2172148, 0x00, 0x10, ERRATA_A510_2172148},
-		[4] = {2218950, 0x00, 0x10, ERRATA_A510_2218950},
-		[5] = {2250311, 0x00, 0x10, ERRATA_A510_2250311},
-		[6] = {2288014, 0x00, 0x10, ERRATA_A510_2288014},
-		[7] = {2347730, 0x00, 0x11, ERRATA_A510_2347730},
-		[8] = {2371937, 0x00, 0x11, ERRATA_A510_2371937},
-		[9] = {2666669, 0x00, 0x11, ERRATA_A510_2666669},
-		[10] = {2684597, 0x00, 0x12, ERRATA_A510_2684597},
-		[11 ... ERRATA_LIST_END] = UNDEF_ERRATA,
+		[3] = {2080326, 0x02, 0x02, ERRATA_A510_2080326},
+		[4] = {2172148, 0x00, 0x10, ERRATA_A510_2172148},
+		[5] = {2218950, 0x00, 0x10, ERRATA_A510_2218950},
+		[6] = {2250311, 0x00, 0x10, ERRATA_A510_2250311},
+		[7] = {2288014, 0x00, 0x10, ERRATA_A510_2288014},
+		[8] = {2347730, 0x00, 0x11, ERRATA_A510_2347730},
+		[9] = {2371937, 0x00, 0x11, ERRATA_A510_2371937},
+		[10] = {2666669, 0x00, 0x11, ERRATA_A510_2666669},
+		[11] = {2684597, 0x00, 0x12, ERRATA_A510_2684597},
+		[12 ... ERRATA_LIST_END] = UNDEF_ERRATA,
 	}
 },
 #endif /* CORTEX_A510_H_INC */