From 6dacc272b090558cf12a52d3679f7d334a753631 Mon Sep 17 00:00:00 2001
From: Boyan Karatotev <boyan.karatotev@arm.com>
Date: Mon, 4 Dec 2023 16:12:08 +0000
Subject: [PATCH] refactor(tc): correlate secure world addresses with
platform_def
Similarly to the memory node in the NS device tree, platform_def already
defines all the necessary values to populate the spmc manifest and NS
related entries automatically. Use the macros directly so any changes
can propagate automatically.
The result of this is that TC3 and above get correct secure world
manifests automatically. They were previously broken.
One "breaking" change is that the FWU region moves. This should have
happened previously but it was missed when the secure portion of DRAM
was increased, leaving it in secure memory. This was caught when going
over the definitions and correlating them should prevent this in the
future.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I1415e402be8c70f5e22f28eabddcb53298c57a11
---
fdts/tc.dts | 8 ++++----
plat/arm/board/tc/fdts/tc_spmc_manifest.dtsi | 10 +++++++---
plat/arm/board/tc/include/platform_def.h | 10 ++++++++++
3 files changed, 21 insertions(+), 7 deletions(-)
diff --git a/fdts/tc.dts b/fdts/tc.dts
index 4b601894b..63f6c3dd7 100644
--- a/fdts/tc.dts
+++ b/fdts/tc.dts
@@ -337,13 +337,13 @@
linux,cma-default;
};
- optee@f8e00000 {
+ optee {
compatible = "restricted-dma-pool";
- reg = <0x00000000 0xf8e00000 0 0x00200000>;
+ reg = <0x0 TC_NS_OPTEE_BASE 0x0 TC_NS_OPTEE_SIZE>;
};
- fwu_mm@fca00000 {
- reg = <0x00000000 0xfca00000 0 0x00400000>;
+ fwu_mm {
+ reg = <0x0 TC_NS_FWU_BASE 0x0 TC_NS_FWU_SIZE>;
no-map;
};
};
diff --git a/plat/arm/board/tc/fdts/tc_spmc_manifest.dtsi b/plat/arm/board/tc/fdts/tc_spmc_manifest.dtsi
index 045bba5ad..3bc0cbb43 100644
--- a/plat/arm/board/tc/fdts/tc_spmc_manifest.dtsi
+++ b/plat/arm/board/tc/fdts/tc_spmc_manifest.dtsi
@@ -3,6 +3,8 @@
*
* SPDX-License-Identifier: BSD-3-Clause
*/
+#include <platform_def.h>
+
/ {
compatible = "arm,ffa-core-manifest-1.0";
#address-cells = <2>;
@@ -88,9 +90,10 @@
};
};
+ /* the full secure world range */
memory@0 {
device_type = "memory";
- reg = <0x0 0xf9000000 0x0 0x6000000>,
+ reg = <0x0 TC_TZC_DRAM1_BASE 0x0 TC_TZC_DRAM1_SIZE>,
<0x0 0xff000000 0x0 0x1000000>;
};
@@ -100,7 +103,8 @@
#ifdef TS_SP_FW_CONFIG
<0x0 0x08000000 0x0 0x4000000>,
#endif /* TS_SP_FW_CONFIG */
- <0x0 0x80000000 0x0 0x79000000>,
- <0x80 0x80000000 0x1 0x80000000>;
+ <0x0 TC_NS_DRAM1_BASE 0x0 TC_NS_DRAM1_SIZE>,
+ <HI(PLAT_ARM_DRAM2_BASE) LO(PLAT_ARM_DRAM2_BASE)
+ HI(TC_NS_DRAM2_SIZE) LO(TC_NS_DRAM2_SIZE)>;
};
};
diff --git a/plat/arm/board/tc/include/platform_def.h b/plat/arm/board/tc/include/platform_def.h
index 86fbf4936..130111ede 100644
--- a/plat/arm/board/tc/include/platform_def.h
+++ b/plat/arm/board/tc/include/platform_def.h
@@ -28,6 +28,12 @@
* - Region to load secure partitions
*
*
+ * 0xf8a0_0000 ------------------ TC_NS_FWU_BASE
+ * | FWU shmem |
+ * | (4MB) |
+ * 0xf8e0_0000 ------------------ TC_NS_OPTEE_BASE
+ * | OP-TEE shmem |
+ * | (2MB) |
* 0xF900_0000 ------------------ TC_TZC_DRAM1_BASE
* | |
* | SPMC |
@@ -54,6 +60,10 @@
TC_TZC_DRAM1_SIZE)
#define TC_NS_DRAM1_END (TC_NS_DRAM1_BASE + TC_NS_DRAM1_SIZE - 1)
+#define TC_NS_OPTEE_SIZE (2 * SZ_1M)
+#define TC_NS_OPTEE_BASE (TC_NS_DRAM1_BASE + TC_NS_DRAM1_SIZE - TC_NS_OPTEE_SIZE)
+#define TC_NS_FWU_SIZE (4 * SZ_1M)
+#define TC_NS_FWU_BASE (TC_NS_OPTEE_BASE - TC_NS_FWU_SIZE)
/*
* Mappings for TC DRAM1 (non-secure) and TC TZC DRAM1 (secure)