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fix(security): add CVE-2024-7881 mitigation to Cortex-X4
This patch mitigates CVE-2024-7881 [1] by setting CPUACTLR6_EL1[41] to 1 for Cortex-X4 CPU. [1]: https://developer.arm.com/Arm%20Security%20Center/Arm%20CPU%20Vulnerability%20CVE-2024-7881 Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com> Change-Id: I0bec96d4f71a08a89c6612e272ecfb173f80da20
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2 changed files with 18 additions and 2 deletions
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2022-2024, Arm Limited. All rights reserved.
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* Copyright (c) 2022-2025, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -36,6 +36,11 @@
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#define CORTEX_X4_CPUACTLR5_EL1 S3_0_C15_C8_0
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#define CORTEX_X4_CPUACTLR5_EL1_BIT_14 (ULL(1) << 14)
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/*******************************************************************************
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* CPU Auxiliary control register 6 specific definitions
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******************************************************************************/
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#define CORTEX_X4_CPUACTLR6_EL1 S3_0_C15_C8_1
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#ifndef __ASSEMBLER__
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#if ERRATA_X4_2726228
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long check_erratum_cortex_x4_2726228(long cpu_rev);
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2022-2024, Arm Limited. All rights reserved.
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* Copyright (c) 2022-2025, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -108,6 +108,17 @@ workaround_reset_end cortex_x4, CVE(2022, 23960)
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check_erratum_chosen cortex_x4, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
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workaround_reset_start cortex_x4, CVE(2024, 7881), WORKAROUND_CVE_2024_7881
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/* ---------------------------------
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* Sets BIT41 of CPUACTLR6_EL1 which
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* disables L1 Data cache prefetcher
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* ---------------------------------
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*/
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sysreg_bit_set CORTEX_X4_CPUACTLR6_EL1, BIT(41)
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workaround_reset_end cortex_x4, CVE(2024, 7881)
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check_erratum_chosen cortex_x4, CVE(2024, 7881), WORKAROUND_CVE_2024_7881
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cpu_reset_func_start cortex_x4
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/* Disable speculative loads */
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msr SSBS, xzr
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