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fix(security): add CVE-2024-7881 mitigation to Cortex-X4

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This patch mitigates CVE-2024-7881 [1] by setting CPUACTLR6_EL1[41] to 1
for Cortex-X4 CPU.

[1]: https://developer.arm.com/Arm%20Security%20Center/Arm%20CPU%20Vulnerability%20CVE-2024-7881

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I0bec96d4f71a08a89c6612e272ecfb173f80da20
This commit is contained in:
Arvind Ram Prakash 2024-09-06 12:18:51 -05:00
parent 2372179484
commit 6ce6acac91
2 changed files with 18 additions and 2 deletions
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7
include/lib/cpus/aarch64/cortex_x4.h
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2022-2024, Arm Limited. All rights reserved. * Copyright (c) 2022-2025, Arm Limited. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -36,6 +36,11 @@
#define CORTEX_X4_CPUACTLR5_EL1 S3_0_C15_C8_0 #define CORTEX_X4_CPUACTLR5_EL1 S3_0_C15_C8_0
#define CORTEX_X4_CPUACTLR5_EL1_BIT_14 (ULL(1) << 14) #define CORTEX_X4_CPUACTLR5_EL1_BIT_14 (ULL(1) << 14)
/*******************************************************************************
* CPU Auxiliary control register 6 specific definitions
******************************************************************************/
#define CORTEX_X4_CPUACTLR6_EL1 S3_0_C15_C8_1
#ifndef __ASSEMBLER__ #ifndef __ASSEMBLER__
#if ERRATA_X4_2726228 #if ERRATA_X4_2726228
long check_erratum_cortex_x4_2726228(long cpu_rev); long check_erratum_cortex_x4_2726228(long cpu_rev);

13
lib/cpus/aarch64/cortex_x4.S
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2022-2024, Arm Limited. All rights reserved. * Copyright (c) 2022-2025, Arm Limited. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -108,6 +108,17 @@ workaround_reset_end cortex_x4, CVE(2022, 23960)
check_erratum_chosen cortex_x4, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 check_erratum_chosen cortex_x4, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
workaround_reset_start cortex_x4, CVE(2024, 7881), WORKAROUND_CVE_2024_7881
/* ---------------------------------
* Sets BIT41 of CPUACTLR6_EL1 which
* disables L1 Data cache prefetcher
* ---------------------------------
*/
sysreg_bit_set CORTEX_X4_CPUACTLR6_EL1, BIT(41)
workaround_reset_end cortex_x4, CVE(2024, 7881)
check_erratum_chosen cortex_x4, CVE(2024, 7881), WORKAROUND_CVE_2024_7881
cpu_reset_func_start cortex_x4 cpu_reset_func_start cortex_x4
/* Disable speculative loads */ /* Disable speculative loads */
msr SSBS, xzr msr SSBS, xzr