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Merge "fix(mte): remove CTX_INCLUDE_MTE_REGS usage" into integration

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This commit is contained in:
Manish V Badarkhe 2024-01-25 17:59:33 +01:00 • committed by TrustedFirmware Code Review
commit 6c74b55637
2 changed files with 24 additions and 8 deletions
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25
lib/el3_runtime/aarch64/context.S
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved. * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -107,7 +107,12 @@ func el1_sysregs_context_save
#endif /* NS_TIMER_SWITCH */ #endif /* NS_TIMER_SWITCH */
/* Save MTE system registers if the build has instructed so */ /* Save MTE system registers if the build has instructed so */
#if CTX_INCLUDE_MTE_REGS #if ENABLE_FEAT_MTE
#if ENABLE_FEAT_MTE == 2
mrs x8, id_aa64pfr1_el1
and x8, x8, #(ID_AA64PFR1_EL1_MTE_MASK << ID_AA64PFR1_EL1_MTE_SHIFT)
cbz x8, no_mte_save
#endif
mrs x15, TFSRE0_EL1 mrs x15, TFSRE0_EL1
mrs x16, TFSR_EL1 mrs x16, TFSR_EL1
stp x15, x16, [x0, #CTX_TFSRE0_EL1] stp x15, x16, [x0, #CTX_TFSRE0_EL1]
@ -115,7 +120,9 @@ func el1_sysregs_context_save
mrs x9, RGSR_EL1 mrs x9, RGSR_EL1
mrs x10, GCR_EL1 mrs x10, GCR_EL1
stp x9, x10, [x0, #CTX_RGSR_EL1] stp x9, x10, [x0, #CTX_RGSR_EL1]
#endif /* CTX_INCLUDE_MTE_REGS */
no_mte_save:
#endif /* ENABLE_FEAT_MTE */
ret ret
endfunc el1_sysregs_context_save endfunc el1_sysregs_context_save
@ -206,7 +213,13 @@ func el1_sysregs_context_restore
#endif /* NS_TIMER_SWITCH */ #endif /* NS_TIMER_SWITCH */
/* Restore MTE system registers if the build has instructed so */ /* Restore MTE system registers if the build has instructed so */
#if CTX_INCLUDE_MTE_REGS #if ENABLE_FEAT_MTE
#if ENABLE_FEAT_MTE == 2
mrs x8, id_aa64pfr1_el1
and x8, x8, #(ID_AA64PFR1_EL1_MTE_MASK << ID_AA64PFR1_EL1_MTE_SHIFT)
cbz x8, no_mte_restore
#endif
ldp x11, x12, [x0, #CTX_TFSRE0_EL1] ldp x11, x12, [x0, #CTX_TFSRE0_EL1]
msr TFSRE0_EL1, x11 msr TFSRE0_EL1, x11
msr TFSR_EL1, x12 msr TFSR_EL1, x12
@ -214,7 +227,9 @@ func el1_sysregs_context_restore
ldp x13, x14, [x0, #CTX_RGSR_EL1] ldp x13, x14, [x0, #CTX_RGSR_EL1]
msr RGSR_EL1, x13 msr RGSR_EL1, x13
msr GCR_EL1, x14 msr GCR_EL1, x14
#endif /* CTX_INCLUDE_MTE_REGS */
no_mte_restore:
#endif /* ENABLE_FEAT_MTE */
/* No explict ISB required here as ERET covers it */ /* No explict ISB required here as ERET covers it */
ret ret

7
lib/el3_runtime/aarch64/context_mgmt.c
View file

@ -1333,9 +1333,10 @@ void cm_el2_sysregs_context_restore(uint32_t security_state)
el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); el2_sysregs_ctx = get_el2_sysregs_ctx(ctx);
el2_sysregs_context_restore_common(el2_sysregs_ctx); el2_sysregs_context_restore_common(el2_sysregs_ctx);
#if CTX_INCLUDE_MTE_REGS
write_tfsr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TFSR_EL2)); if (is_feat_mte_supported()) {
#endif write_tfsr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TFSR_EL2));
}
#if CTX_INCLUDE_MPAM_REGS #if CTX_INCLUDE_MPAM_REGS
if (is_feat_mpam_supported()) { if (is_feat_mpam_supported()) {