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feat(smmu): add SMMU abort transaction function

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Created a function to abort all pending NS DMA transactions to
engage complete DMA protection. This call will be used by the
subsequent DRTM implementation changes.

Signed-off-by: Manish V Badarkhe <manish.badarkhe@arm.com>
Signed-off-by: Lucian Paul-Trifu <lucian.paultrifu@gmail.com>
Change-Id: I94992b54c570327d6746295073822a9c0ebdc85d
This commit is contained in:
Lucian Paul-Trifu 2022-03-25 14:30:20 +00:00 • committed by Manish V Badarkhe
parent 859eabd4c4
commit 6c5c532051
2 changed files with 33 additions and 1 deletions
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27
drivers/arm/smmu/smmu_v3.c
View file

@ -14,7 +14,7 @@
/* SMMU poll number of retries */ /* SMMU poll number of retries */
#define SMMU_POLL_TIMEOUT_US U(1000) #define SMMU_POLL_TIMEOUT_US U(1000)
static int __init smmuv3_poll(uintptr_t smmu_reg, uint32_t mask, static int smmuv3_poll(uintptr_t smmu_reg, uint32_t mask,
uint32_t value) uint32_t value)
{ {
uint32_t reg_val; uint32_t reg_val;
@ -155,3 +155,28 @@ int __init smmuv3_init(uintptr_t smmu_base)
return smmuv3_poll(smmu_base + SMMU_S_INIT, return smmuv3_poll(smmu_base + SMMU_S_INIT,
SMMU_S_INIT_INV_ALL, 0U); SMMU_S_INIT_INV_ALL, 0U);
} }
int smmuv3_ns_set_abort_all(uintptr_t smmu_base)
{
/* Attribute update has completed when SMMU_GBPA.Update bit is 0 */
if (smmuv3_poll(smmu_base + SMMU_GBPA, SMMU_GBPA_UPDATE, 0U) != 0U) {
return -1;
}
/*
* Set GBPA's ABORT bit. Other GBPA fields are presumably ignored then,
* so simply preserve their value.
*/
mmio_setbits_32(smmu_base + SMMU_GBPA, SMMU_GBPA_UPDATE | SMMU_GBPA_ABORT);
if (smmuv3_poll(smmu_base + SMMU_GBPA, SMMU_GBPA_UPDATE, 0U) != 0U) {
return -1;
}
/* Disable the SMMU to engage the GBPA fields previously configured. */
mmio_clrbits_32(smmu_base + SMMU_CR0, SMMU_CR0_SMMUEN);
if (smmuv3_poll(smmu_base + SMMU_CR0ACK, SMMU_CR0_SMMUEN, 0U) != 0U) {
return -1;
}
return 0;
}

7
include/drivers/arm/smmu_v3.h
View file

@ -12,6 +12,8 @@
#include <platform_def.h> #include <platform_def.h>
/* SMMUv3 register offsets from device base */ /* SMMUv3 register offsets from device base */
#define SMMU_CR0 U(0x0020)
#define SMMU_CR0ACK U(0x0024)
#define SMMU_GBPA U(0x0044) #define SMMU_GBPA U(0x0044)
#define SMMU_S_IDR1 U(0x8004) #define SMMU_S_IDR1 U(0x8004)
#define SMMU_S_INIT U(0x803c) #define SMMU_S_INIT U(0x803c)
@ -37,6 +39,9 @@
#endif /* ENABLE_RME */ #endif /* ENABLE_RME */
/* SMMU_CR0 and SMMU_CR0ACK register fields */
#define SMMU_CR0_SMMUEN (1UL << 0)
/* SMMU_GBPA register fields */ /* SMMU_GBPA register fields */
#define SMMU_GBPA_UPDATE (1UL << 31) #define SMMU_GBPA_UPDATE (1UL << 31)
#define SMMU_GBPA_ABORT (1UL << 20) #define SMMU_GBPA_ABORT (1UL << 20)
@ -61,4 +66,6 @@
int smmuv3_init(uintptr_t smmu_base); int smmuv3_init(uintptr_t smmu_base);
int smmuv3_security_init(uintptr_t smmu_base); int smmuv3_security_init(uintptr_t smmu_base);
int smmuv3_ns_set_abort_all(uintptr_t smmu_base);
#endif /* SMMU_V3_H */ #endif /* SMMU_V3_H */