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feat(tc): add MHUv3 DT binding for TC3

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MHUv3's device tree is different from MHUv2's. Add support MHUv3 DT
binding for TC3 while keeping TC2 as-is.

Change-Id: Ib2f55d3a64a4cfe2ea9e62fe39d27ed54a2ca007
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
This commit is contained in:
Boyan Karatotev 2024-04-24 10:09:18 +01:00 • committed by Leo Yan
parent 4f65c0beaa
commit 6c069e7168
3 changed files with 27 additions and 11 deletions
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18
fdts/tc-base.dtsi
View file

@ -285,22 +285,22 @@
};
mbox_db_rx: mhu@MHU_RX_ADDR {
compatible = "arm,mhuv2-rx","arm,primecell";
reg = <0x0 ADDRESSIFY(MHU_RX_ADDR) 0x0 0x1000>;
compatible = MHU_RX_COMPAT;
reg = <0x0 ADDRESSIFY(MHU_RX_ADDR) 0x0 MHU_OFFSET>;
clocks = <&soc_refclk>;
clock-names = "apb_pclk";
#mbox-cells = <2>;
interrupts = <GIC_SPI INT_MBOX_RX IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mhu_rx";
#mbox-cells = <MHU_MBOX_CELLS>;
interrupts = <GIC_SPI MHU_RX_INT_NUM IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = MHU_RX_INT_NAME;
};
mbox_db_tx: mhu@MHU_TX_ADDR {
compatible = "arm,mhuv2-tx","arm,primecell";
reg = <0x0 ADDRESSIFY(MHU_TX_ADDR) 0x0 0x1000>;
compatible = MHU_TX_COMPAT;
reg = <0x0 ADDRESSIFY(MHU_TX_ADDR) 0x0 MHU_OFFSET>;
clocks = <&soc_refclk>;
clock-names = "apb_pclk";
#mbox-cells = <2>;
interrupt-names = "mhu_tx";
#mbox-cells = <MHU_MBOX_CELLS>;
interrupt-names = MHU_TX_INT_NAME;
};
firmware {

10
fdts/tc2.dts
View file

@ -20,9 +20,17 @@
#endif /* TARGET_FLAVOUR_FPGA */
#define BIG_CAPACITY 1024
#define INT_MBOX_RX 317
#define MHU_TX_ADDR 45000000 /* hex */
#define MHU_TX_COMPAT "arm,mhuv2-tx","arm,primecell"
#define MHU_TX_INT_NAME "mhu_tx"
#define MHU_RX_ADDR 45010000 /* hex */
#define MHU_RX_COMPAT "arm,mhuv2-rx","arm,primecell"
#define MHU_OFFSET 0x1000
#define MHU_MBOX_CELLS 2
#define MHU_RX_INT_NUM 317
#define MHU_RX_INT_NAME "mhu_rx"
#define MPAM_ADDR 0x1 0x00010000 /* 0x1_0001_0000 */
#define UARTCLK_FREQ 5000000

10
fdts/tc3.dts
View file

@ -14,9 +14,17 @@
#define MID_CAPACITY 686
#define BIG_CAPACITY 1024
#define INT_MBOX_RX 300
#define MHU_TX_ADDR 46040000 /* hex */
#define MHU_TX_COMPAT "arm,mhuv3"
#define MHU_TX_INT_NAME ""
#define MHU_RX_ADDR 46140000 /* hex */
#define MHU_RX_COMPAT "arm,mhuv3"
#define MHU_OFFSET 0x10000
#define MHU_MBOX_CELLS 3
#define MHU_RX_INT_NUM 300
#define MHU_RX_INT_NAME "combined-mbx"
#define MPAM_ADDR 0x0 0x5f010000 /* 0x5f01_0000 */
#define UARTCLK_FREQ 3750000