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PSCI: Fix MISRA defects in common and setup code
MISRA C-2012 Rules 10.1, 10.3, 17.8 and 20.7. Change-Id: I3980bd2a1d845559af4bbe2887a0250d0506a064 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
This commit is contained in:
Antonio Nino Diaz
parent
abce1dce8b
commit
6b7b0f3686
6 changed files with 214 additions and 164 deletions
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -32,9 +32,9 @@ unsigned int psci_caps;
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* Function which initializes the 'psci_non_cpu_pd_nodes' or the
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* 'psci_cpu_pd_nodes' corresponding to the power level.
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******************************************************************************/
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static void psci_init_pwr_domain_node(unsigned int node_idx,
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static void psci_init_pwr_domain_node(unsigned char node_idx,
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unsigned int parent_idx,
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unsigned int level)
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unsigned char level)
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{
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if (level > PSCI_CPU_PWR_LVL) {
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psci_non_cpu_pd_nodes[node_idx].level = level;
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@ -82,15 +82,15 @@ static void psci_init_pwr_domain_node(unsigned int node_idx,
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*******************************************************************************/
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static void psci_update_pwrlvl_limits(void)
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{
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int j;
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int j, cpu_idx;
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unsigned int nodes_idx[PLAT_MAX_PWR_LVL] = {0};
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unsigned int temp_index[PLAT_MAX_PWR_LVL], cpu_idx;
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unsigned int temp_index[PLAT_MAX_PWR_LVL];
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for (cpu_idx = 0; cpu_idx < PLATFORM_CORE_COUNT; cpu_idx++) {
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psci_get_parent_pwr_domain_nodes(cpu_idx,
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PLAT_MAX_PWR_LVL,
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(unsigned int)PLAT_MAX_PWR_LVL,
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temp_index);
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for (j = PLAT_MAX_PWR_LVL - 1; j >= 0; j--) {
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for (j = (int) PLAT_MAX_PWR_LVL - 1; j >= 0; j--) {
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if (temp_index[j] != nodes_idx[j]) {
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nodes_idx[j] = temp_index[j];
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psci_non_cpu_pd_nodes[nodes_idx[j]].cpu_start_idx
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@ -109,9 +109,10 @@ static void psci_update_pwrlvl_limits(void)
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******************************************************************************/
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static void populate_power_domain_tree(const unsigned char *topology)
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{
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unsigned int i, j = 0, num_nodes_at_lvl = 1, num_nodes_at_next_lvl;
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unsigned int node_index = 0, parent_node_index = 0, num_children;
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int level = PLAT_MAX_PWR_LVL;
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unsigned int i, j = 0U, num_nodes_at_lvl = 1U, num_nodes_at_next_lvl;
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unsigned int node_index = 0U, num_children;
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int parent_node_index = 0;
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int level = (int) PLAT_MAX_PWR_LVL;
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/*
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* For each level the inputs are:
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@ -122,8 +123,8 @@ static void populate_power_domain_tree(const unsigned char *topology)
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* - Index of first free entry in psci_non_cpu_pd_nodes[] or
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* psci_cpu_pd_nodes[] i.e. node_index depending upon the level.
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*/
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while (level >= PSCI_CPU_PWR_LVL) {
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num_nodes_at_next_lvl = 0;
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while (level >= (int) PSCI_CPU_PWR_LVL) {
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num_nodes_at_next_lvl = 0U;
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/*
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* For each entry (parent node) at this level in the plat_array:
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* - Find the number of children
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@ -132,16 +133,16 @@ static void populate_power_domain_tree(const unsigned char *topology)
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* - Increment parent_node_index to point to the next parent
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* - Accumulate the number of children at next level.
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*/
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for (i = 0; i < num_nodes_at_lvl; i++) {
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for (i = 0U; i < num_nodes_at_lvl; i++) {
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assert(parent_node_index <=
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PSCI_NUM_NON_CPU_PWR_DOMAINS);
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num_children = topology[parent_node_index];
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for (j = node_index;
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j < node_index + num_children; j++)
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psci_init_pwr_domain_node(j,
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j < (node_index + num_children); j++)
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psci_init_pwr_domain_node((unsigned char)j,
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parent_node_index - 1,
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level);
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(unsigned char)level);
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node_index = j;
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num_nodes_at_next_lvl += num_children;
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@ -152,12 +153,12 @@ static void populate_power_domain_tree(const unsigned char *topology)
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level--;
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/* Reset the index for the cpu power domain array */
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if (level == PSCI_CPU_PWR_LVL)
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if (level == (int) PSCI_CPU_PWR_LVL)
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node_index = 0;
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}
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/* Validate the sanity of array exported by the platform */
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assert(j == PLATFORM_CORE_COUNT);
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assert((int) j == PLATFORM_CORE_COUNT);
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}
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/*******************************************************************************
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@ -213,8 +214,9 @@ int psci_setup(const psci_lib_args_t *lib_args)
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*/
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psci_set_pwr_domains_to_run(PLAT_MAX_PWR_LVL);
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plat_setup_psci_ops((uintptr_t)lib_args->mailbox_ep, &psci_plat_pm_ops);
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assert(psci_plat_pm_ops);
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(void) plat_setup_psci_ops((uintptr_t)lib_args->mailbox_ep,
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&psci_plat_pm_ops);
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assert(psci_plat_pm_ops != NULL);
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/*
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* Flush `psci_plat_pm_ops` as it will be accessed by secondary CPUs
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@ -226,29 +228,29 @@ int psci_setup(const psci_lib_args_t *lib_args)
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/* Initialize the psci capability */
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psci_caps = PSCI_GENERIC_CAP;
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if (psci_plat_pm_ops->pwr_domain_off)
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if (psci_plat_pm_ops->pwr_domain_off != NULL)
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psci_caps |= define_psci_cap(PSCI_CPU_OFF);
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if (psci_plat_pm_ops->pwr_domain_on &&
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psci_plat_pm_ops->pwr_domain_on_finish)
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if ((psci_plat_pm_ops->pwr_domain_on != NULL) &&
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(psci_plat_pm_ops->pwr_domain_on_finish != NULL))
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psci_caps |= define_psci_cap(PSCI_CPU_ON_AARCH64);
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if (psci_plat_pm_ops->pwr_domain_suspend &&
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psci_plat_pm_ops->pwr_domain_suspend_finish) {
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if ((psci_plat_pm_ops->pwr_domain_suspend != NULL) &&
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(psci_plat_pm_ops->pwr_domain_suspend_finish != NULL)) {
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psci_caps |= define_psci_cap(PSCI_CPU_SUSPEND_AARCH64);
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if (psci_plat_pm_ops->get_sys_suspend_power_state)
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if (psci_plat_pm_ops->get_sys_suspend_power_state != NULL)
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psci_caps |= define_psci_cap(PSCI_SYSTEM_SUSPEND_AARCH64);
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}
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if (psci_plat_pm_ops->system_off)
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if (psci_plat_pm_ops->system_off != NULL)
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psci_caps |= define_psci_cap(PSCI_SYSTEM_OFF);
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if (psci_plat_pm_ops->system_reset)
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if (psci_plat_pm_ops->system_reset != NULL)
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psci_caps |= define_psci_cap(PSCI_SYSTEM_RESET);
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if (psci_plat_pm_ops->get_node_hw_state)
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if (psci_plat_pm_ops->get_node_hw_state != NULL)
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psci_caps |= define_psci_cap(PSCI_NODE_HW_STATE_AARCH64);
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if (psci_plat_pm_ops->read_mem_protect &&
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psci_plat_pm_ops->write_mem_protect)
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if ((psci_plat_pm_ops->read_mem_protect != NULL) &&
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(psci_plat_pm_ops->write_mem_protect != NULL))
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psci_caps |= define_psci_cap(PSCI_MEM_PROTECT);
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if (psci_plat_pm_ops->mem_protect_chk)
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if (psci_plat_pm_ops->mem_protect_chk != NULL)
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psci_caps |= define_psci_cap(PSCI_MEM_CHK_RANGE_AARCH64);
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if (psci_plat_pm_ops->system_reset2)
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if (psci_plat_pm_ops->system_reset2 != NULL)
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psci_caps |= define_psci_cap(PSCI_SYSTEM_RESET2_AARCH64);
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#if ENABLE_PSCI_STAT
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@ -266,7 +268,7 @@ int psci_setup(const psci_lib_args_t *lib_args)
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******************************************************************************/
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void psci_arch_setup(void)
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{
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#if ARM_ARCH_MAJOR > 7 || defined(ARMV7_SUPPORTS_GENERIC_TIMER)
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#if (ARM_ARCH_MAJOR > 7) || defined(ARMV7_SUPPORTS_GENERIC_TIMER)
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/* Program the counter frequency */
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write_cntfrq_el0(plat_get_syscnt_freq2());
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#endif
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