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Release v1.3: update change-log.md
Updated change-log.md with summary of changes since release v1.2. Change-Id: Ia1e18ff4b0da567cf12dfcb53e6317e995100bdf
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David Cunado
Dan Handley
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commit
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1 changed files with 234 additions and 1 deletions
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ARM Trusted Firmware - version 1.3
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==================================
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New features
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------------
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* Added support for running Trusted Firmware in AArch32 execution state.
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The PSCI library has been refactored to allow integration with **EL3 Runtime
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Software**. This is software that is executing at the highest secure
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privilege which is EL3 in AArch64 or Secure SVC/Monitor mode in AArch32. See
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[PSCI Integration Guide].
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Included is a minimal AArch32 Secure Payload, **SP-MIN**, that illustrates
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the usage and integration of the PSCI library with EL3 Runtime Software
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running in AArch32 state.
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Booting to the BL1/BL2 images as well as booting straight to the Secure
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Payload is supported.
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* Improvements to the initialization framework for the PSCI service and ARM
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Standard Services in general.
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The PSCI service is now initialized as part of ARM Standard Service
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initialization. This consolidates the initializations of any ARM Standard
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Service that may be added in the future.
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A new function `get_arm_std_svc_args()` is introduced to get arguments
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corresponding to each standard service and must be implemented by the EL3
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Runtime Software.
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For PSCI, a new versioned structure `psci_lib_args_t` is introduced to
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initialize the PSCI Library. **Note** this is a compatibility break due to
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the change in the prototype of `psci_setup()`.
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* To support AArch32 builds of BL1 and BL2, implemented a new, alternative
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firmware image loading mechanism that adds flexibility.
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The current mechanism has a hard-coded set of images and execution order
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(BL31, BL32, etc). The new mechanism is data-driven by a list of image
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descriptors provided by the platform code.
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ARM platforms have been updated to support the new loading mechanism.
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The new mechanism is enabled by a build flag (`LOAD_IMAGE_V2`) which is
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currently off by default for the AArch64 build.
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**Note** `TRUSTED_BOARD_BOOT` is currently not supported when
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`LOAD_IMAGE_V2` is enabled.
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* Updated requirements for making contributions to ARM TF.
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Commits now must have a 'Signed-off-by:' field to certify that the
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contribution has been made under the terms of the
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[Developer Certificate of Origin].
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A signed CLA is no longer required.
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The [Contribution Guide] has been updated to reflect this change.
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* Introduced Performance Measurement Framework (PMF) which provides support
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for capturing, storing, dumping and retrieving time-stamps to measure the
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execution time of critical paths in the firmware. This relies on defining
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fixed sample points at key places in the code.
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* To support the QEMU platform port, imported libfdt v1.4.1 from
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https://git.kernel.org/cgit/utils/dtc/dtc.git
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* Updated PSCI support:
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* Added support for PSCI NODE_HW_STATE API for ARM platforms.
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* New optional platform hook, `pwr_domain_pwr_down_wfi()`, in
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`plat_psci_ops` to enable platforms to perform platform-specific actions
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needed to enter powerdown, including the 'wfi' invocation.
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* PSCI STAT residency and count functions have been added on ARM platforms
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by using PMF.
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* Enhancements to the translation table library:
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* Limited memory mapping support for region overlaps to only allow regions
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to overlap that are identity mapped or have the same virtual to physical
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address offset, and overlap completely but must not cover the same area.
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This limitation will enable future enhancements without having to
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support complex edge cases that may not be necessary.
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* The initial translation lookup level is now inferred from the virtual
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address space size. Previously, it was hard-coded.
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* Added support for mapping Normal, Inner Non-cacheable, Outer
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Non-cacheable memory in the translation table library.
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This can be useful to map a non-cacheable memory region, such as a DMA
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buffer.
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* Introduced the MT_EXECUTE/MT_EXECUTE_NEVER memory mapping attributes to
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specify the access permissions for instruction execution of a memory
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region.
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* Enabled support to isolate code and read-only data on separate memory pages,
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allowing independent access control to be applied to each.
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* Enabled SCR_EL3.SIF (Secure Instruction Fetch) bit in BL1 and BL31 common
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architectural setup code, preventing fetching instructions from non-secure
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memory when in secure state.
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* Enhancements to FIP support:
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* Replaced `fip_create` with `fiptool` which provides a more consistent
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and intuitive interface as well as additional support to remove an image
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from a FIP file.
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* Enabled printing the SHA256 digest with info command, allowing quick
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verification of an image within a FIP without having to extract the
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image and running sha256sum on it.
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* Added support for unpacking the contents of an existing FIP file into
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the working directory.
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* Aligned command line options for specifying images to use same naming
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convention as specified by TBBR and already used in cert_create tool.
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* Refactored the TZC-400 driver to also support memory controllers that
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integrate TZC functionality, for example ARM CoreLink DMC-500. Also added
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DMC-500 specific support.
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* Implemented generic delay timer based on the system generic counter and
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migrated all platforms to use it.
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* Enhanced support for ARM platforms:
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* Updated image loading support to make SCP images (SCP_BL2 and SCP_BL2U)
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optional.
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* Enhanced topology description support to allow multi-cluster topology
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definitions.
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* Added interconnect abstraction layer to help platform ports select the
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right interconnect driver, CCI or CCN, for the platform.
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* Added support to allow loading BL31 in the TZC-secured DRAM instead of
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the default secure SRAM.
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* Added support to use a System Security Control (SSC) Registers Unit
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enabling ARM TF to be compiled to support multiple ARM platforms and
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then select one at runtime.
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* Restricted mapping of Trusted ROM in BL1 to what is actually needed by
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BL1 rather than entire Trusted ROM region.
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* Flash is now mapped as execute-never by default. This increases security
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by restricting the executable region to what is strictly needed.
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* Applied following erratum workarounds for Cortex-A57: 833471, 826977,
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829520, 828024 and 826974.
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* Added support for Mediatek MT6795 platform.
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* Added support for QEMU virtualization ARMv8-A target.
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* Added support for Rockchip RK3368 and RK3399 platforms.
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* Added support for Xilinx Zynq UltraScale+ MPSoC platform.
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* Added support for ARM Cortex-A73 MPCore Processor.
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* Added support for ARM Cortex-A72 processor.
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* Added support for ARM Cortex-A35 processor.
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* Added support for ARM Cortex-A32 MPCore Processor.
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* Enabled preloaded BL33 alternative boot flow, in which BL2 does not load
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BL33 from non-volatile storage and BL31 hands execution over to a preloaded
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BL33. The User Guide has been updated with an example of how to use this
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option with a bootwrapped kernel.
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* Added support to build ARM TF on a Windows-based host machine.
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* Updated Trusted Board Boot prototype implementation:
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* Enabled the ability for a production ROM with TBBR enabled to boot test
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software before a real ROTPK is deployed (e.g. manufacturing mode).
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Added support to use ROTPK in certificate without verifying against the
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platform value when `ROTPK_NOT_DEPLOYED` bit is set.
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* Added support for non-volatile counter authentication to the
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Authentication Module to protect against roll-back.
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* Updated GICv3 support:
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* Enabled processor power-down and automatic power-on using GICv3.
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* Enabled G1S or G0 interrupts to be configured independently.
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* Changed FVP default interrupt driver to be the GICv3-only driver.
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**Note** the default build of Trusted Firmware will not be able to boot
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Linux kernel with GICv2 FDT blob.
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* Enabled wake-up from CPU_SUSPEND to stand-by by temporarily re-routing
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interrupts and then restoring after resume.
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Issues resolved since last release
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----------------------------------
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Known issues
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------------
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* The version of the AEMv8 Base FVP used in this release resets the model
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instead of terminating its execution in response to a shutdown request using
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the PSCI `SYSTEM_OFF` API. This issue will be fixed in a future version of
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the model.
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* Building TF with compiler optimisations disabled (`-O0`) fails.
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* ARM TF cannot be built with mbed TLS version v2.3.0 due to build warnings
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that the ARM TF build system interprets as errors.
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* TBBR is not currently supported when running Trusted Firmware in AArch32
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state.
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ARM Trusted Firmware - version 1.2
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ARM Trusted Firmware - version 1.2
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==================================
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==================================
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@ -860,7 +1086,7 @@ releases of the ARM Trusted Firmware.
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- - - - - - - - - - - - - - - - - - - - - - - - - -
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- - - - - - - - - - - - - - - - - - - - - - - - - -
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_Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved._
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_Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved._
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[OP-TEE Dispatcher]: optee-dispatcher.md
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[OP-TEE Dispatcher]: optee-dispatcher.md
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[Power Domain Topology Design]: psci-pd-tree.md
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[Power Domain Topology Design]: psci-pd-tree.md
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@ -868,3 +1094,10 @@ _Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved._
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[Authentication Framework]: auth-framework.md
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[Authentication Framework]: auth-framework.md
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[Firmware Update]: firmware-update.md
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[Firmware Update]: firmware-update.md
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[TF Reset Design]: reset-design.md
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[TF Reset Design]: reset-design.md
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[PSCI Integration Guide]: psci-lib-integration-guide.md
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[Firmware Design]: firmware-design.md
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[CPU Specific Build Macros]: cpu-specific-build-macros.md
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[User Guide]: user-guide.md
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[Porting Guide]: porting-guide.md
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[Developer Certificate of Origin]: ../dco.txt
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[Contribution Guide]: ../contributing.md
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