mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-17 10:04:26 +00:00
rcar_gen3: drivers: staging
- ddr - pfc [pin function controller] - qos [bandwidth] checkpatch.pl is generating too many errors.
This commit is contained in:
parent
7e532c4bf7
commit
6ac2892a17
75 changed files with 31702 additions and 5 deletions
18
drivers/staging/renesas/rcar/ddr/boot_init_dram.h
Normal file
18
drivers/staging/renesas/rcar/ddr/boot_init_dram.h
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@ -0,0 +1,18 @@
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/*
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* Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __BOOT_INIT_DRAM_
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#define __BOOT_INIT_DRAM_
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extern int32_t rcar_dram_init(void);
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#define INITDRAM_OK (0)
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#define INITDRAM_NG (0xffffffff)
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#define INITDRAM_ERR_I (0xffffffff)
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#define INITDRAM_ERR_O (0xfffffffe)
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#define INITDRAM_ERR_T (0xfffffff0)
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#endif
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13
drivers/staging/renesas/rcar/ddr/ddr.mk
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13
drivers/staging/renesas/rcar/ddr/ddr.mk
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#
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# Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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ifeq (${RCAR_LSI},${RCAR_E3})
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include drivers/staging/renesas/rcar/ddr/ddr_a/ddr_a.mk
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else
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include drivers/staging/renesas/rcar/ddr/ddr_b/ddr_b.mk
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endif
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BL2_SOURCES += drivers/staging/renesas/rcar/ddr/dram_sub_func.c
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@ -0,0 +1,115 @@
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/*
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* Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef BOOT_INIT_DRAM_REGDEF_E3_H_
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#define BOOT_INIT_DRAM_REGDEF_E3_H_
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#ifdef __cplusplus
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extern "C" {
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#endif /* __cplusplus */
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#define BIT0 0x00000001U
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#define BIT11 0x00000800U
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#define BIT30 0x40000000U
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/* DBSC registers */
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#define DBSC_E3_DBSYSCONF1 0xE6790004U
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#define DBSC_E3_DBPHYCONF0 0xE6790010U
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#define DBSC_E3_DBKIND 0xE6790020U
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#define DBSC_E3_DBMEMCONF00 0xE6790030U
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#define DBSC_E3_DBSYSCNT0 0xE6790100U
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#define DBSC_E3_DBACEN 0xE6790200U
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#define DBSC_E3_DBRFEN 0xE6790204U
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#define DBSC_E3_DBCMD 0xE6790208U
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#define DBSC_E3_DBWAIT 0xE6790210U
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#define DBSC_E3_DBTR0 0xE6790300U
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#define DBSC_E3_DBTR1 0xE6790304U
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#define DBSC_E3_DBTR2 0xE6790308U
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#define DBSC_E3_DBTR3 0xE679030CU
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#define DBSC_E3_DBTR4 0xE6790310U
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#define DBSC_E3_DBTR5 0xE6790314U
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#define DBSC_E3_DBTR6 0xE6790318U
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#define DBSC_E3_DBTR7 0xE679031CU
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#define DBSC_E3_DBTR8 0xE6790320U
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#define DBSC_E3_DBTR9 0xE6790324U
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#define DBSC_E3_DBTR10 0xE6790328U
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#define DBSC_E3_DBTR11 0xE679032CU
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#define DBSC_E3_DBTR12 0xE6790330U
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#define DBSC_E3_DBTR13 0xE6790334U
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#define DBSC_E3_DBTR14 0xE6790338U
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#define DBSC_E3_DBTR15 0xE679033CU
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#define DBSC_E3_DBTR16 0xE6790340U
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#define DBSC_E3_DBTR17 0xE6790344U
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#define DBSC_E3_DBTR18 0xE6790348U
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#define DBSC_E3_DBTR19 0xE679034CU
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#define DBSC_E3_DBTR20 0xE6790350U
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#define DBSC_E3_DBTR21 0xE6790354U
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#define DBSC_E3_DBBL 0xE6790400U
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#define DBSC_E3_DBRFCNF1 0xE6790414U
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#define DBSC_E3_DBRFCNF2 0xE6790418U
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#define DBSC_E3_DBCALCNF 0xE6790424U
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#define DBSC_E3_DBODT0 0xE6790460U
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#define DBSC_E3_DBADJ0 0xE6790500U
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#define DBSC_E3_DBDFICUPDCNF 0xE679052CU
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#define DBSC_E3_DBDFICNT0 0xE6790604U
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#define DBSC_E3_DBPDLK0 0xE6790620U
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#define DBSC_E3_DBPDRGA0 0xE6790624U
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#define DBSC_E3_DBPDRGD0 0xE6790628U
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#define DBSC_E3_DBBUS0CNF1 0xE6790804U
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#define DBSC_E3_DBCAM0CNF1 0xE6790904U
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#define DBSC_E3_DBCAM0CNF2 0xE6790908U
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#define DBSC_E3_DBCAM0STAT0 0xE6790980U
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#define DBSC_E3_DBBCAMDIS 0xE67909FCU
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#define DBSC_E3_DBSCHCNT0 0xE6791000U
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#define DBSC_E3_DBSCHSZ0 0xE6791010U
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#define DBSC_E3_DBSCHRW0 0xE6791020U
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#define DBSC_E3_DBSCHRW1 0xE6791024U
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#define DBSC_E3_DBSCHQOS00 0xE6791030U
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#define DBSC_E3_DBSCHQOS01 0xE6791034U
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#define DBSC_E3_DBSCHQOS02 0xE6791038U
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#define DBSC_E3_DBSCHQOS03 0xE679103CU
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#define DBSC_E3_DBSCHQOS40 0xE6791070U
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#define DBSC_E3_DBSCHQOS41 0xE6791074U
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#define DBSC_E3_DBSCHQOS42 0xE6791078U
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#define DBSC_E3_DBSCHQOS43 0xE679107CU
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#define DBSC_E3_DBSCHQOS90 0xE67910C0U
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#define DBSC_E3_DBSCHQOS91 0xE67910C4U
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#define DBSC_E3_DBSCHQOS92 0xE67910C8U
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#define DBSC_E3_DBSCHQOS93 0xE67910CCU
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#define DBSC_E3_DBSCHQOS130 0xE6791100U
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#define DBSC_E3_DBSCHQOS131 0xE6791104U
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#define DBSC_E3_DBSCHQOS132 0xE6791108U
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#define DBSC_E3_DBSCHQOS133 0xE679110CU
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#define DBSC_E3_DBSCHQOS140 0xE6791110U
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#define DBSC_E3_DBSCHQOS141 0xE6791114U
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#define DBSC_E3_DBSCHQOS142 0xE6791118U
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#define DBSC_E3_DBSCHQOS143 0xE679111CU
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#define DBSC_E3_DBSCHQOS150 0xE6791120U
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#define DBSC_E3_DBSCHQOS151 0xE6791124U
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#define DBSC_E3_DBSCHQOS152 0xE6791128U
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#define DBSC_E3_DBSCHQOS153 0xE679112CU
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#define DBSC_E3_SCFCTST0 0xE6791700U
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#define DBSC_E3_SCFCTST1 0xE6791708U
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#define DBSC_E3_SCFCTST2 0xE679170CU
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/* CPG registers */
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#define CPG_SRCR4 0xE61500BCU
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#define CPG_PLLECR 0xE61500D0U
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#define CPG_CPGWPR 0xE6150900U
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#define CPG_CPGWPCR 0xE6150904U
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#define CPG_SRSTCLR4 0xE6150950U
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/* MODE Monitor registers */
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#define RST_MODEMR 0xE6160060U
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#ifdef __cplusplus
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}
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#endif /* __cplusplus */
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#endif /* BOOT_INIT_DRAM_REGDEF_E3_H_ */
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7
drivers/staging/renesas/rcar/ddr/ddr_a/ddr_a.mk
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7
drivers/staging/renesas/rcar/ddr/ddr_a/ddr_a.mk
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#
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# Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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BL2_SOURCES += drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c
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1544
drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c
Normal file
1544
drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c
Normal file
File diff suppressed because it is too large
Load diff
34
drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.h
Normal file
34
drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.h
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/*
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* Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#pragma once
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#include <stdint.h>
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#ifndef __DDR_INIT_E3_
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#define __DDR_INIT_E3_
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#define RCAR_E3_DDR_VERSION "rev.0.09"
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#ifdef ddr_qos_init_setting
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#define REFRESH_RATE 3900 /* Average periodic refresh interval[ns]. Support 3900,7800 */
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#else
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#if RCAR_REF_INT == 0
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#define REFRESH_RATE 3900
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#elif RCAR_REF_INT == 1
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#define REFRESH_RATE 7800
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#else
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#define REFRESH_RATE 3900
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#endif
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#endif
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extern int32_t InitDram(void);
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#define INITDRAM_OK (0)
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#define INITDRAM_NG (0xffffffff)
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#define INITDRAM_ERR_I (0xffffffff)
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#define INITDRAM_ERR_O (0xfffffffe)
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#define INITDRAM_ERR_T (0xfffffff0)
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#endif /* __DDR_INIT_E3_ */
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4467
drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c
Normal file
4467
drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c
Normal file
File diff suppressed because it is too large
Load diff
1478
drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c
Normal file
1478
drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c
Normal file
File diff suppressed because it is too large
Load diff
309
drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h
Normal file
309
drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h
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/*
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* Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#define RCAR_DDR_VERSION "rev.0.33"
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#define DRAM_CH_CNT (0x04)
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#define SLICE_CNT (0x04)
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#define CS_CNT (0x02)
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/* order : CS0A, CS0B, CS1A, CS1B */
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#define CSAB_CNT (CS_CNT * 2)
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/* order : CH0A, CH0B, CH1A, CH1B, CH2A, CH2B, CH3A, CH3B */
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#define CHAB_CNT (DRAM_CH_CNT * 2)
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/* pll setting */
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#define CLK_DIV(a, diva, b, divb) (((a) * (divb)) /((b) * (diva)))
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#define CLK_MUL(a, diva, b, divb) (((a) * (b)) / ((diva) * (divb)))
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/* for ddr deisity setting */
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#define DBMEMCONF_REG(d3, row, bank, col, dw) \
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((d3) << 30 | ((row) << 24) | ((bank) << 16) | ((col) << 8) | (dw))
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#define DBMEMCONF_REGD(density) \
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(DBMEMCONF_REG((density) % 2, ((density) + 1) / 2 + (29-3-10-2), 3, 10, 2))
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#define DBMEMCONF_VAL(ch, cs) (DBMEMCONF_REGD(DBMEMCONF_DENS(ch, cs)))
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/* refresh mode */
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#define DBSC_REFINTS (0x0)
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/* system registers */
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#define CPG_BASE (0xE6150000U)
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#define CPG_FRQCRB (CPG_BASE + 0x0004U)
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#define CPG_PLLECR (CPG_BASE + 0x00D0U)
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#define CPG_MSTPSR5 (CPG_BASE + 0x003CU)
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#define CPG_SRCR4 (CPG_BASE + 0x00BCU)
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#define CPG_PLL3CR (CPG_BASE + 0x00DCU)
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#define CPG_ZB3CKCR (CPG_BASE + 0x0380U)
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#define CPG_FRQCRD (CPG_BASE + 0x00E4U)
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#define CPG_SMSTPCR5 (CPG_BASE + 0x0144U)
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#define CPG_CPGWPR (CPG_BASE + 0x0900U)
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#define CPG_SRSTCLR4 (CPG_BASE + 0x0950U)
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#define CPG_FRQCRB_KICK_BIT (1U<<31)
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#define CPG_PLLECR_PLL3E_BIT (1U<<3)
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#define CPG_PLLECR_PLL3ST_BIT (1U<<11)
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#define CPG_ZB3CKCR_ZB3ST_BIT (1U<<11)
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#define RST_BASE (0xE6160000U)
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#define RST_MODEMR (RST_BASE + 0x0060U)
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#define LIFEC_CHIPID(x) (0xE6110040U + 0x04U * (x))
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/* Product Register */
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#define PRR (0xFFF00044U)
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#define PRR_PRODUCT_MASK (0x00007F00U)
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#define PRR_CUT_MASK (0x000000FFU)
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#define PRR_PRODUCT_H3 (0x00004F00U) /* R-Car H3 */
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#define PRR_PRODUCT_M3 (0x00005200U) /* R-Car M3-W */
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#define PRR_PRODUCT_M3N (0x00005500U) /* R-Car M3-N */
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#define PRR_PRODUCT_V3H (0x00005600U) /* R-Car V3H */
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#define PRR_PRODUCT_10 (0x00U) /* Ver.1.0 */
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#define PRR_PRODUCT_11 (0x01U) /* Ver.1.1 */
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#define PRR_PRODUCT_20 (0x10U) /* Ver.2.0 */
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#define PRR_PRODUCT_30 (0x20U) /* Ver.3.0 */
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/* DBSC registers */
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#define DBSC_DBSYSCONF1 0xE6790004U
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#define DBSC_DBPHYCONF0 0xE6790010U
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#define DBSC_DBKIND 0xE6790020U
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#define DBSC_DBMEMCONF(ch, cs) (0xE6790030U + 0x10U * (ch) + 0x04U * (cs))
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#define DBSC_DBMEMCONF_0_0 0xE6790030U
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#define DBSC_DBMEMCONF_0_1 0xE6790034U
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#define DBSC_DBMEMCONF_0_2 0xE6790038U
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#define DBSC_DBMEMCONF_0_3 0xE679003CU
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#define DBSC_DBMEMCONF_1_2 0xE6790048U
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#define DBSC_DBMEMCONF_1_3 0xE679004CU
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#define DBSC_DBMEMCONF_1_0 0xE6790040U
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#define DBSC_DBMEMCONF_1_1 0xE6790044U
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#define DBSC_DBMEMCONF_2_0 0xE6790050U
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#define DBSC_DBMEMCONF_2_1 0xE6790054U
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#define DBSC_DBMEMCONF_2_2 0xE6790058U
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#define DBSC_DBMEMCONF_2_3 0xE679005CU
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#define DBSC_DBMEMCONF_3_0 0xE6790060U
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#define DBSC_DBMEMCONF_3_1 0xE6790064U
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#define DBSC_DBMEMCONF_3_2 0xE6790068U
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#define DBSC_DBMEMCONF_3_3 0xE679006CU
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#define DBSC_DBSYSCNT0 0xE6790100U
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#define DBSC_DBACEN 0xE6790200U
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#define DBSC_DBRFEN 0xE6790204U
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#define DBSC_DBCMD 0xE6790208U
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#define DBSC_DBWAIT 0xE6790210U
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#define DBSC_DBSYSCTRL0 0xE6790280U
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#define DBSC_DBTR(x) (0xE6790300U + 0x04U * (x))
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#define DBSC_DBTR0 0xE6790300U
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#define DBSC_DBTR1 0xE6790304U
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#define DBSC_DBTR3 0xE679030CU
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#define DBSC_DBTR4 0xE6790310U
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#define DBSC_DBTR5 0xE6790314U
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#define DBSC_DBTR6 0xE6790318U
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#define DBSC_DBTR7 0xE679031CU
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#define DBSC_DBTR8 0xE6790320U
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#define DBSC_DBTR9 0xE6790324U
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#define DBSC_DBTR10 0xE6790328U
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#define DBSC_DBTR11 0xE679032CU
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#define DBSC_DBTR12 0xE6790330U
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#define DBSC_DBTR13 0xE6790334U
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#define DBSC_DBTR14 0xE6790338U
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#define DBSC_DBTR15 0xE679033CU
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#define DBSC_DBTR16 0xE6790340U
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#define DBSC_DBTR17 0xE6790344U
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#define DBSC_DBTR18 0xE6790348U
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#define DBSC_DBTR19 0xE679034CU
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#define DBSC_DBTR20 0xE6790350U
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#define DBSC_DBTR21 0xE6790354U
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#define DBSC_DBTR22 0xE6790358U
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#define DBSC_DBTR23 0xE679035CU
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#define DBSC_DBTR24 0xE6790360U
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#define DBSC_DBTR25 0xE6790364U
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#define DBSC_DBTR26 0xE6790368U
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#define DBSC_DBBL 0xE6790400U
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#define DBSC_DBRFCNF1 0xE6790414U
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#define DBSC_DBRFCNF2 0xE6790418U
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#define DBSC_DBTSPCNF 0xE6790420U
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#define DBSC_DBCALCNF 0xE6790424U
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#define DBSC_DBRNK(x) (0xE6790430U + 0x04U * (x))
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#define DBSC_DBRNK2 0xE6790438U
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#define DBSC_DBRNK3 0xE679043CU
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#define DBSC_DBRNK4 0xE6790440U
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#define DBSC_DBRNK5 0xE6790444U
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#define DBSC_DBODT(x) (0xE6790460U + 0x04U * (x))
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#define DBSC_DBADJ0 0xE6790500U
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#define DBSC_DBDBICNT 0xE6790518U
|
||||
#define DBSC_DBDFIPMSTRCNF 0xE6790520U
|
||||
#define DBSC_DBDFICUPDCNF 0xE679052CU
|
||||
|
||||
#define DBSC_INITCOMP(ch) (0xE6790600U + 0x40U * (ch))
|
||||
#define DBSC_INITCOMP_0 0xE6790600U
|
||||
#define DBSC_INITCOMP_1 0xE6790640U
|
||||
#define DBSC_INITCOMP_2 0xE6790680U
|
||||
#define DBSC_INITCOMP_3 0xE67906C0U
|
||||
|
||||
#define DBSC_DBDFICNT(ch) (0xE6790604U + 0x40U * (ch))
|
||||
#define DBSC_DBDFICNT_0 0xE6790604U
|
||||
#define DBSC_DBDFICNT_1 0xE6790644U
|
||||
#define DBSC_DBDFICNT_2 0xE6790684U
|
||||
#define DBSC_DBDFICNT_3 0xE67906C4U
|
||||
|
||||
#define DBSC_DBPDCNT0(ch) (0xE6790610U + 0x40U * (ch))
|
||||
#define DBSC_DBPDCNT0_0 0xE6790610U
|
||||
#define DBSC_DBPDCNT0_1 0xE6790650U
|
||||
#define DBSC_DBPDCNT0_2 0xE6790690U
|
||||
#define DBSC_DBPDCNT0_3 0xE67906D0U
|
||||
|
||||
#define DBSC_DBPDCNT1(ch) (0xE6790614U + 0x40U * (ch))
|
||||
#define DBSC_DBPDCNT1_0 0xE6790614U
|
||||
#define DBSC_DBPDCNT1_1 0xE6790654U
|
||||
#define DBSC_DBPDCNT1_2 0xE6790694U
|
||||
#define DBSC_DBPDCNT1_3 0xE67906D4U
|
||||
|
||||
#define DBSC_DBPDCNT2(ch) (0xE6790618U + 0x40U * (ch))
|
||||
#define DBSC_DBPDCNT2_0 0xE6790618U
|
||||
#define DBSC_DBPDCNT2_1 0xE6790658U
|
||||
#define DBSC_DBPDCNT2_2 0xE6790698U
|
||||
#define DBSC_DBPDCNT2_3 0xE67906D8U
|
||||
|
||||
#define DBSC_DBPDCNT3(ch) (0xE679061CU + 0x40U * (ch))
|
||||
#define DBSC_DBPDCNT3_0 0xE679061CU
|
||||
#define DBSC_DBPDCNT3_1 0xE679065CU
|
||||
#define DBSC_DBPDCNT3_2 0xE679069CU
|
||||
#define DBSC_DBPDCNT3_3 0xE67906DCU
|
||||
|
||||
#define DBSC_DBPDLK(ch) (0xE6790620U + 0x40U * (ch))
|
||||
#define DBSC_DBPDLK_0 0xE6790620U
|
||||
#define DBSC_DBPDLK_1 0xE6790660U
|
||||
#define DBSC_DBPDLK_2 0xE67906a0U
|
||||
#define DBSC_DBPDLK_3 0xE67906e0U
|
||||
|
||||
#define DBSC_DBPDRGA(ch) (0xE6790624U + 0x40U * (ch))
|
||||
#define DBSC_DBPDRGD(ch) (0xE6790628U + 0x40U * (ch))
|
||||
#define DBSC_DBPDRGA_0 0xE6790624U
|
||||
#define DBSC_DBPDRGD_0 0xE6790628U
|
||||
#define DBSC_DBPDRGA_1 0xE6790664U
|
||||
#define DBSC_DBPDRGD_1 0xE6790668U
|
||||
#define DBSC_DBPDRGA_2 0xE67906A4U
|
||||
#define DBSC_DBPDRGD_2 0xE67906A8U
|
||||
#define DBSC_DBPDRGA_3 0xE67906E4U
|
||||
#define DBSC_DBPDRGD_3 0xE67906E8U
|
||||
|
||||
#define DBSC_DBPDSTAT(ch) (0xE6790630U + 0x40U * (ch))
|
||||
#define DBSC_DBPDSTAT_0 0xE6790630U
|
||||
#define DBSC_DBPDSTAT_1 0xE6790670U
|
||||
#define DBSC_DBPDSTAT_2 0xE67906B0U
|
||||
#define DBSC_DBPDSTAT_3 0xE67906F0U
|
||||
|
||||
#define DBSC_DBBUS0CNF0 0xE6790800U
|
||||
#define DBSC_DBBUS0CNF1 0xE6790804U
|
||||
|
||||
#define DBSC_DBCAM0CNF1 0xE6790904U
|
||||
#define DBSC_DBCAM0CNF2 0xE6790908U
|
||||
#define DBSC_DBCAM0CNF3 0xE679090CU
|
||||
#define DBSC_DBBSWAP 0xE67909F0U
|
||||
#define DBSC_DBBCAMDIS 0xE67909FCU
|
||||
#define DBSC_DBSCHCNT0 0xE6791000U
|
||||
#define DBSC_DBSCHCNT1 0xE6791004U
|
||||
#define DBSC_DBSCHSZ0 0xE6791010U
|
||||
#define DBSC_DBSCHRW0 0xE6791020U
|
||||
#define DBSC_DBSCHRW1 0xE6791024U
|
||||
|
||||
#define DBSC_DBSCHQOS_0(x) (0xE6791030U +0x10U * (x))
|
||||
#define DBSC_DBSCHQOS_1(x) (0xE6791034U +0x10U * (x))
|
||||
#define DBSC_DBSCHQOS_2(x) (0xE6791038U +0x10U * (x))
|
||||
#define DBSC_DBSCHQOS_3(x) (0xE679103CU +0x10U * (x))
|
||||
|
||||
#define DBSC_DBSCTR0 0xE6791700U
|
||||
#define DBSC_DBSCTR1 0xE6791708U
|
||||
#define DBSC_DBSCHRW2 0xE679170CU
|
||||
|
||||
#define DBSC_SCFCTST01(x) (0xE6791700U + 0x08U * (x))
|
||||
#define DBSC_SCFCTST0 0xE6791700U
|
||||
#define DBSC_SCFCTST1 0xE6791708U
|
||||
#define DBSC_SCFCTST2 0xE679170CU
|
||||
|
||||
#define DBSC_DBMRRDR(chab) (0xE6791800U + 0x04U * (chab))
|
||||
#define DBSC_DBMRRDR_0 0xE6791800U
|
||||
#define DBSC_DBMRRDR_1 0xE6791804U
|
||||
#define DBSC_DBMRRDR_2 0xE6791808U
|
||||
#define DBSC_DBMRRDR_3 0xE679180CU
|
||||
#define DBSC_DBMRRDR_4 0xE6791810U
|
||||
#define DBSC_DBMRRDR_5 0xE6791814U
|
||||
#define DBSC_DBMRRDR_6 0xE6791818U
|
||||
#define DBSC_DBMRRDR_7 0xE679181CU
|
||||
|
||||
#define DBSC_DBMEMSWAPCONF0 0xE6792000U
|
||||
|
||||
#define DBSC_DBMONCONF4 0xE6793010U
|
||||
|
||||
#define DBSC_PLL_LOCK(ch) (0xE6794054U + 0x100U * (ch))
|
||||
#define DBSC_PLL_LOCK_0 0xE6794054U
|
||||
#define DBSC_PLL_LOCK_1 0xE6794154U
|
||||
#define DBSC_PLL_LOCK_2 0xE6794254U
|
||||
#define DBSC_PLL_LOCK_3 0xE6794354U
|
||||
|
||||
/* STAT registers */
|
||||
#define MSTAT_SL_INIT 0xE67E8000U
|
||||
#define MSTAT_REF_ARS 0xE67E8004U
|
||||
#define MSTATQ_STATQC 0xE67E8008U
|
||||
#define MSTATQ_WTENABLE 0xE67E8030U
|
||||
#define MSTATQ_WTREFRESH 0xE67E8034U
|
||||
#define MSTATQ_WTSETTING0 0xE67E8038U
|
||||
#define MSTATQ_WTSETTING1 0xE67E803CU
|
||||
|
||||
#define QOS_BASE1 (0xE67F0000U)
|
||||
#define QOSCTRL_RAS (QOS_BASE1 + 0x0000U)
|
||||
#define QOSCTRL_FIXTH (QOS_BASE1 + 0x0004U)
|
||||
#define QOSCTRL_RAEN (QOS_BASE1 + 0x0018U)
|
||||
#define QOSCTRL_REGGD (QOS_BASE1 + 0x0020U)
|
||||
#define QOSCTRL_DANN (QOS_BASE1 + 0x0030U)
|
||||
#define QOSCTRL_DANT (QOS_BASE1 + 0x0038U)
|
||||
#define QOSCTRL_EC (QOS_BASE1 + 0x003CU)
|
||||
#define QOSCTRL_EMS (QOS_BASE1 + 0x0040U)
|
||||
#define QOSCTRL_INSFC (QOS_BASE1 + 0x0050U)
|
||||
#define QOSCTRL_BERR (QOS_BASE1 + 0x0054U)
|
||||
#define QOSCTRL_RACNT0 (QOS_BASE1 + 0x0080U)
|
||||
#define QOSCTRL_STATGEN0 (QOS_BASE1 + 0x0088U)
|
||||
|
||||
/* other module */
|
||||
#define THS1_THCTR 0xE6198020U
|
||||
#define THS1_TEMP 0xE6198028U
|
||||
|
||||
#define DBSC_BASE (0xE6790000U)
|
||||
#define DBSC_DBSCHQOS00 (DBSC_BASE + 0x1030U)
|
||||
#define DBSC_DBSCHQOS01 (DBSC_BASE + 0x1034U)
|
||||
#define DBSC_DBSCHQOS02 (DBSC_BASE + 0x1038U)
|
||||
#define DBSC_DBSCHQOS03 (DBSC_BASE + 0x103CU)
|
||||
#define DBSC_DBSCHQOS40 (DBSC_BASE + 0x1070U)
|
||||
#define DBSC_DBSCHQOS41 (DBSC_BASE + 0x1074U)
|
||||
#define DBSC_DBSCHQOS42 (DBSC_BASE + 0x1078U)
|
||||
#define DBSC_DBSCHQOS43 (DBSC_BASE + 0x107CU)
|
||||
#define DBSC_DBSCHQOS90 (DBSC_BASE + 0x10C0U)
|
||||
#define DBSC_DBSCHQOS91 (DBSC_BASE + 0x10C4U)
|
||||
#define DBSC_DBSCHQOS92 (DBSC_BASE + 0x10C8U)
|
||||
#define DBSC_DBSCHQOS93 (DBSC_BASE + 0x10CCU)
|
||||
#define DBSC_DBSCHQOS120 (DBSC_BASE + 0x10F0U)
|
||||
#define DBSC_DBSCHQOS121 (DBSC_BASE + 0x10F4U)
|
||||
#define DBSC_DBSCHQOS122 (DBSC_BASE + 0x10F8U)
|
||||
#define DBSC_DBSCHQOS123 (DBSC_BASE + 0x10FCU)
|
||||
#define DBSC_DBSCHQOS130 (DBSC_BASE + 0x1100U)
|
||||
#define DBSC_DBSCHQOS131 (DBSC_BASE + 0x1104U)
|
||||
#define DBSC_DBSCHQOS132 (DBSC_BASE + 0x1108U)
|
||||
#define DBSC_DBSCHQOS133 (DBSC_BASE + 0x110CU)
|
||||
#define DBSC_DBSCHQOS140 (DBSC_BASE + 0x1110U)
|
||||
#define DBSC_DBSCHQOS141 (DBSC_BASE + 0x1114U)
|
||||
#define DBSC_DBSCHQOS142 (DBSC_BASE + 0x1118U)
|
||||
#define DBSC_DBSCHQOS143 (DBSC_BASE + 0x111CU)
|
||||
#define DBSC_DBSCHQOS150 (DBSC_BASE + 0x1120U)
|
||||
#define DBSC_DBSCHQOS151 (DBSC_BASE + 0x1124U)
|
||||
#define DBSC_DBSCHQOS152 (DBSC_BASE + 0x1128U)
|
||||
#define DBSC_DBSCHQOS153 (DBSC_BASE + 0x112CU)
|
7
drivers/staging/renesas/rcar/ddr/ddr_b/ddr_b.mk
Normal file
7
drivers/staging/renesas/rcar/ddr/ddr_b/ddr_b.mk
Normal file
|
@ -0,0 +1,7 @@
|
|||
#
|
||||
# Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c
|
5886
drivers/staging/renesas/rcar/ddr/ddr_b/ddr_regdef.h
Normal file
5886
drivers/staging/renesas/rcar/ddr/ddr_b/ddr_regdef.h
Normal file
File diff suppressed because it is too large
Load diff
440
drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3.h
Normal file
440
drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3.h
Normal file
|
@ -0,0 +1,440 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#define DDR_PHY_SLICE_REGSET_OFS_H3 0x0400
|
||||
#define DDR_PHY_ADR_V_REGSET_OFS_H3 0x0600
|
||||
#define DDR_PHY_ADR_I_REGSET_OFS_H3 0x0680
|
||||
#define DDR_PHY_ADR_G_REGSET_OFS_H3 0x0700
|
||||
#define DDR_PI_REGSET_OFS_H3 0x0200
|
||||
|
||||
#define DDR_PHY_SLICE_REGSET_SIZE_H3 0x80
|
||||
#define DDR_PHY_ADR_V_REGSET_SIZE_H3 0x80
|
||||
#define DDR_PHY_ADR_I_REGSET_SIZE_H3 0x80
|
||||
#define DDR_PHY_ADR_G_REGSET_SIZE_H3 0x80
|
||||
#define DDR_PI_REGSET_SIZE_H3 0x100
|
||||
|
||||
#define DDR_PHY_SLICE_REGSET_NUM_H3 88
|
||||
#define DDR_PHY_ADR_V_REGSET_NUM_H3 37
|
||||
#define DDR_PHY_ADR_I_REGSET_NUM_H3 37
|
||||
#define DDR_PHY_ADR_G_REGSET_NUM_H3 59
|
||||
#define DDR_PI_REGSET_NUM_H3 181
|
||||
|
||||
static const uint32_t DDR_PHY_SLICE_REGSET_H3[DDR_PHY_SLICE_REGSET_NUM_H3] = {
|
||||
/*0400*/ 0x000004f0,
|
||||
/*0401*/ 0x00000000,
|
||||
/*0402*/ 0x00000000,
|
||||
/*0403*/ 0x00000100,
|
||||
/*0404*/ 0x01003c0c,
|
||||
/*0405*/ 0x02003c0c,
|
||||
/*0406*/ 0x00010300,
|
||||
/*0407*/ 0x04000100,
|
||||
/*0408*/ 0x00000300,
|
||||
/*0409*/ 0x000700c0,
|
||||
/*040a*/ 0x00b00201,
|
||||
/*040b*/ 0x00000020,
|
||||
/*040c*/ 0x00000000,
|
||||
/*040d*/ 0x00000000,
|
||||
/*040e*/ 0x00000000,
|
||||
/*040f*/ 0x00000000,
|
||||
/*0410*/ 0x00000000,
|
||||
/*0411*/ 0x00000000,
|
||||
/*0412*/ 0x00000000,
|
||||
/*0413*/ 0x09000000,
|
||||
/*0414*/ 0x04080000,
|
||||
/*0415*/ 0x04080400,
|
||||
/*0416*/ 0x00000000,
|
||||
/*0417*/ 0x32103210,
|
||||
/*0418*/ 0x00800708,
|
||||
/*0419*/ 0x000f000c,
|
||||
/*041a*/ 0x00000100,
|
||||
/*041b*/ 0x55aa55aa,
|
||||
/*041c*/ 0x33cc33cc,
|
||||
/*041d*/ 0x0ff00ff0,
|
||||
/*041e*/ 0x0f0ff0f0,
|
||||
/*041f*/ 0x00008e38,
|
||||
/*0420*/ 0x76543210,
|
||||
/*0421*/ 0x00000001,
|
||||
/*0422*/ 0x00000000,
|
||||
/*0423*/ 0x00000000,
|
||||
/*0424*/ 0x00000000,
|
||||
/*0425*/ 0x00000000,
|
||||
/*0426*/ 0x00000000,
|
||||
/*0427*/ 0x00000000,
|
||||
/*0428*/ 0x00000000,
|
||||
/*0429*/ 0x00000000,
|
||||
/*042a*/ 0x00000000,
|
||||
/*042b*/ 0x00000000,
|
||||
/*042c*/ 0x00000000,
|
||||
/*042d*/ 0x00000000,
|
||||
/*042e*/ 0x00000000,
|
||||
/*042f*/ 0x00000000,
|
||||
/*0430*/ 0x00000000,
|
||||
/*0431*/ 0x00000000,
|
||||
/*0432*/ 0x00000000,
|
||||
/*0433*/ 0x00200000,
|
||||
/*0434*/ 0x08200820,
|
||||
/*0435*/ 0x08200820,
|
||||
/*0436*/ 0x08200820,
|
||||
/*0437*/ 0x08200820,
|
||||
/*0438*/ 0x08200820,
|
||||
/*0439*/ 0x00000820,
|
||||
/*043a*/ 0x03000300,
|
||||
/*043b*/ 0x03000300,
|
||||
/*043c*/ 0x03000300,
|
||||
/*043d*/ 0x03000300,
|
||||
/*043e*/ 0x00000300,
|
||||
/*043f*/ 0x00000000,
|
||||
/*0440*/ 0x00000000,
|
||||
/*0441*/ 0x00000000,
|
||||
/*0442*/ 0x00000000,
|
||||
/*0443*/ 0x00a000a0,
|
||||
/*0444*/ 0x00a000a0,
|
||||
/*0445*/ 0x00a000a0,
|
||||
/*0446*/ 0x00a000a0,
|
||||
/*0447*/ 0x00a000a0,
|
||||
/*0448*/ 0x00a000a0,
|
||||
/*0449*/ 0x00a000a0,
|
||||
/*044a*/ 0x00a000a0,
|
||||
/*044b*/ 0x00a000a0,
|
||||
/*044c*/ 0x01040109,
|
||||
/*044d*/ 0x00000200,
|
||||
/*044e*/ 0x01000000,
|
||||
/*044f*/ 0x00000200,
|
||||
/*0450*/ 0x4041a141,
|
||||
/*0451*/ 0xc00141a0,
|
||||
/*0452*/ 0x0e0100c0,
|
||||
/*0453*/ 0x0010000c,
|
||||
/*0454*/ 0x0c064208,
|
||||
/*0455*/ 0x000f0c18,
|
||||
/*0456*/ 0x00e00140,
|
||||
/*0457*/ 0x00000c20
|
||||
};
|
||||
|
||||
static const uint32_t DDR_PHY_ADR_V_REGSET_H3[DDR_PHY_ADR_V_REGSET_NUM_H3] = {
|
||||
/*0600*/ 0x00000000,
|
||||
/*0601*/ 0x00000000,
|
||||
/*0602*/ 0x00000000,
|
||||
/*0603*/ 0x00000000,
|
||||
/*0604*/ 0x00000000,
|
||||
/*0605*/ 0x00000000,
|
||||
/*0606*/ 0x00000002,
|
||||
/*0607*/ 0x00000000,
|
||||
/*0608*/ 0x00000000,
|
||||
/*0609*/ 0x00000000,
|
||||
/*060a*/ 0x00400320,
|
||||
/*060b*/ 0x00000040,
|
||||
/*060c*/ 0x00dcba98,
|
||||
/*060d*/ 0x00000000,
|
||||
/*060e*/ 0x00dcba98,
|
||||
/*060f*/ 0x01000000,
|
||||
/*0610*/ 0x00020003,
|
||||
/*0611*/ 0x00000000,
|
||||
/*0612*/ 0x00000000,
|
||||
/*0613*/ 0x00000000,
|
||||
/*0614*/ 0x00002a01,
|
||||
/*0615*/ 0x00000015,
|
||||
/*0616*/ 0x00000015,
|
||||
/*0617*/ 0x0000002a,
|
||||
/*0618*/ 0x00000033,
|
||||
/*0619*/ 0x0000000c,
|
||||
/*061a*/ 0x0000000c,
|
||||
/*061b*/ 0x00000033,
|
||||
/*061c*/ 0x00418820,
|
||||
/*061d*/ 0x003f0000,
|
||||
/*061e*/ 0x0000003f,
|
||||
/*061f*/ 0x0002006e,
|
||||
/*0620*/ 0x02000200,
|
||||
/*0621*/ 0x02000200,
|
||||
/*0622*/ 0x00000200,
|
||||
/*0623*/ 0x42080010,
|
||||
/*0624*/ 0x00000003
|
||||
};
|
||||
|
||||
static const uint32_t DDR_PHY_ADR_I_REGSET_H3[DDR_PHY_ADR_I_REGSET_NUM_H3] = {
|
||||
/*0680*/ 0x04040404,
|
||||
/*0681*/ 0x00000404,
|
||||
/*0682*/ 0x00000000,
|
||||
/*0683*/ 0x00000000,
|
||||
/*0684*/ 0x00000000,
|
||||
/*0685*/ 0x00000000,
|
||||
/*0686*/ 0x00000002,
|
||||
/*0687*/ 0x00000000,
|
||||
/*0688*/ 0x00000000,
|
||||
/*0689*/ 0x00000000,
|
||||
/*068a*/ 0x00400320,
|
||||
/*068b*/ 0x00000040,
|
||||
/*068c*/ 0x00000000,
|
||||
/*068d*/ 0x00000000,
|
||||
/*068e*/ 0x00000000,
|
||||
/*068f*/ 0x01000000,
|
||||
/*0690*/ 0x00020003,
|
||||
/*0691*/ 0x00000000,
|
||||
/*0692*/ 0x00000000,
|
||||
/*0693*/ 0x00000000,
|
||||
/*0694*/ 0x00002a01,
|
||||
/*0695*/ 0x00000015,
|
||||
/*0696*/ 0x00000015,
|
||||
/*0697*/ 0x0000002a,
|
||||
/*0698*/ 0x00000033,
|
||||
/*0699*/ 0x0000000c,
|
||||
/*069a*/ 0x0000000c,
|
||||
/*069b*/ 0x00000033,
|
||||
/*069c*/ 0x00000000,
|
||||
/*069d*/ 0x00000000,
|
||||
/*069e*/ 0x00000000,
|
||||
/*069f*/ 0x0002006e,
|
||||
/*06a0*/ 0x02000200,
|
||||
/*06a1*/ 0x02000200,
|
||||
/*06a2*/ 0x00000200,
|
||||
/*06a3*/ 0x42080010,
|
||||
/*06a4*/ 0x00000003
|
||||
};
|
||||
|
||||
static const uint32_t DDR_PHY_ADR_G_REGSET_H3[DDR_PHY_ADR_G_REGSET_NUM_H3] = {
|
||||
/*0700*/ 0x00000001,
|
||||
/*0701*/ 0x00000000,
|
||||
/*0702*/ 0x00000005,
|
||||
/*0703*/ 0x04000f00,
|
||||
/*0704*/ 0x00020080,
|
||||
/*0705*/ 0x00020055,
|
||||
/*0706*/ 0x00000000,
|
||||
/*0707*/ 0x00000000,
|
||||
/*0708*/ 0x00000000,
|
||||
/*0709*/ 0x00000050,
|
||||
/*070a*/ 0x00000000,
|
||||
/*070b*/ 0x01010100,
|
||||
/*070c*/ 0x00000200,
|
||||
/*070d*/ 0x00001102,
|
||||
/*070e*/ 0x00000000,
|
||||
/*070f*/ 0x000f1f00,
|
||||
/*0710*/ 0x0f1f0f1f,
|
||||
/*0711*/ 0x0f1f0f1f,
|
||||
/*0712*/ 0x00020003,
|
||||
/*0713*/ 0x02000200,
|
||||
/*0714*/ 0x00000200,
|
||||
/*0715*/ 0x00001102,
|
||||
/*0716*/ 0x00000064,
|
||||
/*0717*/ 0x00000000,
|
||||
/*0718*/ 0x00000000,
|
||||
/*0719*/ 0x00000502,
|
||||
/*071a*/ 0x027f6e00,
|
||||
/*071b*/ 0x007f007f,
|
||||
/*071c*/ 0x00007f3c,
|
||||
/*071d*/ 0x00047f6e,
|
||||
/*071e*/ 0x0003154f,
|
||||
/*071f*/ 0x0001154f,
|
||||
/*0720*/ 0x0001154f,
|
||||
/*0721*/ 0x0001154f,
|
||||
/*0722*/ 0x0001154f,
|
||||
/*0723*/ 0x00003fee,
|
||||
/*0724*/ 0x0001154f,
|
||||
/*0725*/ 0x00003fee,
|
||||
/*0726*/ 0x0001154f,
|
||||
/*0727*/ 0x00007f3c,
|
||||
/*0728*/ 0x0001154f,
|
||||
/*0729*/ 0x00000000,
|
||||
/*072a*/ 0x00000000,
|
||||
/*072b*/ 0x00000000,
|
||||
/*072c*/ 0x65000000,
|
||||
/*072d*/ 0x00000000,
|
||||
/*072e*/ 0x00000000,
|
||||
/*072f*/ 0x00000201,
|
||||
/*0730*/ 0x00000000,
|
||||
/*0731*/ 0x00000000,
|
||||
/*0732*/ 0x00000000,
|
||||
/*0733*/ 0x00000000,
|
||||
/*0734*/ 0x00000000,
|
||||
/*0735*/ 0x00000000,
|
||||
/*0736*/ 0x00000000,
|
||||
/*0737*/ 0x00000000,
|
||||
/*0738*/ 0x00000000,
|
||||
/*0739*/ 0x00000000,
|
||||
/*073a*/ 0x00000000
|
||||
};
|
||||
|
||||
static const uint32_t DDR_PI_REGSET_H3[DDR_PI_REGSET_NUM_H3] = {
|
||||
/*0200*/ 0x00000b00,
|
||||
/*0201*/ 0x00000100,
|
||||
/*0202*/ 0x00000000,
|
||||
/*0203*/ 0x0000ffff,
|
||||
/*0204*/ 0x00000000,
|
||||
/*0205*/ 0x0000ffff,
|
||||
/*0206*/ 0x00000000,
|
||||
/*0207*/ 0x304cffff,
|
||||
/*0208*/ 0x00000200,
|
||||
/*0209*/ 0x00000200,
|
||||
/*020a*/ 0x00000200,
|
||||
/*020b*/ 0x00000200,
|
||||
/*020c*/ 0x0000304c,
|
||||
/*020d*/ 0x00000200,
|
||||
/*020e*/ 0x00000200,
|
||||
/*020f*/ 0x00000200,
|
||||
/*0210*/ 0x00000200,
|
||||
/*0211*/ 0x0000304c,
|
||||
/*0212*/ 0x00000200,
|
||||
/*0213*/ 0x00000200,
|
||||
/*0214*/ 0x00000200,
|
||||
/*0215*/ 0x00000200,
|
||||
/*0216*/ 0x00010000,
|
||||
/*0217*/ 0x00000003,
|
||||
/*0218*/ 0x01000001,
|
||||
/*0219*/ 0x00000000,
|
||||
/*021a*/ 0x00000000,
|
||||
/*021b*/ 0x00000000,
|
||||
/*021c*/ 0x00000000,
|
||||
/*021d*/ 0x00000000,
|
||||
/*021e*/ 0x00000000,
|
||||
/*021f*/ 0x00000000,
|
||||
/*0220*/ 0x00000000,
|
||||
/*0221*/ 0x00000000,
|
||||
/*0222*/ 0x00000000,
|
||||
/*0223*/ 0x00000000,
|
||||
/*0224*/ 0x00000000,
|
||||
/*0225*/ 0x00000000,
|
||||
/*0226*/ 0x00000000,
|
||||
/*0227*/ 0x00000000,
|
||||
/*0228*/ 0x00000000,
|
||||
/*0229*/ 0x0f000101,
|
||||
/*022a*/ 0x08492d25,
|
||||
/*022b*/ 0x500e0c04,
|
||||
/*022c*/ 0x0002500e,
|
||||
/*022d*/ 0x00460003,
|
||||
/*022e*/ 0x182600cf,
|
||||
/*022f*/ 0x182600cf,
|
||||
/*0230*/ 0x00000005,
|
||||
/*0231*/ 0x00000000,
|
||||
/*0232*/ 0x00000000,
|
||||
/*0233*/ 0x00000000,
|
||||
/*0234*/ 0x00000000,
|
||||
/*0235*/ 0x00000000,
|
||||
/*0236*/ 0x00000000,
|
||||
/*0237*/ 0x00000000,
|
||||
/*0238*/ 0x01000000,
|
||||
/*0239*/ 0x00040404,
|
||||
/*023a*/ 0x01280a00,
|
||||
/*023b*/ 0x00000000,
|
||||
/*023c*/ 0x000f0000,
|
||||
/*023d*/ 0x00001803,
|
||||
/*023e*/ 0x00000000,
|
||||
/*023f*/ 0x00000000,
|
||||
/*0240*/ 0x00060002,
|
||||
/*0241*/ 0x00010001,
|
||||
/*0242*/ 0x01000101,
|
||||
/*0243*/ 0x04020201,
|
||||
/*0244*/ 0x00080804,
|
||||
/*0245*/ 0x00000000,
|
||||
/*0246*/ 0x08030000,
|
||||
/*0247*/ 0x15150408,
|
||||
/*0248*/ 0x00000000,
|
||||
/*0249*/ 0x00000000,
|
||||
/*024a*/ 0x00000000,
|
||||
/*024b*/ 0x001e0f0f,
|
||||
/*024c*/ 0x00000000,
|
||||
/*024d*/ 0x01000300,
|
||||
/*024e*/ 0x00000000,
|
||||
/*024f*/ 0x00000000,
|
||||
/*0250*/ 0x01000000,
|
||||
/*0251*/ 0x00010101,
|
||||
/*0252*/ 0x000e0e0e,
|
||||
/*0253*/ 0x000c0c0c,
|
||||
/*0254*/ 0x02060601,
|
||||
/*0255*/ 0x00000000,
|
||||
/*0256*/ 0x00000003,
|
||||
/*0257*/ 0x00181703,
|
||||
/*0258*/ 0x00280006,
|
||||
/*0259*/ 0x00280016,
|
||||
/*025a*/ 0x00000016,
|
||||
/*025b*/ 0x00000000,
|
||||
/*025c*/ 0x00000000,
|
||||
/*025d*/ 0x00000000,
|
||||
/*025e*/ 0x140a0000,
|
||||
/*025f*/ 0x0005010a,
|
||||
/*0260*/ 0x03018d03,
|
||||
/*0261*/ 0x000a018d,
|
||||
/*0262*/ 0x00060100,
|
||||
/*0263*/ 0x01000006,
|
||||
/*0264*/ 0x018e018e,
|
||||
/*0265*/ 0x018e0100,
|
||||
/*0266*/ 0x1111018e,
|
||||
/*0267*/ 0x10010204,
|
||||
/*0268*/ 0x09090650,
|
||||
/*0269*/ 0x20110202,
|
||||
/*026a*/ 0x00201000,
|
||||
/*026b*/ 0x00201000,
|
||||
/*026c*/ 0x04041000,
|
||||
/*026d*/ 0x18020100,
|
||||
/*026e*/ 0x00010118,
|
||||
/*026f*/ 0x004b004a,
|
||||
/*0270*/ 0x050f0000,
|
||||
/*0271*/ 0x0c01021e,
|
||||
/*0272*/ 0x34000000,
|
||||
/*0273*/ 0x00000000,
|
||||
/*0274*/ 0x00000000,
|
||||
/*0275*/ 0x00000000,
|
||||
/*0276*/ 0x312ed400,
|
||||
/*0277*/ 0xd4111132,
|
||||
/*0278*/ 0x1132312e,
|
||||
/*0279*/ 0x312ed411,
|
||||
/*027a*/ 0x00111132,
|
||||
/*027b*/ 0x32312ed4,
|
||||
/*027c*/ 0x2ed41111,
|
||||
/*027d*/ 0x11113231,
|
||||
/*027e*/ 0x32312ed4,
|
||||
/*027f*/ 0xd4001111,
|
||||
/*0280*/ 0x1132312e,
|
||||
/*0281*/ 0x312ed411,
|
||||
/*0282*/ 0xd4111132,
|
||||
/*0283*/ 0x1132312e,
|
||||
/*0284*/ 0x2ed40011,
|
||||
/*0285*/ 0x11113231,
|
||||
/*0286*/ 0x32312ed4,
|
||||
/*0287*/ 0x2ed41111,
|
||||
/*0288*/ 0x11113231,
|
||||
/*0289*/ 0x00020000,
|
||||
/*028a*/ 0x018d018d,
|
||||
/*028b*/ 0x0c08018d,
|
||||
/*028c*/ 0x1f121d22,
|
||||
/*028d*/ 0x4301b344,
|
||||
/*028e*/ 0x10172006,
|
||||
/*028f*/ 0x121d220c,
|
||||
/*0290*/ 0x01b3441f,
|
||||
/*0291*/ 0x17200643,
|
||||
/*0292*/ 0x1d220c10,
|
||||
/*0293*/ 0x00001f12,
|
||||
/*0294*/ 0x4301b344,
|
||||
/*0295*/ 0x10172006,
|
||||
/*0296*/ 0x00020002,
|
||||
/*0297*/ 0x00020002,
|
||||
/*0298*/ 0x00020002,
|
||||
/*0299*/ 0x00020002,
|
||||
/*029a*/ 0x00020002,
|
||||
/*029b*/ 0x00000000,
|
||||
/*029c*/ 0x00000000,
|
||||
/*029d*/ 0x00000000,
|
||||
/*029e*/ 0x00000000,
|
||||
/*029f*/ 0x00000000,
|
||||
/*02a0*/ 0x00000000,
|
||||
/*02a1*/ 0x00000000,
|
||||
/*02a2*/ 0x00000000,
|
||||
/*02a3*/ 0x00000000,
|
||||
/*02a4*/ 0x00000000,
|
||||
/*02a5*/ 0x00000000,
|
||||
/*02a6*/ 0x00000000,
|
||||
/*02a7*/ 0x01000400,
|
||||
/*02a8*/ 0x00304c00,
|
||||
/*02a9*/ 0x0001e2f8,
|
||||
/*02aa*/ 0x0000304c,
|
||||
/*02ab*/ 0x0001e2f8,
|
||||
/*02ac*/ 0x0000304c,
|
||||
/*02ad*/ 0x0001e2f8,
|
||||
/*02ae*/ 0x08000000,
|
||||
/*02af*/ 0x00000100,
|
||||
/*02b0*/ 0x00000000,
|
||||
/*02b1*/ 0x00000000,
|
||||
/*02b2*/ 0x00000000,
|
||||
/*02b3*/ 0x00000000,
|
||||
/*02b4*/ 0x00000002
|
||||
};
|
537
drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3ver2.h
Normal file
537
drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3ver2.h
Normal file
|
@ -0,0 +1,537 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#define DDR_PHY_SLICE_REGSET_OFS_H3VER2 0x0400
|
||||
#define DDR_PHY_ADR_V_REGSET_OFS_H3VER2 0x0600
|
||||
#define DDR_PHY_ADR_I_REGSET_OFS_H3VER2 0x0640
|
||||
#define DDR_PHY_ADR_G_REGSET_OFS_H3VER2 0x0680
|
||||
#define DDR_PI_REGSET_OFS_H3VER2 0x0200
|
||||
|
||||
#define DDR_PHY_SLICE_REGSET_SIZE_H3VER2 0x80
|
||||
#define DDR_PHY_ADR_V_REGSET_SIZE_H3VER2 0x40
|
||||
#define DDR_PHY_ADR_I_REGSET_SIZE_H3VER2 0x40
|
||||
#define DDR_PHY_ADR_G_REGSET_SIZE_H3VER2 0x80
|
||||
#define DDR_PI_REGSET_SIZE_H3VER2 0x100
|
||||
|
||||
#define DDR_PHY_SLICE_REGSET_NUM_H3VER2 97
|
||||
#define DDR_PHY_ADR_V_REGSET_NUM_H3VER2 37
|
||||
#define DDR_PHY_ADR_I_REGSET_NUM_H3VER2 37
|
||||
#define DDR_PHY_ADR_G_REGSET_NUM_H3VER2 79
|
||||
#define DDR_PI_REGSET_NUM_H3VER2 245
|
||||
|
||||
static const uint32_t
|
||||
DDR_PHY_SLICE_REGSET_H3VER2[DDR_PHY_SLICE_REGSET_NUM_H3VER2] = {
|
||||
/*0400*/ 0x76543210,
|
||||
/*0401*/ 0x0004f008,
|
||||
/*0402*/ 0x00020133,
|
||||
/*0403*/ 0x00000000,
|
||||
/*0404*/ 0x00000000,
|
||||
/*0405*/ 0x00010000,
|
||||
/*0406*/ 0x016e6e0e,
|
||||
/*0407*/ 0x026e6e0e,
|
||||
/*0408*/ 0x00010300,
|
||||
/*0409*/ 0x04000100,
|
||||
/*040a*/ 0x01000000,
|
||||
/*040b*/ 0x00000000,
|
||||
/*040c*/ 0x00000000,
|
||||
/*040d*/ 0x00000100,
|
||||
/*040e*/ 0x001700c0,
|
||||
/*040f*/ 0x020100b0,
|
||||
/*0410*/ 0x00030020,
|
||||
/*0411*/ 0x00000000,
|
||||
/*0412*/ 0x00000000,
|
||||
/*0413*/ 0x00000000,
|
||||
/*0414*/ 0x00000000,
|
||||
/*0415*/ 0x00000000,
|
||||
/*0416*/ 0x00000000,
|
||||
/*0417*/ 0x00000000,
|
||||
/*0418*/ 0x09000000,
|
||||
/*0419*/ 0x04080000,
|
||||
/*041a*/ 0x04080400,
|
||||
/*041b*/ 0x08000000,
|
||||
/*041c*/ 0x0c008007,
|
||||
/*041d*/ 0x00000f00,
|
||||
/*041e*/ 0x00000100,
|
||||
/*041f*/ 0x55aa55aa,
|
||||
/*0420*/ 0x33cc33cc,
|
||||
/*0421*/ 0x0ff00ff0,
|
||||
/*0422*/ 0x0f0ff0f0,
|
||||
/*0423*/ 0x00018e38,
|
||||
/*0424*/ 0x00000000,
|
||||
/*0425*/ 0x00000000,
|
||||
/*0426*/ 0x00000000,
|
||||
/*0427*/ 0x00000000,
|
||||
/*0428*/ 0x00000000,
|
||||
/*0429*/ 0x00000000,
|
||||
/*042a*/ 0x00000000,
|
||||
/*042b*/ 0x00000000,
|
||||
/*042c*/ 0x00000000,
|
||||
/*042d*/ 0x00000000,
|
||||
/*042e*/ 0x00000000,
|
||||
/*042f*/ 0x00000000,
|
||||
/*0430*/ 0x00000000,
|
||||
/*0431*/ 0x00000000,
|
||||
/*0432*/ 0x00000000,
|
||||
/*0433*/ 0x00000000,
|
||||
/*0434*/ 0x00000000,
|
||||
/*0435*/ 0x00000000,
|
||||
/*0436*/ 0x00000000,
|
||||
/*0437*/ 0x00000000,
|
||||
/*0438*/ 0x00000104,
|
||||
/*0439*/ 0x00082020,
|
||||
/*043a*/ 0x08200820,
|
||||
/*043b*/ 0x08200820,
|
||||
/*043c*/ 0x08200820,
|
||||
/*043d*/ 0x08200820,
|
||||
/*043e*/ 0x08200820,
|
||||
/*043f*/ 0x00000000,
|
||||
/*0440*/ 0x00000000,
|
||||
/*0441*/ 0x03000300,
|
||||
/*0442*/ 0x03000300,
|
||||
/*0443*/ 0x03000300,
|
||||
/*0444*/ 0x03000300,
|
||||
/*0445*/ 0x00000300,
|
||||
/*0446*/ 0x00000000,
|
||||
/*0447*/ 0x00000000,
|
||||
/*0448*/ 0x00000000,
|
||||
/*0449*/ 0x00000000,
|
||||
/*044a*/ 0x00000000,
|
||||
/*044b*/ 0x00a000a0,
|
||||
/*044c*/ 0x00a000a0,
|
||||
/*044d*/ 0x00a000a0,
|
||||
/*044e*/ 0x00a000a0,
|
||||
/*044f*/ 0x00a000a0,
|
||||
/*0450*/ 0x00a000a0,
|
||||
/*0451*/ 0x00a000a0,
|
||||
/*0452*/ 0x00a000a0,
|
||||
/*0453*/ 0x00a000a0,
|
||||
/*0454*/ 0x01040109,
|
||||
/*0455*/ 0x00000200,
|
||||
/*0456*/ 0x01000000,
|
||||
/*0457*/ 0x00000200,
|
||||
/*0458*/ 0x00000004,
|
||||
/*0459*/ 0x4041a141,
|
||||
/*045a*/ 0xc00141a0,
|
||||
/*045b*/ 0x0e0000c0,
|
||||
/*045c*/ 0x0010000c,
|
||||
/*045d*/ 0x063e4208,
|
||||
/*045e*/ 0x0f0c180c,
|
||||
/*045f*/ 0x00e00140,
|
||||
/*0460*/ 0x00000c20
|
||||
};
|
||||
|
||||
static const uint32_t
|
||||
DDR_PHY_ADR_V_REGSET_H3VER2[DDR_PHY_ADR_V_REGSET_NUM_H3VER2] = {
|
||||
/*0600*/ 0x00000000,
|
||||
/*0601*/ 0x00000000,
|
||||
/*0602*/ 0x00000000,
|
||||
/*0603*/ 0x00000000,
|
||||
/*0604*/ 0x00000000,
|
||||
/*0605*/ 0x00000000,
|
||||
/*0606*/ 0x00000000,
|
||||
/*0607*/ 0x00010000,
|
||||
/*0608*/ 0x00000200,
|
||||
/*0609*/ 0x00000000,
|
||||
/*060a*/ 0x00000000,
|
||||
/*060b*/ 0x00000000,
|
||||
/*060c*/ 0x00400320,
|
||||
/*060d*/ 0x00000040,
|
||||
/*060e*/ 0x00dcba98,
|
||||
/*060f*/ 0x03000000,
|
||||
/*0610*/ 0x00000200,
|
||||
/*0611*/ 0x00000000,
|
||||
/*0612*/ 0x00000000,
|
||||
/*0613*/ 0x00000000,
|
||||
/*0614*/ 0x0000002a,
|
||||
/*0615*/ 0x00000015,
|
||||
/*0616*/ 0x00000015,
|
||||
/*0617*/ 0x0000002a,
|
||||
/*0618*/ 0x00000033,
|
||||
/*0619*/ 0x0000000c,
|
||||
/*061a*/ 0x0000000c,
|
||||
/*061b*/ 0x00000033,
|
||||
/*061c*/ 0x00418820,
|
||||
/*061d*/ 0x003f0000,
|
||||
/*061e*/ 0x0000003f,
|
||||
/*061f*/ 0x0002c06e,
|
||||
/*0620*/ 0x02c002c0,
|
||||
/*0621*/ 0x02c002c0,
|
||||
/*0622*/ 0x000002c0,
|
||||
/*0623*/ 0x42080010,
|
||||
/*0624*/ 0x0000033e
|
||||
};
|
||||
|
||||
static const uint32_t
|
||||
DDR_PHY_ADR_I_REGSET_H3VER2[DDR_PHY_ADR_I_REGSET_NUM_H3VER2] = {
|
||||
/*0640*/ 0x00000000,
|
||||
/*0641*/ 0x00000000,
|
||||
/*0642*/ 0x00000000,
|
||||
/*0643*/ 0x00000000,
|
||||
/*0644*/ 0x00000000,
|
||||
/*0645*/ 0x00000000,
|
||||
/*0646*/ 0x00000000,
|
||||
/*0647*/ 0x00000000,
|
||||
/*0648*/ 0x00000000,
|
||||
/*0649*/ 0x00000000,
|
||||
/*064a*/ 0x00000000,
|
||||
/*064b*/ 0x00000000,
|
||||
/*064c*/ 0x00000000,
|
||||
/*064d*/ 0x00000000,
|
||||
/*064e*/ 0x00000000,
|
||||
/*064f*/ 0x00000000,
|
||||
/*0650*/ 0x00000000,
|
||||
/*0651*/ 0x00000000,
|
||||
/*0652*/ 0x00000000,
|
||||
/*0653*/ 0x00000000,
|
||||
/*0654*/ 0x00000000,
|
||||
/*0655*/ 0x00000000,
|
||||
/*0656*/ 0x00000000,
|
||||
/*0657*/ 0x00000000,
|
||||
/*0658*/ 0x00000000,
|
||||
/*0659*/ 0x00000000,
|
||||
/*065a*/ 0x00000000,
|
||||
/*065b*/ 0x00000000,
|
||||
/*065c*/ 0x00000000,
|
||||
/*065d*/ 0x00000000,
|
||||
/*065e*/ 0x00000000,
|
||||
/*065f*/ 0x00000000,
|
||||
/*0660*/ 0x00000000,
|
||||
/*0661*/ 0x00000000,
|
||||
/*0662*/ 0x00000000,
|
||||
/*0663*/ 0x00000000,
|
||||
/*0664*/ 0x00000000
|
||||
};
|
||||
|
||||
static const uint32_t
|
||||
DDR_PHY_ADR_G_REGSET_H3VER2[DDR_PHY_ADR_G_REGSET_NUM_H3VER2] = {
|
||||
/*0680*/ 0x00000000,
|
||||
/*0681*/ 0x00000100,
|
||||
/*0682*/ 0x00000000,
|
||||
/*0683*/ 0x00050000,
|
||||
/*0684*/ 0x0f000000,
|
||||
/*0685*/ 0x00800400,
|
||||
/*0686*/ 0x00020032,
|
||||
/*0687*/ 0x00020055,
|
||||
/*0688*/ 0x00000000,
|
||||
/*0689*/ 0x00000000,
|
||||
/*068a*/ 0x00000000,
|
||||
/*068b*/ 0x00000050,
|
||||
/*068c*/ 0x00000000,
|
||||
/*068d*/ 0x01010100,
|
||||
/*068e*/ 0x01000200,
|
||||
/*068f*/ 0x00000000,
|
||||
/*0690*/ 0x00010100,
|
||||
/*0691*/ 0x00000000,
|
||||
/*0692*/ 0x00000000,
|
||||
/*0693*/ 0x00000000,
|
||||
/*0694*/ 0x00000000,
|
||||
/*0695*/ 0x00005064,
|
||||
/*0696*/ 0x01421142,
|
||||
/*0697*/ 0x00000142,
|
||||
/*0698*/ 0x00000000,
|
||||
/*0699*/ 0x000f1100,
|
||||
/*069a*/ 0x0f110f11,
|
||||
/*069b*/ 0x09000f11,
|
||||
/*069c*/ 0x00000003,
|
||||
/*069d*/ 0x0002c000,
|
||||
/*069e*/ 0x02c002c0,
|
||||
/*069f*/ 0x000002c0,
|
||||
/*06a0*/ 0x01421142,
|
||||
/*06a1*/ 0x00000142,
|
||||
/*06a2*/ 0x00000000,
|
||||
/*06a3*/ 0x00000000,
|
||||
/*06a4*/ 0x05020000,
|
||||
/*06a5*/ 0x14000000,
|
||||
/*06a6*/ 0x027f6e00,
|
||||
/*06a7*/ 0x047f027f,
|
||||
/*06a8*/ 0x00027f6e,
|
||||
/*06a9*/ 0x00047f6e,
|
||||
/*06aa*/ 0x0003554f,
|
||||
/*06ab*/ 0x0001554f,
|
||||
/*06ac*/ 0x0001554f,
|
||||
/*06ad*/ 0x0001554f,
|
||||
/*06ae*/ 0x0001554f,
|
||||
/*06af*/ 0x00003fee,
|
||||
/*06b0*/ 0x0001554f,
|
||||
/*06b1*/ 0x00003fee,
|
||||
/*06b2*/ 0x0001554f,
|
||||
/*06b3*/ 0x00027f6e,
|
||||
/*06b4*/ 0x0001554f,
|
||||
/*06b5*/ 0x00004011,
|
||||
/*06b6*/ 0x00004410,
|
||||
/*06b7*/ 0x00000000,
|
||||
/*06b8*/ 0x00000000,
|
||||
/*06b9*/ 0x00000000,
|
||||
/*06ba*/ 0x00000065,
|
||||
/*06bb*/ 0x00000000,
|
||||
/*06bc*/ 0x00020201,
|
||||
/*06bd*/ 0x00000000,
|
||||
/*06be*/ 0x03000000,
|
||||
/*06bf*/ 0x00000008,
|
||||
/*06c0*/ 0x00000000,
|
||||
/*06c1*/ 0x00000000,
|
||||
/*06c2*/ 0x00000000,
|
||||
/*06c3*/ 0x00000000,
|
||||
/*06c4*/ 0x00000001,
|
||||
/*06c5*/ 0x00000000,
|
||||
/*06c6*/ 0x00000000,
|
||||
/*06c7*/ 0x00000000,
|
||||
/*06c8*/ 0x000000e4,
|
||||
/*06c9*/ 0x00010198,
|
||||
/*06ca*/ 0x00000000,
|
||||
/*06cb*/ 0x00000000,
|
||||
/*06cc*/ 0x07010000,
|
||||
/*06cd*/ 0x00000104,
|
||||
/*06ce*/ 0x00000000
|
||||
};
|
||||
|
||||
static const uint32_t DDR_PI_REGSET_H3VER2[DDR_PI_REGSET_NUM_H3VER2] = {
|
||||
/*0200*/ 0x00000b00,
|
||||
/*0201*/ 0x00000100,
|
||||
/*0202*/ 0x00640000,
|
||||
/*0203*/ 0x00000000,
|
||||
/*0204*/ 0x0000ffff,
|
||||
/*0205*/ 0x00000000,
|
||||
/*0206*/ 0x0000ffff,
|
||||
/*0207*/ 0x00000000,
|
||||
/*0208*/ 0x0000ffff,
|
||||
/*0209*/ 0x0000304c,
|
||||
/*020a*/ 0x00000200,
|
||||
/*020b*/ 0x00000200,
|
||||
/*020c*/ 0x00000200,
|
||||
/*020d*/ 0x00000200,
|
||||
/*020e*/ 0x0000304c,
|
||||
/*020f*/ 0x00000200,
|
||||
/*0210*/ 0x00000200,
|
||||
/*0211*/ 0x00000200,
|
||||
/*0212*/ 0x00000200,
|
||||
/*0213*/ 0x0000304c,
|
||||
/*0214*/ 0x00000200,
|
||||
/*0215*/ 0x00000200,
|
||||
/*0216*/ 0x00000200,
|
||||
/*0217*/ 0x00000200,
|
||||
/*0218*/ 0x00010000,
|
||||
/*0219*/ 0x00000003,
|
||||
/*021a*/ 0x01000001,
|
||||
/*021b*/ 0x00000000,
|
||||
/*021c*/ 0x00000000,
|
||||
/*021d*/ 0x00000000,
|
||||
/*021e*/ 0x00000000,
|
||||
/*021f*/ 0x00000000,
|
||||
/*0220*/ 0x00000000,
|
||||
/*0221*/ 0x00000000,
|
||||
/*0222*/ 0x00000000,
|
||||
/*0223*/ 0x00000000,
|
||||
/*0224*/ 0x00000000,
|
||||
/*0225*/ 0x00000000,
|
||||
/*0226*/ 0x00000000,
|
||||
/*0227*/ 0x00000000,
|
||||
/*0228*/ 0x00000000,
|
||||
/*0229*/ 0x00000000,
|
||||
/*022a*/ 0x00000000,
|
||||
/*022b*/ 0x0f000101,
|
||||
/*022c*/ 0x08492d25,
|
||||
/*022d*/ 0x500e0c04,
|
||||
/*022e*/ 0x0002500e,
|
||||
/*022f*/ 0x00000301,
|
||||
/*0230*/ 0x00000046,
|
||||
/*0231*/ 0x000000cf,
|
||||
/*0232*/ 0x00001826,
|
||||
/*0233*/ 0x000000cf,
|
||||
/*0234*/ 0x00001826,
|
||||
/*0235*/ 0x00000005,
|
||||
/*0236*/ 0x00000000,
|
||||
/*0237*/ 0x00000000,
|
||||
/*0238*/ 0x00000000,
|
||||
/*0239*/ 0x00000000,
|
||||
/*023a*/ 0x00000000,
|
||||
/*023b*/ 0x00000000,
|
||||
/*023c*/ 0x00000000,
|
||||
/*023d*/ 0x00000000,
|
||||
/*023e*/ 0x04010000,
|
||||
/*023f*/ 0x00000404,
|
||||
/*0240*/ 0x0101280a,
|
||||
/*0241*/ 0x00000000,
|
||||
/*0242*/ 0x00000000,
|
||||
/*0243*/ 0x0003000f,
|
||||
/*0244*/ 0x00000018,
|
||||
/*0245*/ 0x00000000,
|
||||
/*0246*/ 0x00000000,
|
||||
/*0247*/ 0x00060002,
|
||||
/*0248*/ 0x00010001,
|
||||
/*0249*/ 0x01000101,
|
||||
/*024a*/ 0x04020201,
|
||||
/*024b*/ 0x00080804,
|
||||
/*024c*/ 0x00000000,
|
||||
/*024d*/ 0x08030000,
|
||||
/*024e*/ 0x15150408,
|
||||
/*024f*/ 0x00000000,
|
||||
/*0250*/ 0x00000000,
|
||||
/*0251*/ 0x00000000,
|
||||
/*0252*/ 0x0f0f0000,
|
||||
/*0253*/ 0x0000001e,
|
||||
/*0254*/ 0x00000000,
|
||||
/*0255*/ 0x01000300,
|
||||
/*0256*/ 0x00000100,
|
||||
/*0257*/ 0x00000000,
|
||||
/*0258*/ 0x00000000,
|
||||
/*0259*/ 0x01000000,
|
||||
/*025a*/ 0x00000101,
|
||||
/*025b*/ 0x55555a5a,
|
||||
/*025c*/ 0x55555a5a,
|
||||
/*025d*/ 0x55555a5a,
|
||||
/*025e*/ 0x55555a5a,
|
||||
/*025f*/ 0x0e0e0001,
|
||||
/*0260*/ 0x0c0c000e,
|
||||
/*0261*/ 0x0601000c,
|
||||
/*0262*/ 0x17170106,
|
||||
/*0263*/ 0x00020202,
|
||||
/*0264*/ 0x03000000,
|
||||
/*0265*/ 0x00000000,
|
||||
/*0266*/ 0x00181703,
|
||||
/*0267*/ 0x00280006,
|
||||
/*0268*/ 0x00280016,
|
||||
/*0269*/ 0x00000016,
|
||||
/*026a*/ 0x00000000,
|
||||
/*026b*/ 0x00000000,
|
||||
/*026c*/ 0x00000000,
|
||||
/*026d*/ 0x0a000000,
|
||||
/*026e*/ 0x00010a14,
|
||||
/*026f*/ 0x00030005,
|
||||
/*0270*/ 0x0003018d,
|
||||
/*0271*/ 0x000a018d,
|
||||
/*0272*/ 0x00060100,
|
||||
/*0273*/ 0x01000006,
|
||||
/*0274*/ 0x018e018e,
|
||||
/*0275*/ 0x018e0100,
|
||||
/*0276*/ 0x1111018e,
|
||||
/*0277*/ 0x10010204,
|
||||
/*0278*/ 0x09090650,
|
||||
/*0279*/ 0xff110202,
|
||||
/*027a*/ 0x00ff1000,
|
||||
/*027b*/ 0x00ff1000,
|
||||
/*027c*/ 0x04041000,
|
||||
/*027d*/ 0x18020100,
|
||||
/*027e*/ 0x01010018,
|
||||
/*027f*/ 0x004a004a,
|
||||
/*0280*/ 0x004b004a,
|
||||
/*0281*/ 0x050f0000,
|
||||
/*0282*/ 0x0c01021e,
|
||||
/*0283*/ 0x34000000,
|
||||
/*0284*/ 0x00000000,
|
||||
/*0285*/ 0x00000000,
|
||||
/*0286*/ 0x00000000,
|
||||
/*0287*/ 0x00000000,
|
||||
/*0288*/ 0x36312ed4,
|
||||
/*0289*/ 0x2ed41111,
|
||||
/*028a*/ 0x11113631,
|
||||
/*028b*/ 0x36312ed4,
|
||||
/*028c*/ 0xd4001111,
|
||||
/*028d*/ 0x1136312e,
|
||||
/*028e*/ 0x312ed411,
|
||||
/*028f*/ 0xd4111136,
|
||||
/*0290*/ 0x1136312e,
|
||||
/*0291*/ 0x2ed40011,
|
||||
/*0292*/ 0x11113631,
|
||||
/*0293*/ 0x36312ed4,
|
||||
/*0294*/ 0x2ed41111,
|
||||
/*0295*/ 0x11113631,
|
||||
/*0296*/ 0x312ed400,
|
||||
/*0297*/ 0xd4111136,
|
||||
/*0298*/ 0x1136312e,
|
||||
/*0299*/ 0x312ed411,
|
||||
/*029a*/ 0x00111136,
|
||||
/*029b*/ 0x018d0200,
|
||||
/*029c*/ 0x018d018d,
|
||||
/*029d*/ 0x1d220c08,
|
||||
/*029e*/ 0x00001f12,
|
||||
/*029f*/ 0x4301b344,
|
||||
/*02a0*/ 0x10172006,
|
||||
/*02a1*/ 0x121d220c,
|
||||
/*02a2*/ 0x01b3441f,
|
||||
/*02a3*/ 0x17200643,
|
||||
/*02a4*/ 0x1d220c10,
|
||||
/*02a5*/ 0x00001f12,
|
||||
/*02a6*/ 0x4301b344,
|
||||
/*02a7*/ 0x10172006,
|
||||
/*02a8*/ 0x00020002,
|
||||
/*02a9*/ 0x00020002,
|
||||
/*02aa*/ 0x00020002,
|
||||
/*02ab*/ 0x00020002,
|
||||
/*02ac*/ 0x00020002,
|
||||
/*02ad*/ 0x00000000,
|
||||
/*02ae*/ 0x00000000,
|
||||
/*02af*/ 0x00000000,
|
||||
/*02b0*/ 0x00000000,
|
||||
/*02b1*/ 0x00000000,
|
||||
/*02b2*/ 0x00000000,
|
||||
/*02b3*/ 0x00000000,
|
||||
/*02b4*/ 0x00000000,
|
||||
/*02b5*/ 0x00000000,
|
||||
/*02b6*/ 0x00000000,
|
||||
/*02b7*/ 0x00000000,
|
||||
/*02b8*/ 0x00000000,
|
||||
/*02b9*/ 0x00000400,
|
||||
/*02ba*/ 0x05040302,
|
||||
/*02bb*/ 0x01000f0e,
|
||||
/*02bc*/ 0x07060504,
|
||||
/*02bd*/ 0x03020100,
|
||||
/*02be*/ 0x02010000,
|
||||
/*02bf*/ 0x00000103,
|
||||
/*02c0*/ 0x0000304c,
|
||||
/*02c1*/ 0x0001e2f8,
|
||||
/*02c2*/ 0x0000304c,
|
||||
/*02c3*/ 0x0001e2f8,
|
||||
/*02c4*/ 0x0000304c,
|
||||
/*02c5*/ 0x0001e2f8,
|
||||
/*02c6*/ 0x08000000,
|
||||
/*02c7*/ 0x00000100,
|
||||
/*02c8*/ 0x00000000,
|
||||
/*02c9*/ 0x00000000,
|
||||
/*02ca*/ 0x00000000,
|
||||
/*02cb*/ 0x00000000,
|
||||
/*02cc*/ 0x00010000,
|
||||
/*02cd*/ 0x00000000,
|
||||
/*02ce*/ 0x00000000,
|
||||
/*02cf*/ 0x00000000,
|
||||
/*02d0*/ 0x00000000,
|
||||
/*02d1*/ 0x00000000,
|
||||
/*02d2*/ 0x00000000,
|
||||
/*02d3*/ 0x00000000,
|
||||
/*02d4*/ 0x00000000,
|
||||
/*02d5*/ 0x00000000,
|
||||
/*02d6*/ 0x00000000,
|
||||
/*02d7*/ 0x00000000,
|
||||
/*02d8*/ 0x00000000,
|
||||
/*02d9*/ 0x00000000,
|
||||
/*02da*/ 0x00000000,
|
||||
/*02db*/ 0x00000000,
|
||||
/*02dc*/ 0x00000000,
|
||||
/*02dd*/ 0x00000000,
|
||||
/*02de*/ 0x00000000,
|
||||
/*02df*/ 0x00000000,
|
||||
/*02e0*/ 0x00000000,
|
||||
/*02e1*/ 0x00000000,
|
||||
/*02e2*/ 0x00000000,
|
||||
/*02e3*/ 0x00000000,
|
||||
/*02e4*/ 0x00000000,
|
||||
/*02e5*/ 0x00000000,
|
||||
/*02e6*/ 0x00000000,
|
||||
/*02e7*/ 0x00000000,
|
||||
/*02e8*/ 0x00000000,
|
||||
/*02e9*/ 0x00000000,
|
||||
/*02ea*/ 0x00000000,
|
||||
/*02eb*/ 0x00000000,
|
||||
/*02ec*/ 0x00000000,
|
||||
/*02ed*/ 0x00000000,
|
||||
/*02ee*/ 0x00000002,
|
||||
/*02ef*/ 0x00000000,
|
||||
/*02f0*/ 0x00000000,
|
||||
/*02f1*/ 0x00000000,
|
||||
/*02f2*/ 0x00000000,
|
||||
/*02f3*/ 0x00000000,
|
||||
/*02f4*/ 0x00000000
|
||||
};
|
467
drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3.h
Normal file
467
drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3.h
Normal file
|
@ -0,0 +1,467 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#define DDR_PHY_SLICE_REGSET_OFS_M3 0x0800
|
||||
#define DDR_PHY_ADR_V_REGSET_OFS_M3 0x0a00
|
||||
#define DDR_PHY_ADR_I_REGSET_OFS_M3 0x0a80
|
||||
#define DDR_PHY_ADR_G_REGSET_OFS_M3 0x0b80
|
||||
#define DDR_PI_REGSET_OFS_M3 0x0200
|
||||
|
||||
#define DDR_PHY_SLICE_REGSET_SIZE_M3 0x80
|
||||
#define DDR_PHY_ADR_V_REGSET_SIZE_M3 0x80
|
||||
#define DDR_PHY_ADR_I_REGSET_SIZE_M3 0x80
|
||||
#define DDR_PHY_ADR_G_REGSET_SIZE_M3 0x80
|
||||
#define DDR_PI_REGSET_SIZE_M3 0x100
|
||||
|
||||
#define DDR_PHY_SLICE_REGSET_NUM_M3 89
|
||||
#define DDR_PHY_ADR_V_REGSET_NUM_M3 37
|
||||
#define DDR_PHY_ADR_I_REGSET_NUM_M3 37
|
||||
#define DDR_PHY_ADR_G_REGSET_NUM_M3 64
|
||||
#define DDR_PI_REGSET_NUM_M3 202
|
||||
|
||||
static const uint32_t DDR_PHY_SLICE_REGSET_M3[DDR_PHY_SLICE_REGSET_NUM_M3] = {
|
||||
/*0800*/ 0x76543210,
|
||||
/*0801*/ 0x0004f008,
|
||||
/*0802*/ 0x00000000,
|
||||
/*0803*/ 0x00000000,
|
||||
/*0804*/ 0x00010000,
|
||||
/*0805*/ 0x036e6e0e,
|
||||
/*0806*/ 0x026e6e0e,
|
||||
/*0807*/ 0x00010300,
|
||||
/*0808*/ 0x04000100,
|
||||
/*0809*/ 0x00000300,
|
||||
/*080a*/ 0x001700c0,
|
||||
/*080b*/ 0x00b00201,
|
||||
/*080c*/ 0x00030020,
|
||||
/*080d*/ 0x00000000,
|
||||
/*080e*/ 0x00000000,
|
||||
/*080f*/ 0x00000000,
|
||||
/*0810*/ 0x00000000,
|
||||
/*0811*/ 0x00000000,
|
||||
/*0812*/ 0x00000000,
|
||||
/*0813*/ 0x00000000,
|
||||
/*0814*/ 0x09000000,
|
||||
/*0815*/ 0x04080000,
|
||||
/*0816*/ 0x04080400,
|
||||
/*0817*/ 0x00000000,
|
||||
/*0818*/ 0x32103210,
|
||||
/*0819*/ 0x00800708,
|
||||
/*081a*/ 0x000f000c,
|
||||
/*081b*/ 0x00000100,
|
||||
/*081c*/ 0x55aa55aa,
|
||||
/*081d*/ 0x33cc33cc,
|
||||
/*081e*/ 0x0ff00ff0,
|
||||
/*081f*/ 0x0f0ff0f0,
|
||||
/*0820*/ 0x00018e38,
|
||||
/*0821*/ 0x00000000,
|
||||
/*0822*/ 0x00000000,
|
||||
/*0823*/ 0x00000000,
|
||||
/*0824*/ 0x00000000,
|
||||
/*0825*/ 0x00000000,
|
||||
/*0826*/ 0x00000000,
|
||||
/*0827*/ 0x00000000,
|
||||
/*0828*/ 0x00000000,
|
||||
/*0829*/ 0x00000000,
|
||||
/*082a*/ 0x00000000,
|
||||
/*082b*/ 0x00000000,
|
||||
/*082c*/ 0x00000000,
|
||||
/*082d*/ 0x00000000,
|
||||
/*082e*/ 0x00000000,
|
||||
/*082f*/ 0x00000000,
|
||||
/*0830*/ 0x00000000,
|
||||
/*0831*/ 0x00000000,
|
||||
/*0832*/ 0x00000000,
|
||||
/*0833*/ 0x00200000,
|
||||
/*0834*/ 0x08200820,
|
||||
/*0835*/ 0x08200820,
|
||||
/*0836*/ 0x08200820,
|
||||
/*0837*/ 0x08200820,
|
||||
/*0838*/ 0x08200820,
|
||||
/*0839*/ 0x00000820,
|
||||
/*083a*/ 0x03000300,
|
||||
/*083b*/ 0x03000300,
|
||||
/*083c*/ 0x03000300,
|
||||
/*083d*/ 0x03000300,
|
||||
/*083e*/ 0x00000300,
|
||||
/*083f*/ 0x00000000,
|
||||
/*0840*/ 0x00000000,
|
||||
/*0841*/ 0x00000000,
|
||||
/*0842*/ 0x00000000,
|
||||
/*0843*/ 0x00a00000,
|
||||
/*0844*/ 0x00a000a0,
|
||||
/*0845*/ 0x00a000a0,
|
||||
/*0846*/ 0x00a000a0,
|
||||
/*0847*/ 0x00a000a0,
|
||||
/*0848*/ 0x00a000a0,
|
||||
/*0849*/ 0x00a000a0,
|
||||
/*084a*/ 0x00a000a0,
|
||||
/*084b*/ 0x00a000a0,
|
||||
/*084c*/ 0x010900a0,
|
||||
/*084d*/ 0x02000104,
|
||||
/*084e*/ 0x00000000,
|
||||
/*084f*/ 0x00010000,
|
||||
/*0850*/ 0x00000200,
|
||||
/*0851*/ 0x4041a141,
|
||||
/*0852*/ 0xc00141a0,
|
||||
/*0853*/ 0x0e0100c0,
|
||||
/*0854*/ 0x0010000c,
|
||||
/*0855*/ 0x0c064208,
|
||||
/*0856*/ 0x000f0c18,
|
||||
/*0857*/ 0x00e00140,
|
||||
/*0858*/ 0x00000c20
|
||||
};
|
||||
|
||||
static const uint32_t DDR_PHY_ADR_V_REGSET_M3[DDR_PHY_ADR_V_REGSET_NUM_M3] = {
|
||||
/*0a00*/ 0x00000000,
|
||||
/*0a01*/ 0x00000000,
|
||||
/*0a02*/ 0x00000000,
|
||||
/*0a03*/ 0x00000000,
|
||||
/*0a04*/ 0x00000000,
|
||||
/*0a05*/ 0x00000000,
|
||||
/*0a06*/ 0x00000002,
|
||||
/*0a07*/ 0x00000000,
|
||||
/*0a08*/ 0x00000000,
|
||||
/*0a09*/ 0x00000000,
|
||||
/*0a0a*/ 0x00400320,
|
||||
/*0a0b*/ 0x00000040,
|
||||
/*0a0c*/ 0x00dcba98,
|
||||
/*0a0d*/ 0x00000000,
|
||||
/*0a0e*/ 0x00dcba98,
|
||||
/*0a0f*/ 0x01000000,
|
||||
/*0a10*/ 0x00020003,
|
||||
/*0a11*/ 0x00000000,
|
||||
/*0a12*/ 0x00000000,
|
||||
/*0a13*/ 0x00000000,
|
||||
/*0a14*/ 0x0000002a,
|
||||
/*0a15*/ 0x00000015,
|
||||
/*0a16*/ 0x00000015,
|
||||
/*0a17*/ 0x0000002a,
|
||||
/*0a18*/ 0x00000033,
|
||||
/*0a19*/ 0x0000000c,
|
||||
/*0a1a*/ 0x0000000c,
|
||||
/*0a1b*/ 0x00000033,
|
||||
/*0a1c*/ 0x0a418820,
|
||||
/*0a1d*/ 0x003f0000,
|
||||
/*0a1e*/ 0x0000003f,
|
||||
/*0a1f*/ 0x0002c06e,
|
||||
/*0a20*/ 0x02c002c0,
|
||||
/*0a21*/ 0x02c002c0,
|
||||
/*0a22*/ 0x000002c0,
|
||||
/*0a23*/ 0x42080010,
|
||||
/*0a24*/ 0x00000003
|
||||
};
|
||||
|
||||
static const uint32_t DDR_PHY_ADR_I_REGSET_M3[DDR_PHY_ADR_I_REGSET_NUM_M3] = {
|
||||
/*0a80*/ 0x04040404,
|
||||
/*0a81*/ 0x00000404,
|
||||
/*0a82*/ 0x00000000,
|
||||
/*0a83*/ 0x00000000,
|
||||
/*0a84*/ 0x00000000,
|
||||
/*0a85*/ 0x00000000,
|
||||
/*0a86*/ 0x00000002,
|
||||
/*0a87*/ 0x00000000,
|
||||
/*0a88*/ 0x00000000,
|
||||
/*0a89*/ 0x00000000,
|
||||
/*0a8a*/ 0x00400320,
|
||||
/*0a8b*/ 0x00000040,
|
||||
/*0a8c*/ 0x00000000,
|
||||
/*0a8d*/ 0x00000000,
|
||||
/*0a8e*/ 0x00000000,
|
||||
/*0a8f*/ 0x01000000,
|
||||
/*0a90*/ 0x00020003,
|
||||
/*0a91*/ 0x00000000,
|
||||
/*0a92*/ 0x00000000,
|
||||
/*0a93*/ 0x00000000,
|
||||
/*0a94*/ 0x0000002a,
|
||||
/*0a95*/ 0x00000015,
|
||||
/*0a96*/ 0x00000015,
|
||||
/*0a97*/ 0x0000002a,
|
||||
/*0a98*/ 0x00000033,
|
||||
/*0a99*/ 0x0000000c,
|
||||
/*0a9a*/ 0x0000000c,
|
||||
/*0a9b*/ 0x00000033,
|
||||
/*0a9c*/ 0x00000000,
|
||||
/*0a9d*/ 0x00000000,
|
||||
/*0a9e*/ 0x00000000,
|
||||
/*0a9f*/ 0x0002c06e,
|
||||
/*0aa0*/ 0x02c002c0,
|
||||
/*0aa1*/ 0x02c002c0,
|
||||
/*0aa2*/ 0x000002c0,
|
||||
/*0aa3*/ 0x42080010,
|
||||
/*0aa4*/ 0x00000003
|
||||
};
|
||||
|
||||
static const uint32_t DDR_PHY_ADR_G_REGSET_M3[DDR_PHY_ADR_G_REGSET_NUM_M3] = {
|
||||
/*0b80*/ 0x00000001,
|
||||
/*0b81*/ 0x00000000,
|
||||
/*0b82*/ 0x00000005,
|
||||
/*0b83*/ 0x04000f00,
|
||||
/*0b84*/ 0x00020080,
|
||||
/*0b85*/ 0x00020055,
|
||||
/*0b86*/ 0x00000000,
|
||||
/*0b87*/ 0x00000000,
|
||||
/*0b88*/ 0x00000000,
|
||||
/*0b89*/ 0x00000050,
|
||||
/*0b8a*/ 0x00000000,
|
||||
/*0b8b*/ 0x01010100,
|
||||
/*0b8c*/ 0x00000600,
|
||||
/*0b8d*/ 0x50640000,
|
||||
/*0b8e*/ 0x01421142,
|
||||
/*0b8f*/ 0x00000142,
|
||||
/*0b90*/ 0x00000000,
|
||||
/*0b91*/ 0x000f1600,
|
||||
/*0b92*/ 0x0f160f16,
|
||||
/*0b93*/ 0x0f160f16,
|
||||
/*0b94*/ 0x00000003,
|
||||
/*0b95*/ 0x0002c000,
|
||||
/*0b96*/ 0x02c002c0,
|
||||
/*0b97*/ 0x000002c0,
|
||||
/*0b98*/ 0x01421142,
|
||||
/*0b99*/ 0x00000142,
|
||||
/*0b9a*/ 0x00000000,
|
||||
/*0b9b*/ 0x00000000,
|
||||
/*0b9c*/ 0x05020000,
|
||||
/*0b9d*/ 0x00000000,
|
||||
/*0b9e*/ 0x00027f6e,
|
||||
/*0b9f*/ 0x047f027f,
|
||||
/*0ba0*/ 0x00027f6e,
|
||||
/*0ba1*/ 0x00047f6e,
|
||||
/*0ba2*/ 0x0003554f,
|
||||
/*0ba3*/ 0x0001554f,
|
||||
/*0ba4*/ 0x0001554f,
|
||||
/*0ba5*/ 0x0001554f,
|
||||
/*0ba6*/ 0x0001554f,
|
||||
/*0ba7*/ 0x00003fee,
|
||||
/*0ba8*/ 0x0001554f,
|
||||
/*0ba9*/ 0x00003fee,
|
||||
/*0baa*/ 0x0001554f,
|
||||
/*0bab*/ 0x00027f6e,
|
||||
/*0bac*/ 0x0001554f,
|
||||
/*0bad*/ 0x00000000,
|
||||
/*0bae*/ 0x00000000,
|
||||
/*0baf*/ 0x00000000,
|
||||
/*0bb0*/ 0x65000000,
|
||||
/*0bb1*/ 0x00000000,
|
||||
/*0bb2*/ 0x00000000,
|
||||
/*0bb3*/ 0x00000201,
|
||||
/*0bb4*/ 0x00000000,
|
||||
/*0bb5*/ 0x00000000,
|
||||
/*0bb6*/ 0x00000000,
|
||||
/*0bb7*/ 0x00000000,
|
||||
/*0bb8*/ 0x00000000,
|
||||
/*0bb9*/ 0x00000000,
|
||||
/*0bba*/ 0x00000000,
|
||||
/*0bbb*/ 0x00000000,
|
||||
/*0bbc*/ 0x06e40000,
|
||||
/*0bbd*/ 0x00000000,
|
||||
/*0bbe*/ 0x00000000,
|
||||
/*0bbf*/ 0x00010000
|
||||
};
|
||||
|
||||
static const uint32_t DDR_PI_REGSET_M3[DDR_PI_REGSET_NUM_M3] = {
|
||||
/*0200*/ 0x00000b00,
|
||||
/*0201*/ 0x00000100,
|
||||
/*0202*/ 0x00000000,
|
||||
/*0203*/ 0x0000ffff,
|
||||
/*0204*/ 0x00000000,
|
||||
/*0205*/ 0x0000ffff,
|
||||
/*0206*/ 0x00000000,
|
||||
/*0207*/ 0x304cffff,
|
||||
/*0208*/ 0x00000200,
|
||||
/*0209*/ 0x00000200,
|
||||
/*020a*/ 0x00000200,
|
||||
/*020b*/ 0x00000200,
|
||||
/*020c*/ 0x0000304c,
|
||||
/*020d*/ 0x00000200,
|
||||
/*020e*/ 0x00000200,
|
||||
/*020f*/ 0x00000200,
|
||||
/*0210*/ 0x00000200,
|
||||
/*0211*/ 0x0000304c,
|
||||
/*0212*/ 0x00000200,
|
||||
/*0213*/ 0x00000200,
|
||||
/*0214*/ 0x00000200,
|
||||
/*0215*/ 0x00000200,
|
||||
/*0216*/ 0x00010000,
|
||||
/*0217*/ 0x00000003,
|
||||
/*0218*/ 0x01000001,
|
||||
/*0219*/ 0x00000000,
|
||||
/*021a*/ 0x00000000,
|
||||
/*021b*/ 0x00000000,
|
||||
/*021c*/ 0x00000000,
|
||||
/*021d*/ 0x00000000,
|
||||
/*021e*/ 0x00000000,
|
||||
/*021f*/ 0x00000000,
|
||||
/*0220*/ 0x00000000,
|
||||
/*0221*/ 0x00000000,
|
||||
/*0222*/ 0x00000000,
|
||||
/*0223*/ 0x00000000,
|
||||
/*0224*/ 0x00000000,
|
||||
/*0225*/ 0x00000000,
|
||||
/*0226*/ 0x00000000,
|
||||
/*0227*/ 0x00000000,
|
||||
/*0228*/ 0x00000000,
|
||||
/*0229*/ 0x0f000101,
|
||||
/*022a*/ 0x08492d25,
|
||||
/*022b*/ 0x0e0c0004,
|
||||
/*022c*/ 0x000e5000,
|
||||
/*022d*/ 0x00000250,
|
||||
/*022e*/ 0x00460003,
|
||||
/*022f*/ 0x182600cf,
|
||||
/*0230*/ 0x182600cf,
|
||||
/*0231*/ 0x00000005,
|
||||
/*0232*/ 0x00000000,
|
||||
/*0233*/ 0x00000000,
|
||||
/*0234*/ 0x00000000,
|
||||
/*0235*/ 0x00000000,
|
||||
/*0236*/ 0x00000000,
|
||||
/*0237*/ 0x00000000,
|
||||
/*0238*/ 0x00000000,
|
||||
/*0239*/ 0x01000000,
|
||||
/*023a*/ 0x00040404,
|
||||
/*023b*/ 0x01280a00,
|
||||
/*023c*/ 0x00000000,
|
||||
/*023d*/ 0x000f0000,
|
||||
/*023e*/ 0x00001803,
|
||||
/*023f*/ 0x00000000,
|
||||
/*0240*/ 0x00000000,
|
||||
/*0241*/ 0x00060002,
|
||||
/*0242*/ 0x00010001,
|
||||
/*0243*/ 0x01000101,
|
||||
/*0244*/ 0x04020201,
|
||||
/*0245*/ 0x00080804,
|
||||
/*0246*/ 0x00000000,
|
||||
/*0247*/ 0x08030000,
|
||||
/*0248*/ 0x15150408,
|
||||
/*0249*/ 0x00000000,
|
||||
/*024a*/ 0x00000000,
|
||||
/*024b*/ 0x00000000,
|
||||
/*024c*/ 0x000f0f00,
|
||||
/*024d*/ 0x0000001e,
|
||||
/*024e*/ 0x00000000,
|
||||
/*024f*/ 0x01000300,
|
||||
/*0250*/ 0x00000000,
|
||||
/*0251*/ 0x00000000,
|
||||
/*0252*/ 0x01000000,
|
||||
/*0253*/ 0x00010101,
|
||||
/*0254*/ 0x000e0e0e,
|
||||
/*0255*/ 0x000c0c0c,
|
||||
/*0256*/ 0x02060601,
|
||||
/*0257*/ 0x00000000,
|
||||
/*0258*/ 0x00000003,
|
||||
/*0259*/ 0x00181703,
|
||||
/*025a*/ 0x00280006,
|
||||
/*025b*/ 0x00280016,
|
||||
/*025c*/ 0x00000016,
|
||||
/*025d*/ 0x00000000,
|
||||
/*025e*/ 0x00000000,
|
||||
/*025f*/ 0x00000000,
|
||||
/*0260*/ 0x140a0000,
|
||||
/*0261*/ 0x0005010a,
|
||||
/*0262*/ 0x03018d03,
|
||||
/*0263*/ 0x000a018d,
|
||||
/*0264*/ 0x00060100,
|
||||
/*0265*/ 0x01000006,
|
||||
/*0266*/ 0x018e018e,
|
||||
/*0267*/ 0x018e0100,
|
||||
/*0268*/ 0x1111018e,
|
||||
/*0269*/ 0x10010204,
|
||||
/*026a*/ 0x09090650,
|
||||
/*026b*/ 0x20110202,
|
||||
/*026c*/ 0x00201000,
|
||||
/*026d*/ 0x00201000,
|
||||
/*026e*/ 0x04041000,
|
||||
/*026f*/ 0x18020100,
|
||||
/*0270*/ 0x00010118,
|
||||
/*0271*/ 0x004b004a,
|
||||
/*0272*/ 0x050f0000,
|
||||
/*0273*/ 0x0c01021e,
|
||||
/*0274*/ 0x34000000,
|
||||
/*0275*/ 0x00000000,
|
||||
/*0276*/ 0x00000000,
|
||||
/*0277*/ 0x00000000,
|
||||
/*0278*/ 0x0000d400,
|
||||
/*0279*/ 0x0031002e,
|
||||
/*027a*/ 0x00111136,
|
||||
/*027b*/ 0x002e00d4,
|
||||
/*027c*/ 0x11360031,
|
||||
/*027d*/ 0x0000d411,
|
||||
/*027e*/ 0x0031002e,
|
||||
/*027f*/ 0x00111136,
|
||||
/*0280*/ 0x002e00d4,
|
||||
/*0281*/ 0x11360031,
|
||||
/*0282*/ 0x0000d411,
|
||||
/*0283*/ 0x0031002e,
|
||||
/*0284*/ 0x00111136,
|
||||
/*0285*/ 0x002e00d4,
|
||||
/*0286*/ 0x11360031,
|
||||
/*0287*/ 0x00d40011,
|
||||
/*0288*/ 0x0031002e,
|
||||
/*0289*/ 0x00111136,
|
||||
/*028a*/ 0x002e00d4,
|
||||
/*028b*/ 0x11360031,
|
||||
/*028c*/ 0x0000d411,
|
||||
/*028d*/ 0x0031002e,
|
||||
/*028e*/ 0x00111136,
|
||||
/*028f*/ 0x002e00d4,
|
||||
/*0290*/ 0x11360031,
|
||||
/*0291*/ 0x0000d411,
|
||||
/*0292*/ 0x0031002e,
|
||||
/*0293*/ 0x00111136,
|
||||
/*0294*/ 0x002e00d4,
|
||||
/*0295*/ 0x11360031,
|
||||
/*0296*/ 0x02000011,
|
||||
/*0297*/ 0x018d018d,
|
||||
/*0298*/ 0x0c08018d,
|
||||
/*0299*/ 0x1f121d22,
|
||||
/*029a*/ 0x4301b344,
|
||||
/*029b*/ 0x10172006,
|
||||
/*029c*/ 0x1d220c10,
|
||||
/*029d*/ 0x00001f12,
|
||||
/*029e*/ 0x4301b344,
|
||||
/*029f*/ 0x10172006,
|
||||
/*02a0*/ 0x1d220c10,
|
||||
/*02a1*/ 0x00001f12,
|
||||
/*02a2*/ 0x4301b344,
|
||||
/*02a3*/ 0x10172006,
|
||||
/*02a4*/ 0x02000210,
|
||||
/*02a5*/ 0x02000200,
|
||||
/*02a6*/ 0x02000200,
|
||||
/*02a7*/ 0x02000200,
|
||||
/*02a8*/ 0x02000200,
|
||||
/*02a9*/ 0x00000000,
|
||||
/*02aa*/ 0x00000000,
|
||||
/*02ab*/ 0x00000000,
|
||||
/*02ac*/ 0x00000000,
|
||||
/*02ad*/ 0x00000000,
|
||||
/*02ae*/ 0x00000000,
|
||||
/*02af*/ 0x00000000,
|
||||
/*02b0*/ 0x00000000,
|
||||
/*02b1*/ 0x00000000,
|
||||
/*02b2*/ 0x00000000,
|
||||
/*02b3*/ 0x00000000,
|
||||
/*02b4*/ 0x00000000,
|
||||
/*02b5*/ 0x00000400,
|
||||
/*02b6*/ 0x15141312,
|
||||
/*02b7*/ 0x11100f0e,
|
||||
/*02b8*/ 0x080b0c0d,
|
||||
/*02b9*/ 0x05040a09,
|
||||
/*02ba*/ 0x01000706,
|
||||
/*02bb*/ 0x00000302,
|
||||
/*02bc*/ 0x01030201,
|
||||
/*02bd*/ 0x00304c00,
|
||||
/*02be*/ 0x0001e2f8,
|
||||
/*02bf*/ 0x0000304c,
|
||||
/*02c0*/ 0x0001e2f8,
|
||||
/*02c1*/ 0x0000304c,
|
||||
/*02c2*/ 0x0001e2f8,
|
||||
/*02c3*/ 0x08000000,
|
||||
/*02c4*/ 0x00000100,
|
||||
/*02c5*/ 0x00000000,
|
||||
/*02c6*/ 0x00000000,
|
||||
/*02c7*/ 0x00000000,
|
||||
/*02c8*/ 0x00000000,
|
||||
/*02c9*/ 0x00000002
|
||||
};
|
586
drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3n.h
Normal file
586
drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3n.h
Normal file
|
@ -0,0 +1,586 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#define DDR_PHY_SLICE_REGSET_OFS_M3N 0x0800
|
||||
#define DDR_PHY_ADR_V_REGSET_OFS_M3N 0x0a00
|
||||
#define DDR_PHY_ADR_I_REGSET_OFS_M3N 0x0a80
|
||||
#define DDR_PHY_ADR_G_REGSET_OFS_M3N 0x0b80
|
||||
#define DDR_PI_REGSET_OFS_M3N 0x0200
|
||||
|
||||
#define DDR_PHY_SLICE_REGSET_SIZE_M3N 0x80
|
||||
#define DDR_PHY_ADR_V_REGSET_SIZE_M3N 0x80
|
||||
#define DDR_PHY_ADR_I_REGSET_SIZE_M3N 0x80
|
||||
#define DDR_PHY_ADR_G_REGSET_SIZE_M3N 0x80
|
||||
#define DDR_PI_REGSET_SIZE_M3N 0x100
|
||||
|
||||
#define DDR_PHY_SLICE_REGSET_NUM_M3N 101
|
||||
#define DDR_PHY_ADR_V_REGSET_NUM_M3N 37
|
||||
#define DDR_PHY_ADR_I_REGSET_NUM_M3N 37
|
||||
#define DDR_PHY_ADR_G_REGSET_NUM_M3N 87
|
||||
#define DDR_PI_REGSET_NUM_M3N 286
|
||||
|
||||
static const uint32_t DDR_PHY_SLICE_REGSET_M3N[DDR_PHY_SLICE_REGSET_NUM_M3N] = {
|
||||
/*0800*/ 0x76543210,
|
||||
/*0801*/ 0x0004f008,
|
||||
/*0802*/ 0x00020200,
|
||||
/*0803*/ 0x00000000,
|
||||
/*0804*/ 0x00000000,
|
||||
/*0805*/ 0x00010000,
|
||||
/*0806*/ 0x036e6e0e,
|
||||
/*0807*/ 0x026e6e0e,
|
||||
/*0808*/ 0x00000103,
|
||||
/*0809*/ 0x00040001,
|
||||
/*080a*/ 0x00000103,
|
||||
/*080b*/ 0x00000001,
|
||||
/*080c*/ 0x00000000,
|
||||
/*080d*/ 0x00000000,
|
||||
/*080e*/ 0x00000100,
|
||||
/*080f*/ 0x001800c0,
|
||||
/*0810*/ 0x020100b0,
|
||||
/*0811*/ 0x00030020,
|
||||
/*0812*/ 0x00000000,
|
||||
/*0813*/ 0x00000000,
|
||||
/*0814*/ 0x0000aaaa,
|
||||
/*0815*/ 0x00005555,
|
||||
/*0816*/ 0x0000b5b5,
|
||||
/*0817*/ 0x00004a4a,
|
||||
/*0818*/ 0x00000000,
|
||||
/*0819*/ 0x09000000,
|
||||
/*081a*/ 0x04080000,
|
||||
/*081b*/ 0x08040000,
|
||||
/*081c*/ 0x00000004,
|
||||
/*081d*/ 0x00800710,
|
||||
/*081e*/ 0x000f000c,
|
||||
/*081f*/ 0x00000100,
|
||||
/*0820*/ 0x55aa55aa,
|
||||
/*0821*/ 0x33cc33cc,
|
||||
/*0822*/ 0x0ff00ff0,
|
||||
/*0823*/ 0x0f0ff0f0,
|
||||
/*0824*/ 0x00018e38,
|
||||
/*0825*/ 0x00000000,
|
||||
/*0826*/ 0x00000000,
|
||||
/*0827*/ 0x00000000,
|
||||
/*0828*/ 0x00000000,
|
||||
/*0829*/ 0x00000000,
|
||||
/*082a*/ 0x00000000,
|
||||
/*082b*/ 0x00000000,
|
||||
/*082c*/ 0x00000000,
|
||||
/*082d*/ 0x00000000,
|
||||
/*082e*/ 0x00000000,
|
||||
/*082f*/ 0x00000000,
|
||||
/*0830*/ 0x00000000,
|
||||
/*0831*/ 0x00000000,
|
||||
/*0832*/ 0x00000000,
|
||||
/*0833*/ 0x00000000,
|
||||
/*0834*/ 0x00000000,
|
||||
/*0835*/ 0x00000000,
|
||||
/*0836*/ 0x00000000,
|
||||
/*0837*/ 0x00000000,
|
||||
/*0838*/ 0x00000000,
|
||||
/*0839*/ 0x00000000,
|
||||
/*083a*/ 0x00000104,
|
||||
/*083b*/ 0x00082020,
|
||||
/*083c*/ 0x08200820,
|
||||
/*083d*/ 0x08200820,
|
||||
/*083e*/ 0x08200820,
|
||||
/*083f*/ 0x08200820,
|
||||
/*0840*/ 0x08200820,
|
||||
/*0841*/ 0x00000000,
|
||||
/*0842*/ 0x00000000,
|
||||
/*0843*/ 0x03000300,
|
||||
/*0844*/ 0x03000300,
|
||||
/*0845*/ 0x03000300,
|
||||
/*0846*/ 0x03000300,
|
||||
/*0847*/ 0x00000300,
|
||||
/*0848*/ 0x00000000,
|
||||
/*0849*/ 0x00000000,
|
||||
/*084a*/ 0x00000000,
|
||||
/*084b*/ 0x00000000,
|
||||
/*084c*/ 0x00000000,
|
||||
/*084d*/ 0x00a000a0,
|
||||
/*084e*/ 0x00a000a0,
|
||||
/*084f*/ 0x00a000a0,
|
||||
/*0850*/ 0x00a000a0,
|
||||
/*0851*/ 0x00a000a0,
|
||||
/*0852*/ 0x00a000a0,
|
||||
/*0853*/ 0x00a000a0,
|
||||
/*0854*/ 0x00a000a0,
|
||||
/*0855*/ 0x00a000a0,
|
||||
/*0856*/ 0x01040119,
|
||||
/*0857*/ 0x00000200,
|
||||
/*0858*/ 0x01000000,
|
||||
/*0859*/ 0x00000200,
|
||||
/*085a*/ 0x00000004,
|
||||
/*085b*/ 0x4041a141,
|
||||
/*085c*/ 0x0141c0a0,
|
||||
/*085d*/ 0x0000c0c0,
|
||||
/*085e*/ 0x0e0c000e,
|
||||
/*085f*/ 0x10001000,
|
||||
/*0860*/ 0x0c073e42,
|
||||
/*0861*/ 0x000f0c28,
|
||||
/*0862*/ 0x00e00140,
|
||||
/*0863*/ 0x000c0020,
|
||||
/*0864*/ 0x00000203
|
||||
};
|
||||
|
||||
static const uint32_t DDR_PHY_ADR_V_REGSET_M3N[DDR_PHY_ADR_V_REGSET_NUM_M3N] = {
|
||||
/*0a00*/ 0x00000000,
|
||||
/*0a01*/ 0x00000000,
|
||||
/*0a02*/ 0x00000000,
|
||||
/*0a03*/ 0x00000000,
|
||||
/*0a04*/ 0x00000000,
|
||||
/*0a05*/ 0x00000000,
|
||||
/*0a06*/ 0x00000000,
|
||||
/*0a07*/ 0x01000000,
|
||||
/*0a08*/ 0x00020000,
|
||||
/*0a09*/ 0x00000000,
|
||||
/*0a0a*/ 0x00000000,
|
||||
/*0a0b*/ 0x00000000,
|
||||
/*0a0c*/ 0x00400000,
|
||||
/*0a0d*/ 0x00000080,
|
||||
/*0a0e*/ 0x00dcba98,
|
||||
/*0a0f*/ 0x03000000,
|
||||
/*0a10*/ 0x00000200,
|
||||
/*0a11*/ 0x00000000,
|
||||
/*0a12*/ 0x00000000,
|
||||
/*0a13*/ 0x00000000,
|
||||
/*0a14*/ 0x0000002a,
|
||||
/*0a15*/ 0x00000015,
|
||||
/*0a16*/ 0x00000015,
|
||||
/*0a17*/ 0x0000002a,
|
||||
/*0a18*/ 0x00000033,
|
||||
/*0a19*/ 0x0000000c,
|
||||
/*0a1a*/ 0x0000000c,
|
||||
/*0a1b*/ 0x00000033,
|
||||
/*0a1c*/ 0x0a418820,
|
||||
/*0a1d*/ 0x003f0000,
|
||||
/*0a1e*/ 0x0000013f,
|
||||
/*0a1f*/ 0x0002c06e,
|
||||
/*0a20*/ 0x02c002c0,
|
||||
/*0a21*/ 0x02c002c0,
|
||||
/*0a22*/ 0x000002c0,
|
||||
/*0a23*/ 0x42080010,
|
||||
/*0a24*/ 0x0000033e
|
||||
};
|
||||
|
||||
static const uint32_t DDR_PHY_ADR_I_REGSET_M3N[DDR_PHY_ADR_I_REGSET_NUM_M3N] = {
|
||||
/*0a80*/ 0x00000000,
|
||||
/*0a81*/ 0x00000000,
|
||||
/*0a82*/ 0x00000000,
|
||||
/*0a83*/ 0x00000000,
|
||||
/*0a84*/ 0x00000000,
|
||||
/*0a85*/ 0x00000000,
|
||||
/*0a86*/ 0x00000000,
|
||||
/*0a87*/ 0x01000000,
|
||||
/*0a88*/ 0x00020000,
|
||||
/*0a89*/ 0x00000000,
|
||||
/*0a8a*/ 0x00000000,
|
||||
/*0a8b*/ 0x00000000,
|
||||
/*0a8c*/ 0x00400000,
|
||||
/*0a8d*/ 0x00000080,
|
||||
/*0a8e*/ 0x00000000,
|
||||
/*0a8f*/ 0x03000000,
|
||||
/*0a90*/ 0x00000200,
|
||||
/*0a91*/ 0x00000000,
|
||||
/*0a92*/ 0x00000000,
|
||||
/*0a93*/ 0x00000000,
|
||||
/*0a94*/ 0x0000002a,
|
||||
/*0a95*/ 0x00000015,
|
||||
/*0a96*/ 0x00000015,
|
||||
/*0a97*/ 0x0000002a,
|
||||
/*0a98*/ 0x00000033,
|
||||
/*0a99*/ 0x0000000c,
|
||||
/*0a9a*/ 0x0000000c,
|
||||
/*0a9b*/ 0x00000033,
|
||||
/*0a9c*/ 0x00000000,
|
||||
/*0a9d*/ 0x00000000,
|
||||
/*0a9e*/ 0x00000000,
|
||||
/*0a9f*/ 0x0002c06e,
|
||||
/*0aa0*/ 0x02c002c0,
|
||||
/*0aa1*/ 0x02c002c0,
|
||||
/*0aa2*/ 0x000002c0,
|
||||
/*0aa3*/ 0x42080010,
|
||||
/*0aa4*/ 0x0000033e
|
||||
};
|
||||
|
||||
static const uint32_t DDR_PHY_ADR_G_REGSET_M3N[DDR_PHY_ADR_G_REGSET_NUM_M3N] = {
|
||||
/*0b80*/ 0x00000000,
|
||||
/*0b81*/ 0x00000100,
|
||||
/*0b82*/ 0x00000000,
|
||||
/*0b83*/ 0x00050000,
|
||||
/*0b84*/ 0x00000000,
|
||||
/*0b85*/ 0x0004000f,
|
||||
/*0b86*/ 0x00280080,
|
||||
/*0b87*/ 0x02005502,
|
||||
/*0b88*/ 0x00000000,
|
||||
/*0b89*/ 0x00000000,
|
||||
/*0b8a*/ 0x00000000,
|
||||
/*0b8b*/ 0x00000050,
|
||||
/*0b8c*/ 0x00000000,
|
||||
/*0b8d*/ 0x01010100,
|
||||
/*0b8e*/ 0x00010000,
|
||||
/*0b8f*/ 0x00000000,
|
||||
/*0b90*/ 0x00000101,
|
||||
/*0b91*/ 0x00000000,
|
||||
/*0b92*/ 0x00000000,
|
||||
/*0b93*/ 0x00000000,
|
||||
/*0b94*/ 0x00000000,
|
||||
/*0b95*/ 0x00005064,
|
||||
/*0b96*/ 0x01421142,
|
||||
/*0b97*/ 0x00000142,
|
||||
/*0b98*/ 0x00000000,
|
||||
/*0b99*/ 0x000f1600,
|
||||
/*0b9a*/ 0x0f160f16,
|
||||
/*0b9b*/ 0x0f160f16,
|
||||
/*0b9c*/ 0x00000003,
|
||||
/*0b9d*/ 0x0002c000,
|
||||
/*0b9e*/ 0x02c002c0,
|
||||
/*0b9f*/ 0x000002c0,
|
||||
/*0ba0*/ 0x08040201,
|
||||
/*0ba1*/ 0x01421142,
|
||||
/*0ba2*/ 0x00000142,
|
||||
/*0ba3*/ 0x00000000,
|
||||
/*0ba4*/ 0x00000000,
|
||||
/*0ba5*/ 0x05030000,
|
||||
/*0ba6*/ 0x00010700,
|
||||
/*0ba7*/ 0x00000014,
|
||||
/*0ba8*/ 0x00027f6e,
|
||||
/*0ba9*/ 0x047f027f,
|
||||
/*0baa*/ 0x00027f6e,
|
||||
/*0bab*/ 0x00047f6e,
|
||||
/*0bac*/ 0x0003554f,
|
||||
/*0bad*/ 0x0001554f,
|
||||
/*0bae*/ 0x0001554f,
|
||||
/*0baf*/ 0x0001554f,
|
||||
/*0bb0*/ 0x0001554f,
|
||||
/*0bb1*/ 0x00003fee,
|
||||
/*0bb2*/ 0x0001554f,
|
||||
/*0bb3*/ 0x00003fee,
|
||||
/*0bb4*/ 0x0001554f,
|
||||
/*0bb5*/ 0x00027f6e,
|
||||
/*0bb6*/ 0x0001554f,
|
||||
/*0bb7*/ 0x00004011,
|
||||
/*0bb8*/ 0x00004410,
|
||||
/*0bb9*/ 0x00000000,
|
||||
/*0bba*/ 0x00000000,
|
||||
/*0bbb*/ 0x00000000,
|
||||
/*0bbc*/ 0x00000065,
|
||||
/*0bbd*/ 0x00000000,
|
||||
/*0bbe*/ 0x00040401,
|
||||
/*0bbf*/ 0x00000000,
|
||||
/*0bc0*/ 0x03000000,
|
||||
/*0bc1*/ 0x00000020,
|
||||
/*0bc2*/ 0x00000000,
|
||||
/*0bc3*/ 0x00000000,
|
||||
/*0bc4*/ 0x04102006,
|
||||
/*0bc5*/ 0x00041020,
|
||||
/*0bc6*/ 0x01c98c98,
|
||||
/*0bc7*/ 0x00400000,
|
||||
/*0bc8*/ 0x00000000,
|
||||
/*0bc9*/ 0x0001ffff,
|
||||
/*0bca*/ 0x00000000,
|
||||
/*0bcb*/ 0x00000000,
|
||||
/*0bcc*/ 0x00000001,
|
||||
/*0bcd*/ 0x00000000,
|
||||
/*0bce*/ 0x00000000,
|
||||
/*0bcf*/ 0x00000000,
|
||||
/*0bd0*/ 0x76543210,
|
||||
/*0bd1*/ 0x06010198,
|
||||
/*0bd2*/ 0x00000000,
|
||||
/*0bd3*/ 0x00000000,
|
||||
/*0bd4*/ 0x04070000,
|
||||
/*0bd5*/ 0x00000001,
|
||||
/*0bd6*/ 0x00000f00
|
||||
};
|
||||
|
||||
static const uint32_t DDR_PI_REGSET_M3N[DDR_PI_REGSET_NUM_M3N] = {
|
||||
/*0200*/ 0x00000b00,
|
||||
/*0201*/ 0x00000101,
|
||||
/*0202*/ 0x01640000,
|
||||
/*0203*/ 0x00000014,
|
||||
/*0204*/ 0x00000014,
|
||||
/*0205*/ 0x00000014,
|
||||
/*0206*/ 0x00000014,
|
||||
/*0207*/ 0x00000000,
|
||||
/*0208*/ 0x00000000,
|
||||
/*0209*/ 0x0000ffff,
|
||||
/*020a*/ 0x00000000,
|
||||
/*020b*/ 0x0000ffff,
|
||||
/*020c*/ 0x00000000,
|
||||
/*020d*/ 0x0000ffff,
|
||||
/*020e*/ 0x0000304c,
|
||||
/*020f*/ 0x00000200,
|
||||
/*0210*/ 0x00000200,
|
||||
/*0211*/ 0x00000200,
|
||||
/*0212*/ 0x00000200,
|
||||
/*0213*/ 0x0000304c,
|
||||
/*0214*/ 0x00000200,
|
||||
/*0215*/ 0x00000200,
|
||||
/*0216*/ 0x00000200,
|
||||
/*0217*/ 0x00000200,
|
||||
/*0218*/ 0x0000304c,
|
||||
/*0219*/ 0x00000200,
|
||||
/*021a*/ 0x00000200,
|
||||
/*021b*/ 0x00000200,
|
||||
/*021c*/ 0x00000200,
|
||||
/*021d*/ 0x00010000,
|
||||
/*021e*/ 0x00000003,
|
||||
/*021f*/ 0x01000001,
|
||||
/*0220*/ 0x00000000,
|
||||
/*0221*/ 0x00000000,
|
||||
/*0222*/ 0x00000000,
|
||||
/*0223*/ 0x00000000,
|
||||
/*0224*/ 0x00000000,
|
||||
/*0225*/ 0x00000000,
|
||||
/*0226*/ 0x00000000,
|
||||
/*0227*/ 0x00000000,
|
||||
/*0228*/ 0x00000000,
|
||||
/*0229*/ 0x00000000,
|
||||
/*022a*/ 0x00000000,
|
||||
/*022b*/ 0x00000000,
|
||||
/*022c*/ 0x00000000,
|
||||
/*022d*/ 0x00000000,
|
||||
/*022e*/ 0x00000000,
|
||||
/*022f*/ 0x00000000,
|
||||
/*0230*/ 0x0f000101,
|
||||
/*0231*/ 0x084d3129,
|
||||
/*0232*/ 0x0e0c0004,
|
||||
/*0233*/ 0x000e5000,
|
||||
/*0234*/ 0x01000250,
|
||||
/*0235*/ 0x00000003,
|
||||
/*0236*/ 0x00000046,
|
||||
/*0237*/ 0x000000cf,
|
||||
/*0238*/ 0x00001826,
|
||||
/*0239*/ 0x000000cf,
|
||||
/*023a*/ 0x00001826,
|
||||
/*023b*/ 0x00000000,
|
||||
/*023c*/ 0x00000000,
|
||||
/*023d*/ 0x00000000,
|
||||
/*023e*/ 0x00000000,
|
||||
/*023f*/ 0x00000000,
|
||||
/*0240*/ 0x00000000,
|
||||
/*0241*/ 0x00000000,
|
||||
/*0242*/ 0x00000000,
|
||||
/*0243*/ 0x00000000,
|
||||
/*0244*/ 0x00000000,
|
||||
/*0245*/ 0x01000000,
|
||||
/*0246*/ 0x00040404,
|
||||
/*0247*/ 0x01280a00,
|
||||
/*0248*/ 0x00000001,
|
||||
/*0249*/ 0x00000000,
|
||||
/*024a*/ 0x03000f00,
|
||||
/*024b*/ 0x00200020,
|
||||
/*024c*/ 0x00000020,
|
||||
/*024d*/ 0x00000000,
|
||||
/*024e*/ 0x00000000,
|
||||
/*024f*/ 0x00010002,
|
||||
/*0250*/ 0x01010001,
|
||||
/*0251*/ 0x02010100,
|
||||
/*0252*/ 0x08040402,
|
||||
/*0253*/ 0x00000008,
|
||||
/*0254*/ 0x00000000,
|
||||
/*0255*/ 0x04080803,
|
||||
/*0256*/ 0x00001515,
|
||||
/*0257*/ 0x00000000,
|
||||
/*0258*/ 0x000000aa,
|
||||
/*0259*/ 0x00000055,
|
||||
/*025a*/ 0x000000b5,
|
||||
/*025b*/ 0x0000004a,
|
||||
/*025c*/ 0x00000056,
|
||||
/*025d*/ 0x000000a9,
|
||||
/*025e*/ 0x000000a9,
|
||||
/*025f*/ 0x000000b5,
|
||||
/*0260*/ 0x00000000,
|
||||
/*0261*/ 0x00000000,
|
||||
/*0262*/ 0x0f000000,
|
||||
/*0263*/ 0x00001e0f,
|
||||
/*0264*/ 0x000007d0,
|
||||
/*0265*/ 0x01000300,
|
||||
/*0266*/ 0x00000100,
|
||||
/*0267*/ 0x00000000,
|
||||
/*0268*/ 0x00000000,
|
||||
/*0269*/ 0x01000000,
|
||||
/*026a*/ 0x00010101,
|
||||
/*026b*/ 0x000e0e0e,
|
||||
/*026c*/ 0x000c0c0c,
|
||||
/*026d*/ 0x01060601,
|
||||
/*026e*/ 0x04041717,
|
||||
/*026f*/ 0x00000004,
|
||||
/*0270*/ 0x00000300,
|
||||
/*0271*/ 0x17030000,
|
||||
/*0272*/ 0x00060018,
|
||||
/*0273*/ 0x00160028,
|
||||
/*0274*/ 0x00160028,
|
||||
/*0275*/ 0x00000000,
|
||||
/*0276*/ 0x00000000,
|
||||
/*0277*/ 0x00000000,
|
||||
/*0278*/ 0x0a000000,
|
||||
/*0279*/ 0x00010a14,
|
||||
/*027a*/ 0x00030005,
|
||||
/*027b*/ 0x0003018d,
|
||||
/*027c*/ 0x000a018d,
|
||||
/*027d*/ 0x00060100,
|
||||
/*027e*/ 0x01000006,
|
||||
/*027f*/ 0x018e018e,
|
||||
/*0280*/ 0x018e0100,
|
||||
/*0281*/ 0x1e1a018e,
|
||||
/*0282*/ 0x1e1a1e1a,
|
||||
/*0283*/ 0x01010204,
|
||||
/*0284*/ 0x06501001,
|
||||
/*0285*/ 0x090d0a07,
|
||||
/*0286*/ 0x090d0a07,
|
||||
/*0287*/ 0x0811180f,
|
||||
/*0288*/ 0x00ff1102,
|
||||
/*0289*/ 0x00ff1000,
|
||||
/*028a*/ 0x00ff1000,
|
||||
/*028b*/ 0x04041000,
|
||||
/*028c*/ 0x18020100,
|
||||
/*028d*/ 0x01010018,
|
||||
/*028e*/ 0x005f005f,
|
||||
/*028f*/ 0x005f005f,
|
||||
/*0290*/ 0x050f0000,
|
||||
/*0291*/ 0x051e051e,
|
||||
/*0292*/ 0x0c01021e,
|
||||
/*0293*/ 0x00000c0c,
|
||||
/*0294*/ 0x00003400,
|
||||
/*0295*/ 0x00000000,
|
||||
/*0296*/ 0x00000000,
|
||||
/*0297*/ 0x00000000,
|
||||
/*0298*/ 0x00000000,
|
||||
/*0299*/ 0x002e00d4,
|
||||
/*029a*/ 0x11360031,
|
||||
/*029b*/ 0x00d41611,
|
||||
/*029c*/ 0x0031002e,
|
||||
/*029d*/ 0x16111136,
|
||||
/*029e*/ 0x002e00d4,
|
||||
/*029f*/ 0x11360031,
|
||||
/*02a0*/ 0x00001611,
|
||||
/*02a1*/ 0x002e00d4,
|
||||
/*02a2*/ 0x11360031,
|
||||
/*02a3*/ 0x00d41611,
|
||||
/*02a4*/ 0x0031002e,
|
||||
/*02a5*/ 0x16111136,
|
||||
/*02a6*/ 0x002e00d4,
|
||||
/*02a7*/ 0x11360031,
|
||||
/*02a8*/ 0x00001611,
|
||||
/*02a9*/ 0x002e00d4,
|
||||
/*02aa*/ 0x11360031,
|
||||
/*02ab*/ 0x00d41611,
|
||||
/*02ac*/ 0x0031002e,
|
||||
/*02ad*/ 0x16111136,
|
||||
/*02ae*/ 0x002e00d4,
|
||||
/*02af*/ 0x11360031,
|
||||
/*02b0*/ 0x00001611,
|
||||
/*02b1*/ 0x002e00d4,
|
||||
/*02b2*/ 0x11360031,
|
||||
/*02b3*/ 0x00d41611,
|
||||
/*02b4*/ 0x0031002e,
|
||||
/*02b5*/ 0x16111136,
|
||||
/*02b6*/ 0x002e00d4,
|
||||
/*02b7*/ 0x11360031,
|
||||
/*02b8*/ 0x00001611,
|
||||
/*02b9*/ 0x00018d00,
|
||||
/*02ba*/ 0x018d018d,
|
||||
/*02bb*/ 0x1d220c08,
|
||||
/*02bc*/ 0x00001f12,
|
||||
/*02bd*/ 0x4301b344,
|
||||
/*02be*/ 0x17032006,
|
||||
/*02bf*/ 0x220c1010,
|
||||
/*02c0*/ 0x001f121d,
|
||||
/*02c1*/ 0x4301b344,
|
||||
/*02c2*/ 0x17062006,
|
||||
/*02c3*/ 0x220c1010,
|
||||
/*02c4*/ 0x001f121d,
|
||||
/*02c5*/ 0x4301b344,
|
||||
/*02c6*/ 0x17182006,
|
||||
/*02c7*/ 0x00021010,
|
||||
/*02c8*/ 0x00020002,
|
||||
/*02c9*/ 0x00020002,
|
||||
/*02ca*/ 0x00020002,
|
||||
/*02cb*/ 0x00020002,
|
||||
/*02cc*/ 0x00000002,
|
||||
/*02cd*/ 0x00000000,
|
||||
/*02ce*/ 0x00000000,
|
||||
/*02cf*/ 0x00000000,
|
||||
/*02d0*/ 0x00000000,
|
||||
/*02d1*/ 0x00000000,
|
||||
/*02d2*/ 0x00000000,
|
||||
/*02d3*/ 0x00000000,
|
||||
/*02d4*/ 0x00000000,
|
||||
/*02d5*/ 0x00000000,
|
||||
/*02d6*/ 0x00000000,
|
||||
/*02d7*/ 0x00000000,
|
||||
/*02d8*/ 0x00000000,
|
||||
/*02d9*/ 0x00000400,
|
||||
/*02da*/ 0x15141312,
|
||||
/*02db*/ 0x11100f0e,
|
||||
/*02dc*/ 0x080b0c0d,
|
||||
/*02dd*/ 0x05040a09,
|
||||
/*02de*/ 0x01000706,
|
||||
/*02df*/ 0x00000302,
|
||||
/*02e0*/ 0x01030201,
|
||||
/*02e1*/ 0x00304c08,
|
||||
/*02e2*/ 0x0001e2f8,
|
||||
/*02e3*/ 0x0000304c,
|
||||
/*02e4*/ 0x0001e2f8,
|
||||
/*02e5*/ 0x0000304c,
|
||||
/*02e6*/ 0x0001e2f8,
|
||||
/*02e7*/ 0x08000000,
|
||||
/*02e8*/ 0x00000100,
|
||||
/*02e9*/ 0x00000000,
|
||||
/*02ea*/ 0x00000000,
|
||||
/*02eb*/ 0x00000000,
|
||||
/*02ec*/ 0x00000000,
|
||||
/*02ed*/ 0x00010000,
|
||||
/*02ee*/ 0x00000000,
|
||||
/*02ef*/ 0x00000000,
|
||||
/*02f0*/ 0x00000000,
|
||||
/*02f1*/ 0x00000000,
|
||||
/*02f2*/ 0x00000000,
|
||||
/*02f3*/ 0x00000000,
|
||||
/*02f4*/ 0x00000000,
|
||||
/*02f5*/ 0x00000000,
|
||||
/*02f6*/ 0x00000000,
|
||||
/*02f7*/ 0x00000000,
|
||||
/*02f8*/ 0x00000000,
|
||||
/*02f9*/ 0x00000000,
|
||||
/*02fa*/ 0x00000000,
|
||||
/*02fb*/ 0x00000000,
|
||||
/*02fc*/ 0x00000000,
|
||||
/*02fd*/ 0x00000000,
|
||||
/*02fe*/ 0x00000000,
|
||||
/*02ff*/ 0x00000000,
|
||||
/*0300*/ 0x00000000,
|
||||
/*0301*/ 0x00000000,
|
||||
/*0302*/ 0x00000000,
|
||||
/*0303*/ 0x00000000,
|
||||
/*0304*/ 0x00000000,
|
||||
/*0305*/ 0x00000000,
|
||||
/*0306*/ 0x00000000,
|
||||
/*0307*/ 0x00000000,
|
||||
/*0308*/ 0x00000000,
|
||||
/*0309*/ 0x00000000,
|
||||
/*030a*/ 0x00000000,
|
||||
/*030b*/ 0x00000000,
|
||||
/*030c*/ 0x00000000,
|
||||
/*030d*/ 0x00000000,
|
||||
/*030e*/ 0x00000000,
|
||||
/*030f*/ 0x00050002,
|
||||
/*0310*/ 0x015c0057,
|
||||
/*0311*/ 0x01000100,
|
||||
/*0312*/ 0x01020001,
|
||||
/*0313*/ 0x00010300,
|
||||
/*0314*/ 0x05000104,
|
||||
/*0315*/ 0x01060001,
|
||||
/*0316*/ 0x00010700,
|
||||
/*0317*/ 0x00000000,
|
||||
/*0318*/ 0x00000000,
|
||||
/*0319*/ 0x00000001,
|
||||
/*031a*/ 0x00000000,
|
||||
/*031b*/ 0x00000000,
|
||||
/*031c*/ 0x00000000,
|
||||
/*031d*/ 0x20080101
|
||||
};
|
161
drivers/staging/renesas/rcar/ddr/dram_sub_func.c
Normal file
161
drivers/staging/renesas/rcar/ddr/dram_sub_func.c
Normal file
|
@ -0,0 +1,161 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <mmio.h>
|
||||
#include <debug.h>
|
||||
#include "dram_sub_func.h"
|
||||
|
||||
#define PRR (0xFFF00044U)
|
||||
#define PRR_PRODUCT_MASK (0x00007F00U)
|
||||
#define PRR_CUT_MASK (0x000000FFU)
|
||||
#define PRR_PRODUCT_H3 (0x00004F00U) /* R-Car H3 */
|
||||
#define PRR_PRODUCT_M3 (0x00005200U) /* R-Car M3 */
|
||||
#define PRR_PRODUCT_M3N (0x00005500U) /* R-Car M3N */
|
||||
#define PRR_PRODUCT_E3 (0x00005700U) /* R-Car E3 */
|
||||
#define PRR_PRODUCT_V3H (0x00005600U) /* R-Car V3H */
|
||||
|
||||
#if RCAR_SYSTEM_SUSPEND
|
||||
#include "iic_dvfs.h"
|
||||
|
||||
#define DRAM_BACKUP_GPIO_USE (0)
|
||||
#if PMIC_ROHM_BD9571
|
||||
#define PMIC_BKUP_MODE_CNT (0x20U)
|
||||
#define PMIC_QLLM_CNT (0x27U)
|
||||
#define BIT_BKUP_CTRL_OUT ((uint8_t)(1U << 4U))
|
||||
#define BIT_QLLM_DDR0_EN ((uint8_t)(1U << 0U))
|
||||
#define BIT_QLLM_DDR1_EN ((uint8_t)(1U << 1U))
|
||||
#endif
|
||||
|
||||
#define GPIO_OUTDT1 (0xE6051008U)
|
||||
#define GPIO_INDT1 (0xE605100CU)
|
||||
#define GPIO_OUTDT3 (0xE6053008U)
|
||||
#define GPIO_INDT3 (0xE605300CU)
|
||||
#define GPIO_OUTDT6 (0xE6055408U)
|
||||
#define GPIO_INDT6 (0xE605540CU)
|
||||
|
||||
#if DRAM_BACKUP_GPIO_USE == 1
|
||||
#define GPIO_BKUP_REQB_SHIFT_SALVATOR (9U) /* GP1_9 (BKUP_REQB) */
|
||||
#define GPIO_BKUP_REQB_SHIFT_EBISU (14U) /* GP6_14(BKUP_REQB) */
|
||||
#define GPIO_BKUP_REQB_SHIFT_CONDOR (1U) /* GP3_1 (BKUP_REQB) */
|
||||
#endif
|
||||
#define GPIO_BKUP_TRG_SHIFT_SALVATOR (8U) /* GP1_8 (BKUP_TRG) */
|
||||
#define GPIO_BKUP_TRG_SHIFT_EBISU (13U) /* GP6_13(BKUP_TRG) */
|
||||
#define GPIO_BKUP_TRG_SHIFT_CONDOR (0U) /* GP3_0 (BKUP_TRG) */
|
||||
|
||||
#define DRAM_BKUP_TRG_LOOP_CNT (1000U)
|
||||
#endif
|
||||
|
||||
void rcar_dram_get_boot_status(uint32_t * status)
|
||||
{
|
||||
#if RCAR_SYSTEM_SUSPEND
|
||||
uint32_t shift = GPIO_BKUP_TRG_SHIFT_SALVATOR;
|
||||
uint32_t gpio = GPIO_INDT1;
|
||||
uint32_t reg, product;
|
||||
|
||||
product = mmio_read_32(PRR) & PRR_PRODUCT_MASK;
|
||||
|
||||
if (product == PRR_PRODUCT_V3H) {
|
||||
shift = GPIO_BKUP_TRG_SHIFT_CONDOR;
|
||||
gpio = GPIO_INDT3;
|
||||
} else if (product == PRR_PRODUCT_E3) {
|
||||
shift = GPIO_BKUP_TRG_SHIFT_EBISU;
|
||||
gpio = GPIO_INDT6;
|
||||
}
|
||||
|
||||
reg = mmio_read_32(gpio) & (1U << shift);
|
||||
*status = reg ? DRAM_BOOT_STATUS_WARM : DRAM_BOOT_STATUS_COLD;
|
||||
#else
|
||||
*status = DRAM_BOOT_STATUS_COLD;
|
||||
#endif
|
||||
}
|
||||
|
||||
int32_t rcar_dram_update_boot_status(uint32_t status)
|
||||
{
|
||||
int32_t ret = 0;
|
||||
#if RCAR_SYSTEM_SUSPEND
|
||||
#if PMIC_ROHM_BD9571
|
||||
#if DRAM_BACKUP_GPIO_USE == 0
|
||||
uint8_t mode = 0U;
|
||||
#else
|
||||
uint32_t reqb, outd;
|
||||
#endif
|
||||
uint8_t qllm = 0;
|
||||
#endif
|
||||
uint32_t i, product, trg, gpio;
|
||||
|
||||
product = mmio_read_32(PRR) & PRR_PRODUCT_MASK;
|
||||
if (product == PRR_PRODUCT_V3H) {
|
||||
#if DRAM_BACKUP_GPIO_USE == 1
|
||||
reqb = GPIO_BKUP_REQB_SHIFT_CONDOR;
|
||||
outd = GPIO_OUTDT3;
|
||||
#endif
|
||||
trg = GPIO_BKUP_TRG_SHIFT_CONDOR;
|
||||
gpio = GPIO_INDT3;
|
||||
} else if (product == PRR_PRODUCT_E3) {
|
||||
#if DRAM_BACKUP_GPIO_USE == 1
|
||||
reqb = GPIO_BKUP_REQB_SHIFT_EBISU;
|
||||
outd = GPIO_OUTDT6;
|
||||
#endif
|
||||
trg = GPIO_BKUP_TRG_SHIFT_EBISU;
|
||||
gpio = GPIO_INDT6;
|
||||
} else {
|
||||
#if DRAM_BACKUP_GPIO_USE == 1
|
||||
reqb = GPIO_BKUP_REQB_SHIFT_SALVATOR;
|
||||
outd = GPIO_OUTDT1;
|
||||
#endif
|
||||
trg = GPIO_BKUP_TRG_SHIFT_SALVATOR;
|
||||
gpio = GPIO_INDT1;
|
||||
}
|
||||
|
||||
if (status != DRAM_BOOT_STATUS_WARM)
|
||||
goto cold;
|
||||
|
||||
#if DRAM_BACKUP_GPIO_USE==1
|
||||
mmio_setbits_32(outd, 1U << reqb);
|
||||
#else
|
||||
|
||||
#if PMIC_ROHM_BD9571
|
||||
if (rcar_iic_dvfs_receive(PMIC, PMIC_BKUP_MODE_CNT, &mode)) {
|
||||
ERROR("BKUP mode cnt READ ERROR.\n");
|
||||
return DRAM_UPDATE_STATUS_ERR;
|
||||
}
|
||||
|
||||
mode &= ~BIT_BKUP_CTRL_OUT;
|
||||
if (rcar_iic_dvfs_send(PMIC, PMIC_BKUP_MODE_CNT, mode)) {
|
||||
ERROR("BKUP mode cnt WRITE ERROR. value = %d\n", mode);
|
||||
return DRAM_UPDATE_STATUS_ERR;
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
for (i = 0; i < DRAM_BKUP_TRG_LOOP_CNT; i++) {
|
||||
if (mmio_read_32(gpio) & (1U << trg))
|
||||
continue;
|
||||
|
||||
goto cold;
|
||||
}
|
||||
|
||||
ERROR("\nWarm booting Error...\n"
|
||||
" The potential of BKUP_TRG did not switch "
|
||||
"to Low.\n If you expect the operation of "
|
||||
"cold boot,\n check the board configuration"
|
||||
" (ex, Dip-SW) and/or the H/W failure.\n");
|
||||
|
||||
return DRAM_UPDATE_STATUS_ERR;
|
||||
|
||||
cold:
|
||||
#if PMIC_ROHM_BD9571
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
qllm = (BIT_QLLM_DDR0_EN | BIT_QLLM_DDR1_EN);
|
||||
if (rcar_iic_dvfs_send(PMIC, PMIC_QLLM_CNT, qllm)) {
|
||||
ERROR("QLLM cnt WRITE ERROR. value = %d\n", qllm);
|
||||
ret = DRAM_UPDATE_STATUS_ERR;
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
return ret;
|
||||
}
|
17
drivers/staging/renesas/rcar/ddr/dram_sub_func.h
Normal file
17
drivers/staging/renesas/rcar/ddr/dram_sub_func.h
Normal file
|
@ -0,0 +1,17 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef DRAM_SUB_FUNC_H_
|
||||
#define DRAM_SUB_FUNC_H_
|
||||
|
||||
#define DRAM_UPDATE_STATUS_ERR (-1)
|
||||
#define DRAM_BOOT_STATUS_COLD (0)
|
||||
#define DRAM_BOOT_STATUS_WARM (1)
|
||||
|
||||
int32_t rcar_dram_update_boot_status(uint32_t status);
|
||||
void rcar_dram_get_boot_status(uint32_t * status);
|
||||
|
||||
#endif
|
800
drivers/staging/renesas/rcar/pfc/E3/pfc_init_e3.c
Normal file
800
drivers/staging/renesas/rcar/pfc/E3/pfc_init_e3.c
Normal file
|
@ -0,0 +1,800 @@
|
|||
/*
|
||||
* Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <stdint.h> /* for uint32_t */
|
||||
#include <mmio.h>
|
||||
#include "pfc_init_e3.h"
|
||||
#include "rcar_def.h"
|
||||
|
||||
/* GPIO base address */
|
||||
#define GPIO_BASE (0xE6050000U)
|
||||
|
||||
/* GPIO registers */
|
||||
#define GPIO_IOINTSEL0 (GPIO_BASE + 0x0000U)
|
||||
#define GPIO_INOUTSEL0 (GPIO_BASE + 0x0004U)
|
||||
#define GPIO_OUTDT0 (GPIO_BASE + 0x0008U)
|
||||
#define GPIO_INDT0 (GPIO_BASE + 0x000CU)
|
||||
#define GPIO_INTDT0 (GPIO_BASE + 0x0010U)
|
||||
#define GPIO_INTCLR0 (GPIO_BASE + 0x0014U)
|
||||
#define GPIO_INTMSK0 (GPIO_BASE + 0x0018U)
|
||||
#define GPIO_MSKCLR0 (GPIO_BASE + 0x001CU)
|
||||
#define GPIO_POSNEG0 (GPIO_BASE + 0x0020U)
|
||||
#define GPIO_EDGLEVEL0 (GPIO_BASE + 0x0024U)
|
||||
#define GPIO_FILONOFF0 (GPIO_BASE + 0x0028U)
|
||||
#define GPIO_INTMSKS0 (GPIO_BASE + 0x0038U)
|
||||
#define GPIO_MSKCLRS0 (GPIO_BASE + 0x003CU)
|
||||
#define GPIO_OUTDTSEL0 (GPIO_BASE + 0x0040U)
|
||||
#define GPIO_OUTDTH0 (GPIO_BASE + 0x0044U)
|
||||
#define GPIO_OUTDTL0 (GPIO_BASE + 0x0048U)
|
||||
#define GPIO_BOTHEDGE0 (GPIO_BASE + 0x004CU)
|
||||
#define GPIO_IOINTSEL1 (GPIO_BASE + 0x1000U)
|
||||
#define GPIO_INOUTSEL1 (GPIO_BASE + 0x1004U)
|
||||
#define GPIO_OUTDT1 (GPIO_BASE + 0x1008U)
|
||||
#define GPIO_INDT1 (GPIO_BASE + 0x100CU)
|
||||
#define GPIO_INTDT1 (GPIO_BASE + 0x1010U)
|
||||
#define GPIO_INTCLR1 (GPIO_BASE + 0x1014U)
|
||||
#define GPIO_INTMSK1 (GPIO_BASE + 0x1018U)
|
||||
#define GPIO_MSKCLR1 (GPIO_BASE + 0x101CU)
|
||||
#define GPIO_POSNEG1 (GPIO_BASE + 0x1020U)
|
||||
#define GPIO_EDGLEVEL1 (GPIO_BASE + 0x1024U)
|
||||
#define GPIO_FILONOFF1 (GPIO_BASE + 0x1028U)
|
||||
#define GPIO_INTMSKS1 (GPIO_BASE + 0x1038U)
|
||||
#define GPIO_MSKCLRS1 (GPIO_BASE + 0x103CU)
|
||||
#define GPIO_OUTDTSEL1 (GPIO_BASE + 0x1040U)
|
||||
#define GPIO_OUTDTH1 (GPIO_BASE + 0x1044U)
|
||||
#define GPIO_OUTDTL1 (GPIO_BASE + 0x1048U)
|
||||
#define GPIO_BOTHEDGE1 (GPIO_BASE + 0x104CU)
|
||||
#define GPIO_IOINTSEL2 (GPIO_BASE + 0x2000U)
|
||||
#define GPIO_INOUTSEL2 (GPIO_BASE + 0x2004U)
|
||||
#define GPIO_OUTDT2 (GPIO_BASE + 0x2008U)
|
||||
#define GPIO_INDT2 (GPIO_BASE + 0x200CU)
|
||||
#define GPIO_INTDT2 (GPIO_BASE + 0x2010U)
|
||||
#define GPIO_INTCLR2 (GPIO_BASE + 0x2014U)
|
||||
#define GPIO_INTMSK2 (GPIO_BASE + 0x2018U)
|
||||
#define GPIO_MSKCLR2 (GPIO_BASE + 0x201CU)
|
||||
#define GPIO_POSNEG2 (GPIO_BASE + 0x2020U)
|
||||
#define GPIO_EDGLEVEL2 (GPIO_BASE + 0x2024U)
|
||||
#define GPIO_FILONOFF2 (GPIO_BASE + 0x2028U)
|
||||
#define GPIO_INTMSKS2 (GPIO_BASE + 0x2038U)
|
||||
#define GPIO_MSKCLRS2 (GPIO_BASE + 0x203CU)
|
||||
#define GPIO_OUTDTSEL2 (GPIO_BASE + 0x2040U)
|
||||
#define GPIO_OUTDTH2 (GPIO_BASE + 0x2044U)
|
||||
#define GPIO_OUTDTL2 (GPIO_BASE + 0x2048U)
|
||||
#define GPIO_BOTHEDGE2 (GPIO_BASE + 0x204CU)
|
||||
#define GPIO_IOINTSEL3 (GPIO_BASE + 0x3000U)
|
||||
#define GPIO_INOUTSEL3 (GPIO_BASE + 0x3004U)
|
||||
#define GPIO_OUTDT3 (GPIO_BASE + 0x3008U)
|
||||
#define GPIO_INDT3 (GPIO_BASE + 0x300CU)
|
||||
#define GPIO_INTDT3 (GPIO_BASE + 0x3010U)
|
||||
#define GPIO_INTCLR3 (GPIO_BASE + 0x3014U)
|
||||
#define GPIO_INTMSK3 (GPIO_BASE + 0x3018U)
|
||||
#define GPIO_MSKCLR3 (GPIO_BASE + 0x301CU)
|
||||
#define GPIO_POSNEG3 (GPIO_BASE + 0x3020U)
|
||||
#define GPIO_EDGLEVEL3 (GPIO_BASE + 0x3024U)
|
||||
#define GPIO_FILONOFF3 (GPIO_BASE + 0x3028U)
|
||||
#define GPIO_INTMSKS3 (GPIO_BASE + 0x3038U)
|
||||
#define GPIO_MSKCLRS3 (GPIO_BASE + 0x303CU)
|
||||
#define GPIO_OUTDTSEL3 (GPIO_BASE + 0x3040U)
|
||||
#define GPIO_OUTDTH3 (GPIO_BASE + 0x3044U)
|
||||
#define GPIO_OUTDTL3 (GPIO_BASE + 0x3048U)
|
||||
#define GPIO_BOTHEDGE3 (GPIO_BASE + 0x304CU)
|
||||
#define GPIO_IOINTSEL4 (GPIO_BASE + 0x4000U)
|
||||
#define GPIO_INOUTSEL4 (GPIO_BASE + 0x4004U)
|
||||
#define GPIO_OUTDT4 (GPIO_BASE + 0x4008U)
|
||||
#define GPIO_INDT4 (GPIO_BASE + 0x400CU)
|
||||
#define GPIO_INTDT4 (GPIO_BASE + 0x4010U)
|
||||
#define GPIO_INTCLR4 (GPIO_BASE + 0x4014U)
|
||||
#define GPIO_INTMSK4 (GPIO_BASE + 0x4018U)
|
||||
#define GPIO_MSKCLR4 (GPIO_BASE + 0x401CU)
|
||||
#define GPIO_POSNEG4 (GPIO_BASE + 0x4020U)
|
||||
#define GPIO_EDGLEVEL4 (GPIO_BASE + 0x4024U)
|
||||
#define GPIO_FILONOFF4 (GPIO_BASE + 0x4028U)
|
||||
#define GPIO_INTMSKS4 (GPIO_BASE + 0x4038U)
|
||||
#define GPIO_MSKCLRS4 (GPIO_BASE + 0x403CU)
|
||||
#define GPIO_OUTDTSEL4 (GPIO_BASE + 0x4040U)
|
||||
#define GPIO_OUTDTH4 (GPIO_BASE + 0x4044U)
|
||||
#define GPIO_OUTDTL4 (GPIO_BASE + 0x4048U)
|
||||
#define GPIO_BOTHEDGE4 (GPIO_BASE + 0x404CU)
|
||||
#define GPIO_IOINTSEL5 (GPIO_BASE + 0x5000U)
|
||||
#define GPIO_INOUTSEL5 (GPIO_BASE + 0x5004U)
|
||||
#define GPIO_OUTDT5 (GPIO_BASE + 0x5008U)
|
||||
#define GPIO_INDT5 (GPIO_BASE + 0x500CU)
|
||||
#define GPIO_INTDT5 (GPIO_BASE + 0x5010U)
|
||||
#define GPIO_INTCLR5 (GPIO_BASE + 0x5014U)
|
||||
#define GPIO_INTMSK5 (GPIO_BASE + 0x5018U)
|
||||
#define GPIO_MSKCLR5 (GPIO_BASE + 0x501CU)
|
||||
#define GPIO_POSNEG5 (GPIO_BASE + 0x5020U)
|
||||
#define GPIO_EDGLEVEL5 (GPIO_BASE + 0x5024U)
|
||||
#define GPIO_FILONOFF5 (GPIO_BASE + 0x5028U)
|
||||
#define GPIO_INTMSKS5 (GPIO_BASE + 0x5038U)
|
||||
#define GPIO_MSKCLRS5 (GPIO_BASE + 0x503CU)
|
||||
#define GPIO_OUTDTSEL5 (GPIO_BASE + 0x5040U)
|
||||
#define GPIO_OUTDTH5 (GPIO_BASE + 0x5044U)
|
||||
#define GPIO_OUTDTL5 (GPIO_BASE + 0x5048U)
|
||||
#define GPIO_BOTHEDGE5 (GPIO_BASE + 0x504CU)
|
||||
#define GPIO_IOINTSEL6 (GPIO_BASE + 0x5400U)
|
||||
#define GPIO_INOUTSEL6 (GPIO_BASE + 0x5404U)
|
||||
#define GPIO_OUTDT6 (GPIO_BASE + 0x5408U)
|
||||
#define GPIO_INDT6 (GPIO_BASE + 0x540CU)
|
||||
#define GPIO_INTDT6 (GPIO_BASE + 0x5410U)
|
||||
#define GPIO_INTCLR6 (GPIO_BASE + 0x5414U)
|
||||
#define GPIO_INTMSK6 (GPIO_BASE + 0x5418U)
|
||||
#define GPIO_MSKCLR6 (GPIO_BASE + 0x541CU)
|
||||
#define GPIO_POSNEG6 (GPIO_BASE + 0x5420U)
|
||||
#define GPIO_EDGLEVEL6 (GPIO_BASE + 0x5424U)
|
||||
#define GPIO_FILONOFF6 (GPIO_BASE + 0x5428U)
|
||||
#define GPIO_INTMSKS6 (GPIO_BASE + 0x5438U)
|
||||
#define GPIO_MSKCLRS6 (GPIO_BASE + 0x543CU)
|
||||
#define GPIO_OUTDTSEL6 (GPIO_BASE + 0x5440U)
|
||||
#define GPIO_OUTDTH6 (GPIO_BASE + 0x5444U)
|
||||
#define GPIO_OUTDTL6 (GPIO_BASE + 0x5448U)
|
||||
#define GPIO_BOTHEDGE6 (GPIO_BASE + 0x544CU)
|
||||
|
||||
/* Pin functon base address */
|
||||
#define PFC_BASE (0xE6060000U)
|
||||
|
||||
/* Pin functon registers */
|
||||
#define PFC_PMMR (PFC_BASE + 0x0000U)
|
||||
#define PFC_GPSR0 (PFC_BASE + 0x0100U)
|
||||
#define PFC_GPSR1 (PFC_BASE + 0x0104U)
|
||||
#define PFC_GPSR2 (PFC_BASE + 0x0108U)
|
||||
#define PFC_GPSR3 (PFC_BASE + 0x010CU)
|
||||
#define PFC_GPSR4 (PFC_BASE + 0x0110U)
|
||||
#define PFC_GPSR5 (PFC_BASE + 0x0114U)
|
||||
#define PFC_GPSR6 (PFC_BASE + 0x0118U)
|
||||
#define PFC_IPSR0 (PFC_BASE + 0x0200U)
|
||||
#define PFC_IPSR1 (PFC_BASE + 0x0204U)
|
||||
#define PFC_IPSR2 (PFC_BASE + 0x0208U)
|
||||
#define PFC_IPSR3 (PFC_BASE + 0x020CU)
|
||||
#define PFC_IPSR4 (PFC_BASE + 0x0210U)
|
||||
#define PFC_IPSR5 (PFC_BASE + 0x0214U)
|
||||
#define PFC_IPSR6 (PFC_BASE + 0x0218U)
|
||||
#define PFC_IPSR7 (PFC_BASE + 0x021CU)
|
||||
#define PFC_IPSR8 (PFC_BASE + 0x0220U)
|
||||
#define PFC_IPSR9 (PFC_BASE + 0x0224U)
|
||||
#define PFC_IPSR10 (PFC_BASE + 0x0228U)
|
||||
#define PFC_IPSR11 (PFC_BASE + 0x022CU)
|
||||
#define PFC_IPSR12 (PFC_BASE + 0x0230U)
|
||||
#define PFC_IPSR13 (PFC_BASE + 0x0234U)
|
||||
#define PFC_IPSR14 (PFC_BASE + 0x0238U)
|
||||
#define PFC_IPSR15 (PFC_BASE + 0x023CU)
|
||||
#define PFC_IOCTRL30 (PFC_BASE + 0x0380U)
|
||||
#define PFC_IOCTRL32 (PFC_BASE + 0x0388U)
|
||||
#define PFC_IOCTRL40 (PFC_BASE + 0x03C0U)
|
||||
#define PFC_PUEN0 (PFC_BASE + 0x0400U)
|
||||
#define PFC_PUEN1 (PFC_BASE + 0x0404U)
|
||||
#define PFC_PUEN2 (PFC_BASE + 0x0408U)
|
||||
#define PFC_PUEN3 (PFC_BASE + 0x040CU)
|
||||
#define PFC_PUEN4 (PFC_BASE + 0x0410U)
|
||||
#define PFC_PUEN5 (PFC_BASE + 0x0414U)
|
||||
#define PFC_PUD0 (PFC_BASE + 0x0440U)
|
||||
#define PFC_PUD1 (PFC_BASE + 0x0444U)
|
||||
#define PFC_PUD2 (PFC_BASE + 0x0448U)
|
||||
#define PFC_PUD3 (PFC_BASE + 0x044CU)
|
||||
#define PFC_PUD4 (PFC_BASE + 0x0450U)
|
||||
#define PFC_PUD5 (PFC_BASE + 0x0454U)
|
||||
#define PFC_MOD_SEL0 (PFC_BASE + 0x0500U)
|
||||
#define PFC_MOD_SEL1 (PFC_BASE + 0x0504U)
|
||||
|
||||
#define GPSR0_SDA4 ((uint32_t)1U << 17U)
|
||||
#define GPSR0_SCL4 ((uint32_t)1U << 16U)
|
||||
#define GPSR0_D15 ((uint32_t)1U << 15U)
|
||||
#define GPSR0_D14 ((uint32_t)1U << 14U)
|
||||
#define GPSR0_D13 ((uint32_t)1U << 13U)
|
||||
#define GPSR0_D12 ((uint32_t)1U << 12U)
|
||||
#define GPSR0_D11 ((uint32_t)1U << 11U)
|
||||
#define GPSR0_D10 ((uint32_t)1U << 10U)
|
||||
#define GPSR0_D9 ((uint32_t)1U << 9U)
|
||||
#define GPSR0_D8 ((uint32_t)1U << 8U)
|
||||
#define GPSR0_D7 ((uint32_t)1U << 7U)
|
||||
#define GPSR0_D6 ((uint32_t)1U << 6U)
|
||||
#define GPSR0_D5 ((uint32_t)1U << 5U)
|
||||
#define GPSR0_D4 ((uint32_t)1U << 4U)
|
||||
#define GPSR0_D3 ((uint32_t)1U << 3U)
|
||||
#define GPSR0_D2 ((uint32_t)1U << 2U)
|
||||
#define GPSR0_D1 ((uint32_t)1U << 1U)
|
||||
#define GPSR0_D0 ((uint32_t)1U << 0U)
|
||||
#define GPSR1_WE0 ((uint32_t)1U << 22U)
|
||||
#define GPSR1_CS0 ((uint32_t)1U << 21U)
|
||||
#define GPSR1_CLKOUT ((uint32_t)1U << 20U)
|
||||
#define GPSR1_A19 ((uint32_t)1U << 19U)
|
||||
#define GPSR1_A18 ((uint32_t)1U << 18U)
|
||||
#define GPSR1_A17 ((uint32_t)1U << 17U)
|
||||
#define GPSR1_A16 ((uint32_t)1U << 16U)
|
||||
#define GPSR1_A15 ((uint32_t)1U << 15U)
|
||||
#define GPSR1_A14 ((uint32_t)1U << 14U)
|
||||
#define GPSR1_A13 ((uint32_t)1U << 13U)
|
||||
#define GPSR1_A12 ((uint32_t)1U << 12U)
|
||||
#define GPSR1_A11 ((uint32_t)1U << 11U)
|
||||
#define GPSR1_A10 ((uint32_t)1U << 10U)
|
||||
#define GPSR1_A9 ((uint32_t)1U << 9U)
|
||||
#define GPSR1_A8 ((uint32_t)1U << 8U)
|
||||
#define GPSR1_A7 ((uint32_t)1U << 7U)
|
||||
#define GPSR1_A6 ((uint32_t)1U << 6U)
|
||||
#define GPSR1_A5 ((uint32_t)1U << 5U)
|
||||
#define GPSR1_A4 ((uint32_t)1U << 4U)
|
||||
#define GPSR1_A3 ((uint32_t)1U << 3U)
|
||||
#define GPSR1_A2 ((uint32_t)1U << 2U)
|
||||
#define GPSR1_A1 ((uint32_t)1U << 1U)
|
||||
#define GPSR1_A0 ((uint32_t)1U << 0U)
|
||||
#define GPSR2_BIT27_REVERCED ((uint32_t)1U << 27U)
|
||||
#define GPSR2_BIT26_REVERCED ((uint32_t)1U << 26U)
|
||||
#define GPSR2_EX_WAIT0 ((uint32_t)1U << 25U)
|
||||
#define GPSR2_RD_WR ((uint32_t)1U << 24U)
|
||||
#define GPSR2_RD ((uint32_t)1U << 23U)
|
||||
#define GPSR2_BS ((uint32_t)1U << 22U)
|
||||
#define GPSR2_AVB_PHY_INT ((uint32_t)1U << 21U)
|
||||
#define GPSR2_AVB_TXCREFCLK ((uint32_t)1U << 20U)
|
||||
#define GPSR2_AVB_RD3 ((uint32_t)1U << 19U)
|
||||
#define GPSR2_AVB_RD2 ((uint32_t)1U << 18U)
|
||||
#define GPSR2_AVB_RD1 ((uint32_t)1U << 17U)
|
||||
#define GPSR2_AVB_RD0 ((uint32_t)1U << 16U)
|
||||
#define GPSR2_AVB_RXC ((uint32_t)1U << 15U)
|
||||
#define GPSR2_AVB_RX_CTL ((uint32_t)1U << 14U)
|
||||
#define GPSR2_RPC_RESET ((uint32_t)1U << 13U)
|
||||
#define GPSR2_RPC_RPC_INT ((uint32_t)1U << 12U)
|
||||
#define GPSR2_QSPI1_SSL ((uint32_t)1U << 11U)
|
||||
#define GPSR2_QSPI1_IO3 ((uint32_t)1U << 10U)
|
||||
#define GPSR2_QSPI1_IO2 ((uint32_t)1U << 9U)
|
||||
#define GPSR2_QSPI1_MISO_IO1 ((uint32_t)1U << 8U)
|
||||
#define GPSR2_QSPI1_MOSI_IO0 ((uint32_t)1U << 7U)
|
||||
#define GPSR2_QSPI1_SPCLK ((uint32_t)1U << 6U)
|
||||
#define GPSR2_QSPI0_SSL ((uint32_t)1U << 5U)
|
||||
#define GPSR2_QSPI0_IO3 ((uint32_t)1U << 4U)
|
||||
#define GPSR2_QSPI0_IO2 ((uint32_t)1U << 3U)
|
||||
#define GPSR2_QSPI0_MISO_IO1 ((uint32_t)1U << 2U)
|
||||
#define GPSR2_QSPI0_MOSI_IO0 ((uint32_t)1U << 1U)
|
||||
#define GPSR2_QSPI0_SPCLK ((uint32_t)1U << 0U)
|
||||
#define GPSR3_SD1_WP ((uint32_t)1U << 15U)
|
||||
#define GPSR3_SD1_CD ((uint32_t)1U << 14U)
|
||||
#define GPSR3_SD0_WP ((uint32_t)1U << 13U)
|
||||
#define GPSR3_SD0_CD ((uint32_t)1U << 12U)
|
||||
#define GPSR3_SD1_DAT3 ((uint32_t)1U << 11U)
|
||||
#define GPSR3_SD1_DAT2 ((uint32_t)1U << 10U)
|
||||
#define GPSR3_SD1_DAT1 ((uint32_t)1U << 9U)
|
||||
#define GPSR3_SD1_DAT0 ((uint32_t)1U << 8U)
|
||||
#define GPSR3_SD1_CMD ((uint32_t)1U << 7U)
|
||||
#define GPSR3_SD1_CLK ((uint32_t)1U << 6U)
|
||||
#define GPSR3_SD0_DAT3 ((uint32_t)1U << 5U)
|
||||
#define GPSR3_SD0_DAT2 ((uint32_t)1U << 4U)
|
||||
#define GPSR3_SD0_DAT1 ((uint32_t)1U << 3U)
|
||||
#define GPSR3_SD0_DAT0 ((uint32_t)1U << 2U)
|
||||
#define GPSR3_SD0_CMD ((uint32_t)1U << 1U)
|
||||
#define GPSR3_SD0_CLK ((uint32_t)1U << 0U)
|
||||
#define GPSR4_SD3_DS ((uint32_t)1U << 10U)
|
||||
#define GPSR4_SD3_DAT7 ((uint32_t)1U << 9U)
|
||||
#define GPSR4_SD3_DAT6 ((uint32_t)1U << 8U)
|
||||
#define GPSR4_SD3_DAT5 ((uint32_t)1U << 7U)
|
||||
#define GPSR4_SD3_DAT4 ((uint32_t)1U << 6U)
|
||||
#define GPSR4_SD3_DAT3 ((uint32_t)1U << 5U)
|
||||
#define GPSR4_SD3_DAT2 ((uint32_t)1U << 4U)
|
||||
#define GPSR4_SD3_DAT1 ((uint32_t)1U << 3U)
|
||||
#define GPSR4_SD3_DAT0 ((uint32_t)1U << 2U)
|
||||
#define GPSR4_SD3_CMD ((uint32_t)1U << 1U)
|
||||
#define GPSR4_SD3_CLK ((uint32_t)1U << 0U)
|
||||
#define GPSR5_MLB_DAT ((uint32_t)1U << 19U)
|
||||
#define GPSR5_MLB_SIG ((uint32_t)1U << 18U)
|
||||
#define GPSR5_MLB_CLK ((uint32_t)1U << 17U)
|
||||
#define GPSR5_SSI_SDATA9 ((uint32_t)1U << 16U)
|
||||
#define GPSR5_MSIOF0_SS2 ((uint32_t)1U << 15U)
|
||||
#define GPSR5_MSIOF0_SS1 ((uint32_t)1U << 14U)
|
||||
#define GPSR5_MSIOF0_SYNC ((uint32_t)1U << 13U)
|
||||
#define GPSR5_MSIOF0_TXD ((uint32_t)1U << 12U)
|
||||
#define GPSR5_MSIOF0_RXD ((uint32_t)1U << 11U)
|
||||
#define GPSR5_MSIOF0_SCK ((uint32_t)1U << 10U)
|
||||
#define GPSR5_RX2_A ((uint32_t)1U << 9U)
|
||||
#define GPSR5_TX2_A ((uint32_t)1U << 8U)
|
||||
#define GPSR5_SCK2_A ((uint32_t)1U << 7U)
|
||||
#define GPSR5_TX1 ((uint32_t)1U << 6U)
|
||||
#define GPSR5_RX1 ((uint32_t)1U << 5U)
|
||||
#define GPSR5_RTS0_TANS_A ((uint32_t)1U << 4U)
|
||||
#define GPSR5_CTS0_A ((uint32_t)1U << 3U)
|
||||
#define GPSR5_TX0_A ((uint32_t)1U << 2U)
|
||||
#define GPSR5_RX0_A ((uint32_t)1U << 1U)
|
||||
#define GPSR5_SCK0_A ((uint32_t)1U << 0U)
|
||||
#define GPSR6_USB30_PWEN ((uint32_t)1U << 17U)
|
||||
#define GPSR6_SSI_SDATA6 ((uint32_t)1U << 16U)
|
||||
#define GPSR6_SSI_WS6 ((uint32_t)1U << 15U)
|
||||
#define GPSR6_SSI_SCK6 ((uint32_t)1U << 14U)
|
||||
#define GPSR6_SSI_SDATA5 ((uint32_t)1U << 13U)
|
||||
#define GPSR6_SSI_WS5 ((uint32_t)1U << 12U)
|
||||
#define GPSR6_SSI_SCK5 ((uint32_t)1U << 11U)
|
||||
#define GPSR6_SSI_SDATA4 ((uint32_t)1U << 10U)
|
||||
#define GPSR6_USB30_OVC ((uint32_t)1U << 9U)
|
||||
#define GPSR6_AUDIO_CLKA ((uint32_t)1U << 8U)
|
||||
#define GPSR6_SSI_SDATA3 ((uint32_t)1U << 7U)
|
||||
#define GPSR6_SSI_WS349 ((uint32_t)1U << 6U)
|
||||
#define GPSR6_SSI_SCK349 ((uint32_t)1U << 5U)
|
||||
#define GPSR6_SSI_SDATA2 ((uint32_t)1U << 4U)
|
||||
#define GPSR6_SSI_SDATA1 ((uint32_t)1U << 3U)
|
||||
#define GPSR6_SSI_SDATA0 ((uint32_t)1U << 2U)
|
||||
#define GPSR6_SSI_WS01239 ((uint32_t)1U << 1U)
|
||||
#define GPSR6_SSI_SCK01239 ((uint32_t)1U << 0U)
|
||||
|
||||
#define IPSR_28_FUNC(x) ((uint32_t)(x) << 28U)
|
||||
#define IPSR_24_FUNC(x) ((uint32_t)(x) << 24U)
|
||||
#define IPSR_20_FUNC(x) ((uint32_t)(x) << 20U)
|
||||
#define IPSR_16_FUNC(x) ((uint32_t)(x) << 16U)
|
||||
#define IPSR_12_FUNC(x) ((uint32_t)(x) << 12U)
|
||||
#define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U)
|
||||
#define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U)
|
||||
#define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U)
|
||||
|
||||
#define IOCTRL30_MASK (0x0007F000U)
|
||||
#define POC_SD3_DS_33V ((uint32_t)1U << 29U)
|
||||
#define POC_SD3_DAT7_33V ((uint32_t)1U << 28U)
|
||||
#define POC_SD3_DAT6_33V ((uint32_t)1U << 27U)
|
||||
#define POC_SD3_DAT5_33V ((uint32_t)1U << 26U)
|
||||
#define POC_SD3_DAT4_33V ((uint32_t)1U << 25U)
|
||||
#define POC_SD3_DAT3_33V ((uint32_t)1U << 24U)
|
||||
#define POC_SD3_DAT2_33V ((uint32_t)1U << 23U)
|
||||
#define POC_SD3_DAT1_33V ((uint32_t)1U << 22U)
|
||||
#define POC_SD3_DAT0_33V ((uint32_t)1U << 21U)
|
||||
#define POC_SD3_CMD_33V ((uint32_t)1U << 20U)
|
||||
#define POC_SD3_CLK_33V ((uint32_t)1U << 19U)
|
||||
#define POC_SD1_DAT3_33V ((uint32_t)1U << 11U)
|
||||
#define POC_SD1_DAT2_33V ((uint32_t)1U << 10U)
|
||||
#define POC_SD1_DAT1_33V ((uint32_t)1U << 9U)
|
||||
#define POC_SD1_DAT0_33V ((uint32_t)1U << 8U)
|
||||
#define POC_SD1_CMD_33V ((uint32_t)1U << 7U)
|
||||
#define POC_SD1_CLK_33V ((uint32_t)1U << 6U)
|
||||
#define POC_SD0_DAT3_33V ((uint32_t)1U << 5U)
|
||||
#define POC_SD0_DAT2_33V ((uint32_t)1U << 4U)
|
||||
#define POC_SD0_DAT1_33V ((uint32_t)1U << 3U)
|
||||
#define POC_SD0_DAT0_33V ((uint32_t)1U << 2U)
|
||||
#define POC_SD0_CMD_33V ((uint32_t)1U << 1U)
|
||||
#define POC_SD0_CLK_33V ((uint32_t)1U << 0U)
|
||||
|
||||
#define IOCTRL32_MASK (0xFFFFFFFEU)
|
||||
#define POC2_VREF_33V ((uint32_t)1U << 0U)
|
||||
|
||||
#define MOD_SEL0_ADGB_A ((uint32_t)0U << 29U)
|
||||
#define MOD_SEL0_ADGB_B ((uint32_t)1U << 29U)
|
||||
#define MOD_SEL0_ADGB_C ((uint32_t)2U << 29U)
|
||||
#define MOD_SEL0_DRIF0_A ((uint32_t)0U << 28U)
|
||||
#define MOD_SEL0_DRIF0_B ((uint32_t)1U << 28U)
|
||||
#define MOD_SEL0_FM_A ((uint32_t)0U << 26U)
|
||||
#define MOD_SEL0_FM_B ((uint32_t)1U << 26U)
|
||||
#define MOD_SEL0_FM_C ((uint32_t)2U << 26U)
|
||||
#define MOD_SEL0_FSO_A ((uint32_t)0U << 25U)
|
||||
#define MOD_SEL0_FSO_B ((uint32_t)1U << 25U)
|
||||
#define MOD_SEL0_HSCIF0_A ((uint32_t)0U << 24U)
|
||||
#define MOD_SEL0_HSCIF0_B ((uint32_t)1U << 24U)
|
||||
#define MOD_SEL0_HSCIF1_A ((uint32_t)0U << 23U)
|
||||
#define MOD_SEL0_HSCIF1_B ((uint32_t)1U << 23U)
|
||||
#define MOD_SEL0_HSCIF2_A ((uint32_t)0U << 22U)
|
||||
#define MOD_SEL0_HSCIF2_B ((uint32_t)1U << 22U)
|
||||
#define MOD_SEL0_I2C1_A ((uint32_t)0U << 20U)
|
||||
#define MOD_SEL0_I2C1_B ((uint32_t)1U << 20U)
|
||||
#define MOD_SEL0_I2C1_C ((uint32_t)2U << 20U)
|
||||
#define MOD_SEL0_I2C1_D ((uint32_t)3U << 20U)
|
||||
#define MOD_SEL0_I2C2_A ((uint32_t)0U << 17U)
|
||||
#define MOD_SEL0_I2C2_B ((uint32_t)1U << 17U)
|
||||
#define MOD_SEL0_I2C2_C ((uint32_t)2U << 17U)
|
||||
#define MOD_SEL0_I2C2_D ((uint32_t)3U << 17U)
|
||||
#define MOD_SEL0_I2C2_E ((uint32_t)4U << 17U)
|
||||
#define MOD_SEL0_NDFC_A ((uint32_t)0U << 16U)
|
||||
#define MOD_SEL0_NDFC_B ((uint32_t)1U << 16U)
|
||||
#define MOD_SEL0_PWM0_A ((uint32_t)0U << 15U)
|
||||
#define MOD_SEL0_PWM0_B ((uint32_t)1U << 15U)
|
||||
#define MOD_SEL0_PWM1_A ((uint32_t)0U << 14U)
|
||||
#define MOD_SEL0_PWM1_B ((uint32_t)1U << 14U)
|
||||
#define MOD_SEL0_PWM2_A ((uint32_t)0U << 12U)
|
||||
#define MOD_SEL0_PWM2_B ((uint32_t)1U << 12U)
|
||||
#define MOD_SEL0_PWM2_C ((uint32_t)2U << 12U)
|
||||
#define MOD_SEL0_PWM3_A ((uint32_t)0U << 10U)
|
||||
#define MOD_SEL0_PWM3_B ((uint32_t)1U << 10U)
|
||||
#define MOD_SEL0_PWM3_C ((uint32_t)2U << 10U)
|
||||
#define MOD_SEL0_PWM4_A ((uint32_t)0U << 9U)
|
||||
#define MOD_SEL0_PWM4_B ((uint32_t)1U << 9U)
|
||||
#define MOD_SEL0_PWM5_A ((uint32_t)0U << 8U)
|
||||
#define MOD_SEL0_PWM5_B ((uint32_t)1U << 8U)
|
||||
#define MOD_SEL0_PWM6_A ((uint32_t)0U << 7U)
|
||||
#define MOD_SEL0_PWM6_B ((uint32_t)1U << 7U)
|
||||
#define MOD_SEL0_REMOCON_A ((uint32_t)0U << 5U)
|
||||
#define MOD_SEL0_REMOCON_B ((uint32_t)1U << 5U)
|
||||
#define MOD_SEL0_REMOCON_C ((uint32_t)2U << 5U)
|
||||
#define MOD_SEL0_SCIF_A ((uint32_t)0U << 4U)
|
||||
#define MOD_SEL0_SCIF_B ((uint32_t)1U << 4U)
|
||||
#define MOD_SEL0_SCIF0_A ((uint32_t)0U << 3U)
|
||||
#define MOD_SEL0_SCIF0_B ((uint32_t)1U << 3U)
|
||||
#define MOD_SEL0_SCIF2_A ((uint32_t)0U << 2U)
|
||||
#define MOD_SEL0_SCIF2_B ((uint32_t)1U << 2U)
|
||||
#define MOD_SEL0_SPEED_PULSE_IF_A ((uint32_t)0U << 0U)
|
||||
#define MOD_SEL0_SPEED_PULSE_IF_B ((uint32_t)1U << 0U)
|
||||
#define MOD_SEL0_SPEED_PULSE_IF_C ((uint32_t)2U << 0U)
|
||||
#define MOD_SEL1_SIMCARD_A ((uint32_t)0U << 31U)
|
||||
#define MOD_SEL1_SIMCARD_B ((uint32_t)1U << 31U)
|
||||
#define MOD_SEL1_SSI2_A ((uint32_t)0U << 30U)
|
||||
#define MOD_SEL1_SSI2_B ((uint32_t)1U << 30U)
|
||||
#define MOD_SEL1_TIMER_TMU_A ((uint32_t)0U << 29U)
|
||||
#define MOD_SEL1_TIMER_TMU_B ((uint32_t)1U << 29U)
|
||||
#define MOD_SEL1_USB20_CH0_A ((uint32_t)0U << 28U)
|
||||
#define MOD_SEL1_USB20_CH0_B ((uint32_t)1U << 28U)
|
||||
#define MOD_SEL1_DRIF2_A ((uint32_t)0U << 26U)
|
||||
#define MOD_SEL1_DRIF2_B ((uint32_t)1U << 26U)
|
||||
#define MOD_SEL1_DRIF3_A ((uint32_t)0U << 25U)
|
||||
#define MOD_SEL1_DRIF3_B ((uint32_t)1U << 25U)
|
||||
#define MOD_SEL1_HSCIF3_A ((uint32_t)0U << 22U)
|
||||
#define MOD_SEL1_HSCIF3_B ((uint32_t)1U << 22U)
|
||||
#define MOD_SEL1_HSCIF3_C ((uint32_t)2U << 22U)
|
||||
#define MOD_SEL1_HSCIF3_D ((uint32_t)3U << 22U)
|
||||
#define MOD_SEL1_HSCIF3_E ((uint32_t)4U << 22U)
|
||||
#define MOD_SEL1_HSCIF4_A ((uint32_t)0U << 19U)
|
||||
#define MOD_SEL1_HSCIF4_B ((uint32_t)1U << 19U)
|
||||
#define MOD_SEL1_HSCIF4_C ((uint32_t)2U << 19U)
|
||||
#define MOD_SEL1_HSCIF4_D ((uint32_t)3U << 19U)
|
||||
#define MOD_SEL1_HSCIF4_E ((uint32_t)4U << 19U)
|
||||
#define MOD_SEL1_I2C6_A ((uint32_t)0U << 18U)
|
||||
#define MOD_SEL1_I2C6_B ((uint32_t)1U << 18U)
|
||||
#define MOD_SEL1_I2C7_A ((uint32_t)0U << 17U)
|
||||
#define MOD_SEL1_I2C7_B ((uint32_t)1U << 17U)
|
||||
#define MOD_SEL1_MSIOF2_A ((uint32_t)0U << 16U)
|
||||
#define MOD_SEL1_MSIOF2_B ((uint32_t)1U << 16U)
|
||||
#define MOD_SEL1_MSIOF3_A ((uint32_t)0U << 15U)
|
||||
#define MOD_SEL1_MSIOF3_B ((uint32_t)1U << 15U)
|
||||
#define MOD_SEL1_SCIF3_A ((uint32_t)0U << 13U)
|
||||
#define MOD_SEL1_SCIF3_B ((uint32_t)1U << 13U)
|
||||
#define MOD_SEL1_SCIF3_C ((uint32_t)2U << 13U)
|
||||
#define MOD_SEL1_SCIF4_A ((uint32_t)0U << 11U)
|
||||
#define MOD_SEL1_SCIF4_B ((uint32_t)1U << 11U)
|
||||
#define MOD_SEL1_SCIF4_C ((uint32_t)2U << 11U)
|
||||
#define MOD_SEL1_SCIF5_A ((uint32_t)0U << 9U)
|
||||
#define MOD_SEL1_SCIF5_B ((uint32_t)1U << 9U)
|
||||
#define MOD_SEL1_SCIF5_C ((uint32_t)2U << 9U)
|
||||
#define MOD_SEL1_VIN4_A ((uint32_t)0U << 8U)
|
||||
#define MOD_SEL1_VIN4_B ((uint32_t)1U << 8U)
|
||||
#define MOD_SEL1_VIN5_A ((uint32_t)0U << 7U)
|
||||
#define MOD_SEL1_VIN5_B ((uint32_t)1U << 7U)
|
||||
#define MOD_SEL1_ADGC_A ((uint32_t)0U << 5U)
|
||||
#define MOD_SEL1_ADGC_B ((uint32_t)1U << 5U)
|
||||
#define MOD_SEL1_ADGC_C ((uint32_t)2U << 5U)
|
||||
#define MOD_SEL1_SSI9_A ((uint32_t)0U << 4U)
|
||||
#define MOD_SEL1_SSI9_B ((uint32_t)1U << 4U)
|
||||
|
||||
static void pfc_reg_write(uint32_t addr, uint32_t data);
|
||||
|
||||
static void pfc_reg_write(uint32_t addr, uint32_t data)
|
||||
{
|
||||
mmio_write_32(PFC_PMMR, ~data);
|
||||
mmio_write_32((uintptr_t) addr, data);
|
||||
}
|
||||
|
||||
void pfc_init_e3(void)
|
||||
{
|
||||
uint32_t reg;
|
||||
|
||||
/* initialize module select */
|
||||
pfc_reg_write(PFC_MOD_SEL0, MOD_SEL0_ADGB_A
|
||||
| MOD_SEL0_DRIF0_A
|
||||
| MOD_SEL0_FM_A
|
||||
| MOD_SEL0_FSO_A
|
||||
| MOD_SEL0_HSCIF0_A
|
||||
| MOD_SEL0_HSCIF1_A
|
||||
| MOD_SEL0_HSCIF2_A
|
||||
| MOD_SEL0_I2C1_A
|
||||
| MOD_SEL0_I2C2_A
|
||||
| MOD_SEL0_NDFC_A
|
||||
| MOD_SEL0_PWM0_A
|
||||
| MOD_SEL0_PWM1_A
|
||||
| MOD_SEL0_PWM2_A
|
||||
| MOD_SEL0_PWM3_A
|
||||
| MOD_SEL0_PWM4_A
|
||||
| MOD_SEL0_PWM5_A
|
||||
| MOD_SEL0_PWM6_A
|
||||
| MOD_SEL0_REMOCON_A
|
||||
| MOD_SEL0_SCIF_A
|
||||
| MOD_SEL0_SCIF0_A
|
||||
| MOD_SEL0_SCIF2_A | MOD_SEL0_SPEED_PULSE_IF_A);
|
||||
pfc_reg_write(PFC_MOD_SEL1, MOD_SEL1_SIMCARD_A
|
||||
| MOD_SEL1_SSI2_A
|
||||
| MOD_SEL1_TIMER_TMU_A
|
||||
| MOD_SEL1_USB20_CH0_B
|
||||
| MOD_SEL1_DRIF2_A
|
||||
| MOD_SEL1_DRIF3_A
|
||||
| MOD_SEL1_HSCIF3_A
|
||||
| MOD_SEL1_HSCIF4_A
|
||||
| MOD_SEL1_I2C6_A
|
||||
| MOD_SEL1_I2C7_A
|
||||
| MOD_SEL1_MSIOF2_A
|
||||
| MOD_SEL1_MSIOF3_A
|
||||
| MOD_SEL1_SCIF3_A
|
||||
| MOD_SEL1_SCIF4_A
|
||||
| MOD_SEL1_SCIF5_A
|
||||
| MOD_SEL1_VIN4_A
|
||||
| MOD_SEL1_VIN5_A | MOD_SEL1_ADGC_A | MOD_SEL1_SSI9_A);
|
||||
|
||||
/* initialize peripheral function select */
|
||||
pfc_reg_write(PFC_IPSR0, IPSR_28_FUNC(0) /* QSPI1_MISO/IO1 */
|
||||
|IPSR_24_FUNC(0) /* QSPI1_MOSI/IO0 */
|
||||
|IPSR_20_FUNC(0) /* QSPI1_SPCLK */
|
||||
|IPSR_16_FUNC(0) /* QSPI0_IO3 */
|
||||
|IPSR_12_FUNC(0) /* QSPI0_IO2 */
|
||||
|IPSR_8_FUNC(0) /* QSPI0_MISO/IO1 */
|
||||
|IPSR_4_FUNC(0) /* QSPI0_MOSI/IO0 */
|
||||
|IPSR_0_FUNC(0)); /* QSPI0_SPCLK */
|
||||
pfc_reg_write(PFC_IPSR1, IPSR_28_FUNC(0) /* AVB_RD2 */
|
||||
|IPSR_24_FUNC(0) /* AVB_RD1 */
|
||||
|IPSR_20_FUNC(0) /* AVB_RD0 */
|
||||
|IPSR_16_FUNC(0) /* RPC_RESET# */
|
||||
|IPSR_12_FUNC(0) /* RPC_INT# */
|
||||
|IPSR_8_FUNC(0) /* QSPI1_SSL */
|
||||
|IPSR_4_FUNC(0) /* QSPI1_IO3 */
|
||||
|IPSR_0_FUNC(0)); /* QSPI1_IO2 */
|
||||
pfc_reg_write(PFC_IPSR2, IPSR_28_FUNC(1) /* IRQ0 */
|
||||
|IPSR_24_FUNC(0)
|
||||
| IPSR_20_FUNC(0)
|
||||
| IPSR_16_FUNC(2) /* AVB_LINK */
|
||||
|IPSR_12_FUNC(0)
|
||||
| IPSR_8_FUNC(0) /* AVB_MDC */
|
||||
|IPSR_4_FUNC(0) /* AVB_MDIO */
|
||||
|IPSR_0_FUNC(0)); /* AVB_TXCREFCLK */
|
||||
pfc_reg_write(PFC_IPSR3, IPSR_28_FUNC(5) /* DU_HSYNC */
|
||||
|IPSR_24_FUNC(0)
|
||||
| IPSR_20_FUNC(0)
|
||||
| IPSR_16_FUNC(0)
|
||||
| IPSR_12_FUNC(5) /* DU_DG4 */
|
||||
|IPSR_8_FUNC(5) /* DU_DOTCLKOUT0 */
|
||||
|IPSR_4_FUNC(5) /* DU_DISP */
|
||||
|IPSR_0_FUNC(1)); /* IRQ1 */
|
||||
pfc_reg_write(PFC_IPSR4, IPSR_28_FUNC(5) /* DU_DB5 */
|
||||
|IPSR_24_FUNC(5) /* DU_DB4 */
|
||||
|IPSR_20_FUNC(5) /* DU_DB3 */
|
||||
|IPSR_16_FUNC(5) /* DU_DB2 */
|
||||
|IPSR_12_FUNC(5) /* DU_DG6 */
|
||||
|IPSR_8_FUNC(5) /* DU_VSYNC */
|
||||
|IPSR_4_FUNC(5) /* DU_DG5 */
|
||||
|IPSR_0_FUNC(5)); /* DU_DG7 */
|
||||
pfc_reg_write(PFC_IPSR5, IPSR_28_FUNC(5) /* DU_DR3 */
|
||||
|IPSR_24_FUNC(5) /* DU_DB7 */
|
||||
|IPSR_20_FUNC(5) /* DU_DR2 */
|
||||
|IPSR_16_FUNC(5) /* DU_DR1 */
|
||||
|IPSR_12_FUNC(5) /* DU_DR0 */
|
||||
|IPSR_8_FUNC(5) /* DU_DB1 */
|
||||
|IPSR_4_FUNC(5) /* DU_DB0 */
|
||||
|IPSR_0_FUNC(5)); /* DU_DB6 */
|
||||
pfc_reg_write(PFC_IPSR6, IPSR_28_FUNC(5) /* DU_DG1 */
|
||||
|IPSR_24_FUNC(5) /* DU_DG0 */
|
||||
|IPSR_20_FUNC(5) /* DU_DR7 */
|
||||
|IPSR_16_FUNC(2) /* IRQ5 */
|
||||
|IPSR_12_FUNC(5) /* DU_DR6 */
|
||||
|IPSR_8_FUNC(5) /* DU_DR5 */
|
||||
|IPSR_4_FUNC(0)
|
||||
| IPSR_0_FUNC(5)); /* DU_DR4 */
|
||||
pfc_reg_write(PFC_IPSR7, IPSR_28_FUNC(0) /* SD0_CLK */
|
||||
|IPSR_24_FUNC(0)
|
||||
| IPSR_20_FUNC(5) /* DU_DOTCLKIN0 */
|
||||
|IPSR_16_FUNC(5) /* DU_DG3 */
|
||||
|IPSR_12_FUNC(0)
|
||||
| IPSR_8_FUNC(0)
|
||||
| IPSR_4_FUNC(0)
|
||||
| IPSR_0_FUNC(5)); /* DU_DG2 */
|
||||
pfc_reg_write(PFC_IPSR8, IPSR_28_FUNC(0) /* SD1_DAT0 */
|
||||
|IPSR_24_FUNC(0) /* SD1_CMD */
|
||||
|IPSR_20_FUNC(0) /* SD1_CLK */
|
||||
|IPSR_16_FUNC(0) /* SD0_DAT3 */
|
||||
|IPSR_12_FUNC(0) /* SD0_DAT2 */
|
||||
|IPSR_8_FUNC(0) /* SD0_DAT1 */
|
||||
|IPSR_4_FUNC(0) /* SD0_DAT0 */
|
||||
|IPSR_0_FUNC(0)); /* SD0_CMD */
|
||||
pfc_reg_write(PFC_IPSR9, IPSR_28_FUNC(0) /* SD3_DAT2 */
|
||||
|IPSR_24_FUNC(0) /* SD3_DAT1 */
|
||||
|IPSR_20_FUNC(0) /* SD3_DAT0 */
|
||||
|IPSR_16_FUNC(0) /* SD3_CMD */
|
||||
|IPSR_12_FUNC(0) /* SD3_CLK */
|
||||
|IPSR_8_FUNC(0) /* SD1_DAT3 */
|
||||
|IPSR_4_FUNC(0) /* SD1_DAT2 */
|
||||
|IPSR_0_FUNC(0)); /* SD1_DAT1 */
|
||||
pfc_reg_write(PFC_IPSR10, IPSR_28_FUNC(0) /* SD0_WP */
|
||||
|IPSR_24_FUNC(0) /* SD0_CD */
|
||||
|IPSR_20_FUNC(0) /* SD3_DS */
|
||||
|IPSR_16_FUNC(0) /* SD3_DAT7 */
|
||||
|IPSR_12_FUNC(0) /* SD3_DAT6 */
|
||||
|IPSR_8_FUNC(0) /* SD3_DAT5 */
|
||||
|IPSR_4_FUNC(0) /* SD3_DAT4 */
|
||||
|IPSR_0_FUNC(0)); /* SD3_DAT3 */
|
||||
pfc_reg_write(PFC_IPSR11, IPSR_28_FUNC(0)
|
||||
| IPSR_24_FUNC(0)
|
||||
| IPSR_20_FUNC(2) /* AUDIO_CLKOUT1_A */
|
||||
|IPSR_16_FUNC(2) /* AUDIO_CLKOUT_A */
|
||||
|IPSR_12_FUNC(0)
|
||||
| IPSR_8_FUNC(0)
|
||||
| IPSR_4_FUNC(0) /* SD1_WP */
|
||||
|IPSR_0_FUNC(0)); /* SD1_CD */
|
||||
pfc_reg_write(PFC_IPSR12, IPSR_28_FUNC(0)
|
||||
| IPSR_24_FUNC(0)
|
||||
| IPSR_20_FUNC(0)
|
||||
| IPSR_16_FUNC(0)
|
||||
| IPSR_12_FUNC(0) /* RX2_A */
|
||||
|IPSR_8_FUNC(0) /* TX2_A */
|
||||
|IPSR_4_FUNC(2) /* AUDIO_CLKB_A */
|
||||
|IPSR_0_FUNC(0));
|
||||
pfc_reg_write(PFC_IPSR13, IPSR_28_FUNC(0)
|
||||
| IPSR_24_FUNC(0)
|
||||
| IPSR_20_FUNC(0)
|
||||
| IPSR_16_FUNC(0)
|
||||
| IPSR_12_FUNC(0)
|
||||
| IPSR_8_FUNC(2) /* AUDIO_CLKC_A */
|
||||
|IPSR_4_FUNC(1) /* HTX2_A */
|
||||
|IPSR_0_FUNC(1)); /* HRX2_A */
|
||||
pfc_reg_write(PFC_IPSR14, IPSR_28_FUNC(3) /* USB0_PWEN_B */
|
||||
|IPSR_24_FUNC(0) /* SSI_SDATA4 */
|
||||
|IPSR_20_FUNC(0) /* SSI_SDATA3 */
|
||||
|IPSR_16_FUNC(0) /* SSI_WS349 */
|
||||
|IPSR_12_FUNC(0) /* SSI_SCK349 */
|
||||
|IPSR_8_FUNC(0)
|
||||
| IPSR_4_FUNC(0) /* SSI_SDATA1 */
|
||||
|IPSR_0_FUNC(0)); /* SSI_SDATA0 */
|
||||
pfc_reg_write(PFC_IPSR15, IPSR_28_FUNC(0) /* USB30_OVC */
|
||||
|IPSR_24_FUNC(0) /* USB30_PWEN */
|
||||
|IPSR_20_FUNC(0) /* AUDIO_CLKA */
|
||||
|IPSR_16_FUNC(1) /* HRTS2#_A */
|
||||
|IPSR_12_FUNC(1) /* HCTS2#_A */
|
||||
|IPSR_8_FUNC(0)
|
||||
| IPSR_4_FUNC(0)
|
||||
| IPSR_0_FUNC(3)); /* USB0_OVC_B */
|
||||
|
||||
/* initialize GPIO/perihperal function select */
|
||||
pfc_reg_write(PFC_GPSR0, GPSR0_SCL4
|
||||
| GPSR0_D15
|
||||
| GPSR0_D11
|
||||
| GPSR0_D10
|
||||
| GPSR0_D9
|
||||
| GPSR0_D8
|
||||
| GPSR0_D7
|
||||
| GPSR0_D6
|
||||
| GPSR0_D5 | GPSR0_D3 | GPSR0_D2 | GPSR0_D1 | GPSR0_D0);
|
||||
pfc_reg_write(PFC_GPSR1, GPSR1_WE0
|
||||
| GPSR1_CS0
|
||||
| GPSR1_A19
|
||||
| GPSR1_A18
|
||||
| GPSR1_A17
|
||||
| GPSR1_A16
|
||||
| GPSR1_A15
|
||||
| GPSR1_A14
|
||||
| GPSR1_A13
|
||||
| GPSR1_A12
|
||||
| GPSR1_A11
|
||||
| GPSR1_A10
|
||||
| GPSR1_A9
|
||||
| GPSR1_A8
|
||||
| GPSR1_A4 | GPSR1_A3 | GPSR1_A2 | GPSR1_A1 | GPSR1_A0);
|
||||
pfc_reg_write(PFC_GPSR2, GPSR2_BIT27_REVERCED
|
||||
| GPSR2_BIT26_REVERCED
|
||||
| GPSR2_RD
|
||||
| GPSR2_AVB_PHY_INT
|
||||
| GPSR2_AVB_TXCREFCLK
|
||||
| GPSR2_AVB_RD3
|
||||
| GPSR2_AVB_RD2
|
||||
| GPSR2_AVB_RD1
|
||||
| GPSR2_AVB_RD0
|
||||
| GPSR2_AVB_RXC
|
||||
| GPSR2_AVB_RX_CTL
|
||||
| GPSR2_RPC_RESET
|
||||
| GPSR2_RPC_RPC_INT
|
||||
| GPSR2_QSPI1_SSL
|
||||
| GPSR2_QSPI1_IO3
|
||||
| GPSR2_QSPI1_IO2
|
||||
| GPSR2_QSPI1_MISO_IO1
|
||||
| GPSR2_QSPI1_MOSI_IO0
|
||||
| GPSR2_QSPI1_SPCLK
|
||||
| GPSR2_QSPI0_SSL
|
||||
| GPSR2_QSPI0_IO3
|
||||
| GPSR2_QSPI0_IO2
|
||||
| GPSR2_QSPI0_MISO_IO1
|
||||
| GPSR2_QSPI0_MOSI_IO0 | GPSR2_QSPI0_SPCLK);
|
||||
pfc_reg_write(PFC_GPSR3, GPSR3_SD1_WP
|
||||
| GPSR3_SD1_CD
|
||||
| GPSR3_SD0_WP
|
||||
| GPSR3_SD0_CD
|
||||
| GPSR3_SD1_DAT3
|
||||
| GPSR3_SD1_DAT2
|
||||
| GPSR3_SD1_DAT1
|
||||
| GPSR3_SD1_DAT0
|
||||
| GPSR3_SD1_CMD
|
||||
| GPSR3_SD1_CLK
|
||||
| GPSR3_SD0_DAT3
|
||||
| GPSR3_SD0_DAT2
|
||||
| GPSR3_SD0_DAT1
|
||||
| GPSR3_SD0_DAT0 | GPSR3_SD0_CMD | GPSR3_SD0_CLK);
|
||||
pfc_reg_write(PFC_GPSR4, GPSR4_SD3_DS
|
||||
| GPSR4_SD3_DAT7
|
||||
| GPSR4_SD3_DAT6
|
||||
| GPSR4_SD3_DAT5
|
||||
| GPSR4_SD3_DAT4
|
||||
| GPSR4_SD3_DAT3
|
||||
| GPSR4_SD3_DAT2
|
||||
| GPSR4_SD3_DAT1
|
||||
| GPSR4_SD3_DAT0 | GPSR4_SD3_CMD | GPSR4_SD3_CLK);
|
||||
pfc_reg_write(PFC_GPSR5, GPSR5_SSI_SDATA9
|
||||
| GPSR5_MSIOF0_SS2
|
||||
| GPSR5_MSIOF0_SS1
|
||||
| GPSR5_RX2_A
|
||||
| GPSR5_TX2_A
|
||||
| GPSR5_SCK2_A | GPSR5_RTS0_TANS_A | GPSR5_CTS0_A);
|
||||
pfc_reg_write(PFC_GPSR6, GPSR6_USB30_PWEN
|
||||
| GPSR6_SSI_SDATA6
|
||||
| GPSR6_SSI_WS6
|
||||
| GPSR6_SSI_WS5
|
||||
| GPSR6_SSI_SCK5
|
||||
| GPSR6_SSI_SDATA4
|
||||
| GPSR6_USB30_OVC
|
||||
| GPSR6_AUDIO_CLKA
|
||||
| GPSR6_SSI_SDATA3
|
||||
| GPSR6_SSI_WS349
|
||||
| GPSR6_SSI_SCK349
|
||||
| GPSR6_SSI_SDATA1
|
||||
| GPSR6_SSI_SDATA0
|
||||
| GPSR6_SSI_WS01239 | GPSR6_SSI_SCK01239);
|
||||
|
||||
/* initialize POC control */
|
||||
reg = mmio_read_32(PFC_IOCTRL30);
|
||||
reg = ((reg & IOCTRL30_MASK) | POC_SD1_DAT3_33V
|
||||
| POC_SD1_DAT2_33V
|
||||
| POC_SD1_DAT1_33V
|
||||
| POC_SD1_DAT0_33V
|
||||
| POC_SD1_CMD_33V
|
||||
| POC_SD1_CLK_33V
|
||||
| POC_SD0_DAT3_33V
|
||||
| POC_SD0_DAT2_33V
|
||||
| POC_SD0_DAT1_33V
|
||||
| POC_SD0_DAT0_33V | POC_SD0_CMD_33V | POC_SD0_CLK_33V);
|
||||
pfc_reg_write(PFC_IOCTRL30, reg);
|
||||
reg = mmio_read_32(PFC_IOCTRL32);
|
||||
reg = (reg & IOCTRL32_MASK);
|
||||
pfc_reg_write(PFC_IOCTRL32, reg);
|
||||
|
||||
/* initialize LSI pin pull-up/down control */
|
||||
pfc_reg_write(PFC_PUD0, 0xFDF80000U);
|
||||
pfc_reg_write(PFC_PUD1, 0xCE298464U);
|
||||
pfc_reg_write(PFC_PUD2, 0xA4C380F4U);
|
||||
pfc_reg_write(PFC_PUD3, 0x0000079FU);
|
||||
pfc_reg_write(PFC_PUD4, 0xFFF0FFFFU);
|
||||
pfc_reg_write(PFC_PUD5, 0x40000000U);
|
||||
|
||||
/* initialize LSI pin pull-enable register */
|
||||
pfc_reg_write(PFC_PUEN0, 0xFFF00000U);
|
||||
pfc_reg_write(PFC_PUEN1, 0x00000000U);
|
||||
pfc_reg_write(PFC_PUEN2, 0x00000004U);
|
||||
pfc_reg_write(PFC_PUEN3, 0x00000000U);
|
||||
pfc_reg_write(PFC_PUEN4, 0x07800010U);
|
||||
pfc_reg_write(PFC_PUEN5, 0x00000000U);
|
||||
|
||||
/* initialize positive/negative logic select */
|
||||
mmio_write_32(GPIO_POSNEG0, 0x00000000U);
|
||||
mmio_write_32(GPIO_POSNEG1, 0x00000000U);
|
||||
mmio_write_32(GPIO_POSNEG2, 0x00000000U);
|
||||
mmio_write_32(GPIO_POSNEG3, 0x00000000U);
|
||||
mmio_write_32(GPIO_POSNEG4, 0x00000000U);
|
||||
mmio_write_32(GPIO_POSNEG5, 0x00000000U);
|
||||
mmio_write_32(GPIO_POSNEG6, 0x00000000U);
|
||||
|
||||
/* initialize general IO/interrupt switching */
|
||||
mmio_write_32(GPIO_IOINTSEL0, 0x00020000U);
|
||||
mmio_write_32(GPIO_IOINTSEL1, 0x00000000U);
|
||||
mmio_write_32(GPIO_IOINTSEL2, 0x00000000U);
|
||||
mmio_write_32(GPIO_IOINTSEL3, 0x00000000U);
|
||||
mmio_write_32(GPIO_IOINTSEL4, 0x00000000U);
|
||||
mmio_write_32(GPIO_IOINTSEL5, 0x00000000U);
|
||||
mmio_write_32(GPIO_IOINTSEL6, 0x00000000U);
|
||||
|
||||
/* initialize general output register */
|
||||
mmio_write_32(GPIO_OUTDT0, 0x00000010U);
|
||||
mmio_write_32(GPIO_OUTDT1, 0x00100000U);
|
||||
mmio_write_32(GPIO_OUTDT2, 0x00000000U);
|
||||
mmio_write_32(GPIO_OUTDT3, 0x00008000U);
|
||||
mmio_write_32(GPIO_OUTDT5, 0x00060000U);
|
||||
mmio_write_32(GPIO_OUTDT6, 0x00000000U);
|
||||
|
||||
/* initialize general input/output switching */
|
||||
mmio_write_32(GPIO_INOUTSEL0, 0x00000010U);
|
||||
mmio_write_32(GPIO_INOUTSEL1, 0x00100020U);
|
||||
mmio_write_32(GPIO_INOUTSEL2, 0x03000000U);
|
||||
mmio_write_32(GPIO_INOUTSEL3, 0x00008000U);
|
||||
mmio_write_32(GPIO_INOUTSEL4, 0x00000000U);
|
||||
mmio_write_32(GPIO_INOUTSEL5, 0x00060000U);
|
||||
mmio_write_32(GPIO_INOUTSEL6, 0x00004000U);
|
||||
}
|
12
drivers/staging/renesas/rcar/pfc/E3/pfc_init_e3.h
Normal file
12
drivers/staging/renesas/rcar/pfc/E3/pfc_init_e3.h
Normal file
|
@ -0,0 +1,12 @@
|
|||
/*
|
||||
* Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef PFC_INIT_E3_H__
|
||||
#define PFC_INIT_E3_H__
|
||||
|
||||
void pfc_init_e3(void);
|
||||
|
||||
#endif /* PFC_INIT_E3_H__ */
|
1374
drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v1.c
Normal file
1374
drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v1.c
Normal file
File diff suppressed because it is too large
Load diff
12
drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v1.h
Normal file
12
drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v1.h
Normal file
|
@ -0,0 +1,12 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef PFC_INIT_H3_V1_H__
|
||||
#define PFC_INIT_H3_V1_H__
|
||||
|
||||
void pfc_init_h3_v1(void);
|
||||
|
||||
#endif /* PFC_INIT_H3_V1_H__ */
|
1421
drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v2.c
Normal file
1421
drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v2.c
Normal file
File diff suppressed because it is too large
Load diff
12
drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v2.h
Normal file
12
drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v2.h
Normal file
|
@ -0,0 +1,12 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef PFC_INIT_H3_V2_H__
|
||||
#define PFC_INIT_H3_V2_H__
|
||||
|
||||
void pfc_init_h3_v2(void);
|
||||
|
||||
#endif /* PFC_INIT_H3_V2_H__ */
|
1501
drivers/staging/renesas/rcar/pfc/M3/pfc_init_m3.c
Normal file
1501
drivers/staging/renesas/rcar/pfc/M3/pfc_init_m3.c
Normal file
File diff suppressed because it is too large
Load diff
12
drivers/staging/renesas/rcar/pfc/M3/pfc_init_m3.h
Normal file
12
drivers/staging/renesas/rcar/pfc/M3/pfc_init_m3.h
Normal file
|
@ -0,0 +1,12 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef PFC_INIT_M3_H__
|
||||
#define PFC_INIT_M3_H__
|
||||
|
||||
void pfc_init_m3(void);
|
||||
|
||||
#endif /* PFC_INIT_M3_H__ */
|
1409
drivers/staging/renesas/rcar/pfc/M3N/pfc_init_m3n.c
Normal file
1409
drivers/staging/renesas/rcar/pfc/M3N/pfc_init_m3n.c
Normal file
File diff suppressed because it is too large
Load diff
12
drivers/staging/renesas/rcar/pfc/M3N/pfc_init_m3n.h
Normal file
12
drivers/staging/renesas/rcar/pfc/M3N/pfc_init_m3n.h
Normal file
|
@ -0,0 +1,12 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef PFC_INIT_M3N_H__
|
||||
#define PFC_INIT_M3N_H__
|
||||
|
||||
void pfc_init_m3n(void);
|
||||
|
||||
#endif /* PFC_INIT_M3N_H__ */
|
56
drivers/staging/renesas/rcar/pfc/pfc.mk
Normal file
56
drivers/staging/renesas/rcar/pfc/pfc.mk
Normal file
|
@ -0,0 +1,56 @@
|
|||
#
|
||||
# Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
|
||||
ifeq (${RCAR_LSI},${RCAR_AUTO})
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v1.c
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v2.c
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/pfc/M3/pfc_init_m3.c
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/pfc/M3N/pfc_init_m3n.c
|
||||
|
||||
else ifdef RCAR_LSI_CUT_COMPAT
|
||||
ifeq (${RCAR_LSI},${RCAR_H3})
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v1.c
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v2.c
|
||||
endif
|
||||
ifeq (${RCAR_LSI},${RCAR_H3N})
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v1.c
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v2.c
|
||||
endif
|
||||
ifeq (${RCAR_LSI},${RCAR_M3})
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/pfc/M3/pfc_init_m3.c
|
||||
endif
|
||||
ifeq (${RCAR_LSI},${RCAR_M3N})
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/pfc/M3N/pfc_init_m3n.c
|
||||
endif
|
||||
ifeq (${RCAR_LSI},${RCAR_E3})
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/pfc/E3/pfc_init_e3.c
|
||||
endif
|
||||
else
|
||||
ifeq (${RCAR_LSI},${RCAR_H3})
|
||||
ifeq (${LSI_CUT},10)
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v1.c
|
||||
else ifeq (${LSI_CUT},11)
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v1.c
|
||||
else
|
||||
# LSI_CUT 20 or later
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v2.c
|
||||
endif
|
||||
endif
|
||||
ifeq (${RCAR_LSI},${RCAR_H3N})
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v2.c
|
||||
endif
|
||||
ifeq (${RCAR_LSI},${RCAR_M3})
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/pfc/M3/pfc_init_m3.c
|
||||
endif
|
||||
ifeq (${RCAR_LSI},${RCAR_M3N})
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/pfc/M3N/pfc_init_m3n.c
|
||||
endif
|
||||
ifeq (${RCAR_LSI},${RCAR_E3})
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/pfc/E3/pfc_init_e3.c
|
||||
endif
|
||||
endif
|
||||
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/pfc/pfc_init.c
|
172
drivers/staging/renesas/rcar/pfc/pfc_init.c
Normal file
172
drivers/staging/renesas/rcar/pfc/pfc_init.c
Normal file
|
@ -0,0 +1,172 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <debug.h>
|
||||
#include <mmio.h>
|
||||
#include "rcar_def.h"
|
||||
#if RCAR_LSI == RCAR_AUTO
|
||||
#include "H3/pfc_init_h3_v1.h"
|
||||
#include "H3/pfc_init_h3_v2.h"
|
||||
#include "M3/pfc_init_m3.h"
|
||||
#include "M3N/pfc_init_m3n.h"
|
||||
#endif
|
||||
#if (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N) /* H3 */
|
||||
#include "H3/pfc_init_h3_v1.h"
|
||||
#include "H3/pfc_init_h3_v2.h"
|
||||
#endif
|
||||
#if RCAR_LSI == RCAR_M3 /* M3 */
|
||||
#include "M3/pfc_init_m3.h"
|
||||
#endif
|
||||
#if RCAR_LSI == RCAR_M3N /* M3N */
|
||||
#include "M3N/pfc_init_m3n.h"
|
||||
#endif
|
||||
#if RCAR_LSI == RCAR_E3 /* E3 */
|
||||
#include "E3/pfc_init_e3.h"
|
||||
#endif
|
||||
|
||||
/* Product Register */
|
||||
#define PRR (0xFFF00044U)
|
||||
#define PRR_PRODUCT_MASK (0x00007F00U)
|
||||
#define PRR_CUT_MASK (0x000000FFU)
|
||||
#define PRR_PRODUCT_H3 (0x00004F00U) /* R-Car H3 */
|
||||
#define PRR_PRODUCT_M3 (0x00005200U) /* R-Car M3 */
|
||||
#define PRR_PRODUCT_M3N (0x00005500U) /* R-Car M3N */
|
||||
#define PRR_PRODUCT_E3 (0x00005700U) /* R-Car E3 */
|
||||
#define PRR_PRODUCT_10 (0x00U)
|
||||
#define PRR_PRODUCT_11 (0x01U)
|
||||
#define PRR_PRODUCT_20 (0x10U)
|
||||
|
||||
#define PRR_PRODUCT_ERR(reg) do{\
|
||||
ERROR("LSI Product ID(PRR=0x%x) PFC "\
|
||||
"initialize not supported.\n",reg);\
|
||||
panic();\
|
||||
}while(0)
|
||||
#define PRR_CUT_ERR(reg) do{\
|
||||
ERROR("LSI Cut ID(PRR=0x%x) PFC "\
|
||||
"initialize not supported.\n",reg);\
|
||||
panic();\
|
||||
}while(0)
|
||||
|
||||
void rcar_pfc_init(void)
|
||||
{
|
||||
uint32_t reg;
|
||||
|
||||
reg = mmio_read_32(RCAR_PRR);
|
||||
#if RCAR_LSI == RCAR_AUTO
|
||||
switch (reg & RCAR_PRODUCT_MASK) {
|
||||
case RCAR_PRODUCT_H3:
|
||||
switch (reg & PRR_CUT_MASK) {
|
||||
case PRR_PRODUCT_10: /* H3 Ver.1.0 */
|
||||
pfc_init_h3_v1();
|
||||
break;
|
||||
case PRR_PRODUCT_11: /* H3 Ver.1.1 */
|
||||
pfc_init_h3_v1();
|
||||
break;
|
||||
default: /* H3 Ver.2.0 or later */
|
||||
pfc_init_h3_v2();
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case RCAR_PRODUCT_M3:
|
||||
pfc_init_m3();
|
||||
break;
|
||||
case RCAR_PRODUCT_M3N:
|
||||
pfc_init_m3n();
|
||||
break;
|
||||
default:
|
||||
PRR_PRODUCT_ERR(reg);
|
||||
break;
|
||||
}
|
||||
|
||||
#elif RCAR_LSI_CUT_COMPAT
|
||||
switch (reg & PRR_PRODUCT_MASK) {
|
||||
case PRR_PRODUCT_H3:
|
||||
#if (RCAR_LSI != RCAR_H3) && (RCAR_LSI != RCAR_H3N)
|
||||
PRR_PRODUCT_ERR(reg);
|
||||
#else
|
||||
switch (reg & PRR_CUT_MASK) {
|
||||
case PRR_PRODUCT_10: /* H3 Ver.1.0 */
|
||||
pfc_init_h3_v1();
|
||||
break;
|
||||
case PRR_PRODUCT_11: /* H3 Ver.1.1 */
|
||||
pfc_init_h3_v1();
|
||||
break;
|
||||
default: /* H3 Ver.2.0 or later */
|
||||
pfc_init_h3_v2();
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
break;
|
||||
case PRR_PRODUCT_M3:
|
||||
#if RCAR_LSI != RCAR_M3
|
||||
PRR_PRODUCT_ERR(reg);
|
||||
#else
|
||||
pfc_init_m3();
|
||||
#endif
|
||||
break;
|
||||
case PRR_PRODUCT_M3N:
|
||||
#if RCAR_LSI != RCAR_M3N
|
||||
PRR_PRODUCT_ERR(reg);
|
||||
#else
|
||||
pfc_init_m3n();
|
||||
#endif
|
||||
break;
|
||||
case PRR_PRODUCT_E3:
|
||||
#if RCAR_LSI != RCAR_E3
|
||||
PRR_PRODUCT_ERR(reg);
|
||||
#else
|
||||
pfc_init_e3();
|
||||
#endif
|
||||
break;
|
||||
default:
|
||||
PRR_PRODUCT_ERR(reg);
|
||||
break;
|
||||
}
|
||||
|
||||
#else
|
||||
#if (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N) /* H3 */
|
||||
#if RCAR_LSI_CUT == RCAR_CUT_10
|
||||
/* H3 Ver.1.0 */
|
||||
if ((PRR_PRODUCT_H3 | PRR_PRODUCT_10)
|
||||
!= (reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK))) {
|
||||
PRR_PRODUCT_ERR(reg);
|
||||
}
|
||||
pfc_init_h3_v1();
|
||||
#elif RCAR_LSI_CUT == RCAR_CUT_11
|
||||
/* H3 Ver.1.1 */
|
||||
if ((PRR_PRODUCT_H3 | PRR_PRODUCT_11)
|
||||
!= (reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK))) {
|
||||
PRR_PRODUCT_ERR(reg);
|
||||
}
|
||||
pfc_init_h3_v1();
|
||||
#else
|
||||
/* H3 Ver.2.0 or later */
|
||||
if (PRR_PRODUCT_H3 != (reg & PRR_PRODUCT_MASK)) {
|
||||
PRR_PRODUCT_ERR(reg);
|
||||
}
|
||||
pfc_init_h3_v2();
|
||||
#endif
|
||||
#elif RCAR_LSI == RCAR_M3 /* M3 */
|
||||
if ((PRR_PRODUCT_M3) != (reg & PRR_PRODUCT_MASK)) {
|
||||
PRR_PRODUCT_ERR(reg);
|
||||
}
|
||||
pfc_init_m3();
|
||||
#elif RCAR_LSI == RCAR_M3N /* M3N */
|
||||
if ((PRR_PRODUCT_M3N) != (reg & PRR_PRODUCT_MASK)) {
|
||||
PRR_PRODUCT_ERR(reg);
|
||||
}
|
||||
pfc_init_m3n();
|
||||
#elif RCAR_LSI == RCAR_E3 /* E3 */
|
||||
if ((PRR_PRODUCT_E3) != (reg & PRR_PRODUCT_MASK)) {
|
||||
PRR_PRODUCT_ERR(reg);
|
||||
}
|
||||
pfc_init_e3();
|
||||
#else
|
||||
#error "Don't have PFC initialize routine(unknown)."
|
||||
#endif
|
||||
#endif
|
||||
}
|
159
drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10.c
Normal file
159
drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10.c
Normal file
|
@ -0,0 +1,159 @@
|
|||
/*
|
||||
* Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <debug.h>
|
||||
#include "../qos_common.h"
|
||||
#include "../qos_reg.h"
|
||||
#include "qos_init_e3_v10.h"
|
||||
|
||||
#define RCAR_QOS_VERSION "rev.0.02"
|
||||
|
||||
#define QOSCTRL_EARLYR (QOS_BASE1 + 0x0060U)
|
||||
#define QOSCTRL_FSS (QOS_BASE1 + 0x0048U)
|
||||
|
||||
#define REF_ARS_ARBSTOPCYCLE_E3 (((SL_INIT_SSLOTCLK_E3) - 5U) << 16U)
|
||||
|
||||
#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
|
||||
|
||||
#if RCAR_REF_INT == RCAR_REF_DEFAULT
|
||||
#include "qos_init_e3_v10_mstat390.h"
|
||||
#else
|
||||
#include "qos_init_e3_v10_mstat780.h"
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
static void dbsc_setting(void)
|
||||
{
|
||||
/* Register write enable */
|
||||
io_write_32(DBSC_DBSYSCNT0, 0x00001234U);
|
||||
|
||||
/* BUFCAM settings */
|
||||
io_write_32(DBSC_DBCAM0CNF1, 0x00043218);
|
||||
io_write_32(DBSC_DBCAM0CNF2, 0x000000F4);
|
||||
io_write_32(DBSC_DBSCHCNT0, 0x000F0037);
|
||||
io_write_32(DBSC_DBSCHSZ0, 0x00000001);
|
||||
io_write_32(DBSC_DBSCHRW0, 0x22421111);
|
||||
|
||||
/* DDR3 */
|
||||
io_write_32(DBSC_SCFCTST2, 0x012F1123);
|
||||
|
||||
/* QoS Settings */
|
||||
io_write_32(DBSC_DBSCHQOS00, 0x00000F00);
|
||||
io_write_32(DBSC_DBSCHQOS01, 0x00000B00);
|
||||
io_write_32(DBSC_DBSCHQOS02, 0x00000000);
|
||||
io_write_32(DBSC_DBSCHQOS03, 0x00000000);
|
||||
io_write_32(DBSC_DBSCHQOS40, 0x00000300);
|
||||
io_write_32(DBSC_DBSCHQOS41, 0x000002F0);
|
||||
io_write_32(DBSC_DBSCHQOS42, 0x00000200);
|
||||
io_write_32(DBSC_DBSCHQOS43, 0x00000100);
|
||||
io_write_32(DBSC_DBSCHQOS90, 0x00000100);
|
||||
io_write_32(DBSC_DBSCHQOS91, 0x000000F0);
|
||||
io_write_32(DBSC_DBSCHQOS92, 0x000000A0);
|
||||
io_write_32(DBSC_DBSCHQOS93, 0x00000040);
|
||||
io_write_32(DBSC_DBSCHQOS130, 0x00000100);
|
||||
io_write_32(DBSC_DBSCHQOS131, 0x000000F0);
|
||||
io_write_32(DBSC_DBSCHQOS132, 0x000000A0);
|
||||
io_write_32(DBSC_DBSCHQOS133, 0x00000040);
|
||||
io_write_32(DBSC_DBSCHQOS140, 0x000000C0);
|
||||
io_write_32(DBSC_DBSCHQOS141, 0x000000B0);
|
||||
io_write_32(DBSC_DBSCHQOS142, 0x00000080);
|
||||
io_write_32(DBSC_DBSCHQOS143, 0x00000040);
|
||||
io_write_32(DBSC_DBSCHQOS150, 0x00000040);
|
||||
io_write_32(DBSC_DBSCHQOS151, 0x00000030);
|
||||
io_write_32(DBSC_DBSCHQOS152, 0x00000020);
|
||||
io_write_32(DBSC_DBSCHQOS153, 0x00000010);
|
||||
|
||||
/* Register write protect */
|
||||
io_write_32(DBSC_DBSYSCNT0, 0x00000000U);
|
||||
}
|
||||
|
||||
void qos_init_e3_v10(void)
|
||||
{
|
||||
dbsc_setting();
|
||||
|
||||
/* DRAM Split Address mapping */
|
||||
#if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH
|
||||
#if RCAR_LSI == RCAR_E3
|
||||
#error "Don't set DRAM Split 4ch(E3)"
|
||||
#else
|
||||
ERROR("DRAM Split 4ch not supported.(E3)");
|
||||
panic();
|
||||
#endif
|
||||
#elif (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH)
|
||||
#if RCAR_LSI == RCAR_E3
|
||||
#error "Don't set DRAM Split 2ch(E3)"
|
||||
#else
|
||||
ERROR("DRAM Split 2ch not supported.(E3)");
|
||||
panic();
|
||||
#endif
|
||||
#else
|
||||
NOTICE("BL2: DRAM Split is OFF\n");
|
||||
#endif
|
||||
|
||||
#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
|
||||
#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
|
||||
NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
|
||||
#endif
|
||||
|
||||
#if RCAR_REF_INT == RCAR_REF_DEFAULT
|
||||
NOTICE("BL2: DRAM refresh interval 3.9 usec\n");
|
||||
#else
|
||||
NOTICE("BL2: DRAM refresh interval 7.8 usec\n");
|
||||
#endif
|
||||
|
||||
io_write_32(QOSCTRL_RAS, 0x00000020U);
|
||||
io_write_64(QOSCTRL_DANN, 0x0404020002020201UL);
|
||||
io_write_32(QOSCTRL_DANT, 0x00100804U);
|
||||
io_write_32(QOSCTRL_FSS, 0x0000000AU);
|
||||
io_write_32(QOSCTRL_INSFC, 0x06330001U);
|
||||
io_write_32(QOSCTRL_EARLYR, 0x00000000U);
|
||||
io_write_32(QOSCTRL_RACNT0, 0x00010003U);
|
||||
|
||||
io_write_32(QOSCTRL_SL_INIT,
|
||||
SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT |
|
||||
SL_INIT_SSLOTCLK_E3);
|
||||
io_write_32(QOSCTRL_REF_ARS, REF_ARS_ARBSTOPCYCLE_E3);
|
||||
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
|
||||
io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
|
||||
io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
|
||||
}
|
||||
for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
|
||||
io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
|
||||
io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
|
||||
}
|
||||
}
|
||||
|
||||
/* 3DG bus Leaf setting */
|
||||
io_write_32(GPU_ACT_GRD, 0x00001234U);
|
||||
io_write_32(GPU_ACT0, 0x00000000U);
|
||||
io_write_32(GPU_ACT1, 0x00000000U);
|
||||
io_write_32(GPU_ACT2, 0x00000000U);
|
||||
io_write_32(GPU_ACT3, 0x00000000U);
|
||||
io_write_32(GPU_ACT_GRD, 0x00000000U);
|
||||
|
||||
/* RT bus Leaf setting */
|
||||
io_write_32(RT_ACT0, 0x00000000U);
|
||||
io_write_32(RT_ACT1, 0x00000000U);
|
||||
|
||||
/* CCI bus Leaf setting */
|
||||
io_write_32(CPU_ACT0, 0x00000003U);
|
||||
io_write_32(CPU_ACT1, 0x00000003U);
|
||||
|
||||
io_write_32(QOSCTRL_RAEN, 0x00000001U);
|
||||
|
||||
io_write_32(QOSCTRL_STATQC, 0x00000001U);
|
||||
#else
|
||||
NOTICE("BL2: QoS is None\n");
|
||||
|
||||
io_write_32(QOSCTRL_RAEN, 0x00000001U);
|
||||
#endif
|
||||
}
|
12
drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10.h
Normal file
12
drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10.h
Normal file
|
@ -0,0 +1,12 @@
|
|||
/*
|
||||
* Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef QOS_INIT_H_E3_V10__
|
||||
#define QOS_INIT_H_E3_V10__
|
||||
|
||||
void qos_init_e3_v10(void);
|
||||
|
||||
#endif /* QOS_INIT_H_E3_V10__ */
|
241
drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10_mstat390.h
Normal file
241
drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10_mstat390.h
Normal file
|
@ -0,0 +1,241 @@
|
|||
/*
|
||||
* Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
static uint64_t mstat_fix[] = {
|
||||
/* 0x0000, */ 0x0000000000000000UL,
|
||||
/* 0x0008, */ 0x0000000000000000UL,
|
||||
/* 0x0010, */ 0x0000000000000000UL,
|
||||
/* 0x0018, */ 0x0000000000000000UL,
|
||||
/* 0x0020, */ 0x0000000000000000UL,
|
||||
/* 0x0028, */ 0x0000000000000000UL,
|
||||
/* 0x0030, */ 0x001008620000FFFFUL,
|
||||
/* 0x0038, */ 0x001008620000FFFFUL,
|
||||
/* 0x0040, */ 0x0000000000000000UL,
|
||||
/* 0x0048, */ 0x0000000000000000UL,
|
||||
/* 0x0050, */ 0x0000000000000000UL,
|
||||
/* 0x0058, */ 0x001415260000FFFFUL,
|
||||
/* 0x0060, */ 0x001415260000FFFFUL,
|
||||
/* 0x0068, */ 0x0000000000000000UL,
|
||||
/* 0x0070, */ 0x0000000000000000UL,
|
||||
/* 0x0078, */ 0x0000000000000000UL,
|
||||
/* 0x0080, */ 0x0000000000000000UL,
|
||||
/* 0x0088, */ 0x001414930000FFFFUL,
|
||||
/* 0x0090, */ 0x0000000000000000UL,
|
||||
/* 0x0098, */ 0x0000000000000000UL,
|
||||
/* 0x00a0, */ 0x000C08380000FFFFUL,
|
||||
/* 0x00a8, */ 0x000C04110000FFFFUL,
|
||||
/* 0x00b0, */ 0x000C04110000FFFFUL,
|
||||
/* 0x00b8, */ 0x0000000000000000UL,
|
||||
/* 0x00c0, */ 0x000C08380000FFFFUL,
|
||||
/* 0x00c8, */ 0x000C04110000FFFFUL,
|
||||
/* 0x00d0, */ 0x000C04110000FFFFUL,
|
||||
/* 0x00d8, */ 0x0000000000000000UL,
|
||||
/* 0x00e0, */ 0x0000000000000000UL,
|
||||
/* 0x00e8, */ 0x0000000000000000UL,
|
||||
/* 0x00f0, */ 0x001018580000FFFFUL,
|
||||
/* 0x00f8, */ 0x000C04400000FFFFUL,
|
||||
/* 0x0100, */ 0x0000000000000000UL,
|
||||
/* 0x0108, */ 0x0000000000000000UL,
|
||||
/* 0x0110, */ 0x001008580000FFFFUL,
|
||||
/* 0x0118, */ 0x000C19660000FFFFUL,
|
||||
/* 0x0120, */ 0x0000000000000000UL,
|
||||
/* 0x0128, */ 0x0000000000000000UL,
|
||||
/* 0x0130, */ 0x0000000000000000UL,
|
||||
/* 0x0138, */ 0x001008530000FFFFUL,
|
||||
/* 0x0140, */ 0x0000000000000000UL,
|
||||
/* 0x0148, */ 0x0000000000000000UL,
|
||||
/* 0x0150, */ 0x00100C960000FFFFUL,
|
||||
/* 0x0158, */ 0x0000000000000000UL,
|
||||
/* 0x0160, */ 0x001008530000FFFFUL,
|
||||
/* 0x0168, */ 0x0000000000000000UL,
|
||||
/* 0x0170, */ 0x0000000000000000UL,
|
||||
/* 0x0178, */ 0x0010042A0000FFFFUL,
|
||||
/* 0x0180, */ 0x0000000000000000UL,
|
||||
/* 0x0188, */ 0x0000000000000000UL,
|
||||
/* 0x0190, */ 0x00101D8D0000FFFFUL,
|
||||
/* 0x0198, */ 0x0000000000000000UL,
|
||||
/* 0x01a0, */ 0x001008530000FFFFUL,
|
||||
/* 0x01a8, */ 0x0000000000000000UL,
|
||||
/* 0x01b0, */ 0x0000000000000000UL,
|
||||
/* 0x01b8, */ 0x0000000000000000UL,
|
||||
/* 0x01c0, */ 0x000C04010000FFFFUL,
|
||||
/* 0x01c8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x01d0, */ 0x0000000000000000UL,
|
||||
/* 0x01d8, */ 0x0000000000000000UL,
|
||||
/* 0x01e0, */ 0x0000000000000000UL,
|
||||
/* 0x01e8, */ 0x000C04020000FFFFUL,
|
||||
/* 0x01f0, */ 0x000C04090000FFFFUL,
|
||||
/* 0x01f8, */ 0x0000000000000000UL,
|
||||
/* 0x0200, */ 0x0000000000000000UL,
|
||||
/* 0x0208, */ 0x000C04090000FFFFUL,
|
||||
/* 0x0210, */ 0x000C04090000FFFFUL,
|
||||
/* 0x0218, */ 0x0000000000000000UL,
|
||||
/* 0x0220, */ 0x0000000000000000UL,
|
||||
/* 0x0228, */ 0x0000000000000000UL,
|
||||
/* 0x0230, */ 0x0000000000000000UL,
|
||||
/* 0x0238, */ 0x0000000000000000UL,
|
||||
/* 0x0240, */ 0x0000000000000000UL,
|
||||
/* 0x0248, */ 0x0000000000000000UL,
|
||||
/* 0x0250, */ 0x0000000000000000UL,
|
||||
/* 0x0258, */ 0x0000000000000000UL,
|
||||
/* 0x0260, */ 0x000C0C2A0000FFFFUL,
|
||||
/* 0x0268, */ 0x001410040000FFFFUL,
|
||||
/* 0x0270, */ 0x001404020000FFFFUL,
|
||||
/* 0x0278, */ 0x000C08110000FFFFUL,
|
||||
/* 0x0280, */ 0x0000000000000000UL,
|
||||
/* 0x0288, */ 0x0000000000000000UL,
|
||||
/* 0x0290, */ 0x001410040000FFFFUL,
|
||||
/* 0x0298, */ 0x001404020000FFFFUL,
|
||||
/* 0x02a0, */ 0x000C04090000FFFFUL,
|
||||
/* 0x02a8, */ 0x000C04090000FFFFUL,
|
||||
/* 0x02b0, */ 0x0000000000000000UL,
|
||||
/* 0x02b8, */ 0x000C04020000FFFFUL,
|
||||
/* 0x02c0, */ 0x0000000000000000UL,
|
||||
/* 0x02c8, */ 0x0000000000000000UL,
|
||||
/* 0x02d0, */ 0x000C04090000FFFFUL,
|
||||
/* 0x02d8, */ 0x000C04090000FFFFUL,
|
||||
/* 0x02e0, */ 0x0000000000000000UL,
|
||||
/* 0x02e8, */ 0x000C04020000FFFFUL,
|
||||
/* 0x02f0, */ 0x0000000000000000UL,
|
||||
/* 0x02f8, */ 0x0000000000000000UL,
|
||||
/* 0x0300, */ 0x0000000000000000UL,
|
||||
/* 0x0308, */ 0x0000000000000000UL,
|
||||
/* 0x0310, */ 0x0000000000000000UL,
|
||||
/* 0x0318, */ 0x0000000000000000UL,
|
||||
/* 0x0320, */ 0x0000000000000000UL,
|
||||
/* 0x0328, */ 0x0000000000000000UL,
|
||||
/* 0x0330, */ 0x0000000000000000UL,
|
||||
/* 0x0338, */ 0x0000000000000000UL,
|
||||
/* 0x0340, */ 0x0000000000000000UL,
|
||||
/* 0x0348, */ 0x0000000000000000UL,
|
||||
/* 0x0350, */ 0x0000000000000000UL,
|
||||
/* 0x0358, */ 0x0000000000000000UL,
|
||||
/* 0x0360, */ 0x0000000000000000UL,
|
||||
/* 0x0368, */ 0x0000000000000000UL,
|
||||
/* 0x0370, */ 0x000C04020000FFFFUL,
|
||||
/* 0x0378, */ 0x000C04020000FFFFUL,
|
||||
/* 0x0380, */ 0x000C04090000FFFFUL,
|
||||
/* 0x0388, */ 0x000C04090000FFFFUL,
|
||||
/* 0x0390, */ 0x0000000000000000UL,
|
||||
};
|
||||
|
||||
static uint64_t mstat_be[] = {
|
||||
/* 0x0000, */ 0x0000000000000000UL,
|
||||
/* 0x0008, */ 0x0000000000000000UL,
|
||||
/* 0x0010, */ 0x0000000000000000UL,
|
||||
/* 0x0018, */ 0x0000000000000000UL,
|
||||
/* 0x0020, */ 0x0000000000000000UL,
|
||||
/* 0x0028, */ 0x0012001005F03401UL,
|
||||
/* 0x0030, */ 0x0000000000000000UL,
|
||||
/* 0x0038, */ 0x0000000000000000UL,
|
||||
/* 0x0040, */ 0x0000000000000000UL,
|
||||
/* 0x0048, */ 0x0000000000000000UL,
|
||||
/* 0x0050, */ 0x0000000000000000UL,
|
||||
/* 0x0058, */ 0x0000000000000000UL,
|
||||
/* 0x0060, */ 0x0000000000000000UL,
|
||||
/* 0x0068, */ 0x0000000000000000UL,
|
||||
/* 0x0070, */ 0x0000000000000000UL,
|
||||
/* 0x0078, */ 0x0000000000000000UL,
|
||||
/* 0x0080, */ 0x0000000000000000UL,
|
||||
/* 0x0088, */ 0x0000000000000000UL,
|
||||
/* 0x0090, */ 0x0000000000000000UL,
|
||||
/* 0x0098, */ 0x0000000000000000UL,
|
||||
/* 0x00a0, */ 0x0000000000000000UL,
|
||||
/* 0x00a8, */ 0x0000000000000000UL,
|
||||
/* 0x00b0, */ 0x0000000000000000UL,
|
||||
/* 0x00b8, */ 0x0000000000000000UL,
|
||||
/* 0x00c0, */ 0x0000000000000000UL,
|
||||
/* 0x00c8, */ 0x0000000000000000UL,
|
||||
/* 0x00d0, */ 0x0000000000000000UL,
|
||||
/* 0x00d8, */ 0x0000000000000000UL,
|
||||
/* 0x00e0, */ 0x0000000000000000UL,
|
||||
/* 0x00e8, */ 0x0000000000000000UL,
|
||||
/* 0x00f0, */ 0x0000000000000000UL,
|
||||
/* 0x00f8, */ 0x0000000000000000UL,
|
||||
/* 0x0100, */ 0x0000000000000000UL,
|
||||
/* 0x0108, */ 0x0000000000000000UL,
|
||||
/* 0x0110, */ 0x0000000000000000UL,
|
||||
/* 0x0118, */ 0x0000000000000000UL,
|
||||
/* 0x0120, */ 0x0000000000000000UL,
|
||||
/* 0x0128, */ 0x0000000000000000UL,
|
||||
/* 0x0130, */ 0x0000000000000000UL,
|
||||
/* 0x0138, */ 0x0000000000000000UL,
|
||||
/* 0x0140, */ 0x0000000000000000UL,
|
||||
/* 0x0148, */ 0x0000000000000000UL,
|
||||
/* 0x0150, */ 0x0000000000000000UL,
|
||||
/* 0x0158, */ 0x0000000000000000UL,
|
||||
/* 0x0160, */ 0x0000000000000000UL,
|
||||
/* 0x0168, */ 0x0000000000000000UL,
|
||||
/* 0x0170, */ 0x0000000000000000UL,
|
||||
/* 0x0178, */ 0x0000000000000000UL,
|
||||
/* 0x0180, */ 0x0000000000000000UL,
|
||||
/* 0x0188, */ 0x0000000000000000UL,
|
||||
/* 0x0190, */ 0x0000000000000000UL,
|
||||
/* 0x0198, */ 0x0000000000000000UL,
|
||||
/* 0x01a0, */ 0x0000000000000000UL,
|
||||
/* 0x01a8, */ 0x0000000000000000UL,
|
||||
/* 0x01b0, */ 0x0000000000000000UL,
|
||||
/* 0x01b8, */ 0x0000000000000000UL,
|
||||
/* 0x01c0, */ 0x0021060005FFFC01UL,
|
||||
/* 0x01c8, */ 0x0021060005FFFC01UL,
|
||||
/* 0x01d0, */ 0x0000000000000000UL,
|
||||
/* 0x01d8, */ 0x0000000000000000UL,
|
||||
/* 0x01e0, */ 0x0000000000000000UL,
|
||||
/* 0x01e8, */ 0x0000000000000000UL,
|
||||
/* 0x01f0, */ 0x0021010005F79801UL,
|
||||
/* 0x01f8, */ 0x0000000000000000UL,
|
||||
/* 0x0200, */ 0x0000000000000000UL,
|
||||
/* 0x0208, */ 0x0000000000000000UL,
|
||||
/* 0x0210, */ 0x0021010005F79801UL,
|
||||
/* 0x0218, */ 0x0011010005F79801UL,
|
||||
/* 0x0220, */ 0x0011010005F79801UL,
|
||||
/* 0x0228, */ 0x0000000000000000UL,
|
||||
/* 0x0230, */ 0x0011010005F79801UL,
|
||||
/* 0x0238, */ 0x0011010005F79801UL,
|
||||
/* 0x0240, */ 0x0012010005F79801UL,
|
||||
/* 0x0248, */ 0x0011010005F79801UL,
|
||||
/* 0x0250, */ 0x0012010005F79801UL,
|
||||
/* 0x0258, */ 0x0011010005F79801UL,
|
||||
/* 0x0260, */ 0x0000000000000000UL,
|
||||
/* 0x0268, */ 0x0000000000000000UL,
|
||||
/* 0x0270, */ 0x0000000000000000UL,
|
||||
/* 0x0278, */ 0x0000000000000000UL,
|
||||
/* 0x0280, */ 0x0000000000000000UL,
|
||||
/* 0x0288, */ 0x0000000000000000UL,
|
||||
/* 0x0290, */ 0x0000000000000000UL,
|
||||
/* 0x0298, */ 0x0000000000000000UL,
|
||||
/* 0x02a0, */ 0x0000000000000000UL,
|
||||
/* 0x02a8, */ 0x0000000000000000UL,
|
||||
/* 0x02b0, */ 0x0000000000000000UL,
|
||||
/* 0x02b8, */ 0x0000000000000000UL,
|
||||
/* 0x02c0, */ 0x0000000000000000UL,
|
||||
/* 0x02c8, */ 0x0000000000000000UL,
|
||||
/* 0x02d0, */ 0x0000000000000000UL,
|
||||
/* 0x02d8, */ 0x0000000000000000UL,
|
||||
/* 0x02e0, */ 0x0000000000000000UL,
|
||||
/* 0x02e8, */ 0x0000000000000000UL,
|
||||
/* 0x02f0, */ 0x0011060005FFFC01UL,
|
||||
/* 0x02f8, */ 0x0011060005FFFC01UL,
|
||||
/* 0x0300, */ 0x0000000000000000UL,
|
||||
/* 0x0308, */ 0x0000000000000000UL,
|
||||
/* 0x0310, */ 0x0000000000000000UL,
|
||||
/* 0x0318, */ 0x0012001005F03401UL,
|
||||
/* 0x0320, */ 0x0000000000000000UL,
|
||||
/* 0x0328, */ 0x0000000000000000UL,
|
||||
/* 0x0330, */ 0x0000000000000000UL,
|
||||
/* 0x0338, */ 0x0000000000000000UL,
|
||||
/* 0x0340, */ 0x0000000000000000UL,
|
||||
/* 0x0348, */ 0x0000000000000000UL,
|
||||
/* 0x0350, */ 0x0000000000000000UL,
|
||||
/* 0x0358, */ 0x0012060005FFFC01UL,
|
||||
/* 0x0360, */ 0x0012060005FFFC01UL,
|
||||
/* 0x0368, */ 0x0012001005F03401UL,
|
||||
/* 0x0370, */ 0x0000000000000000UL,
|
||||
/* 0x0378, */ 0x0000000000000000UL,
|
||||
/* 0x0380, */ 0x0000000000000000UL,
|
||||
/* 0x0388, */ 0x0000000000000000UL,
|
||||
/* 0x0390, */ 0x0012001005F03401UL,
|
||||
};
|
241
drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10_mstat780.h
Normal file
241
drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10_mstat780.h
Normal file
|
@ -0,0 +1,241 @@
|
|||
/*
|
||||
* Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
static uint64_t mstat_fix[] = {
|
||||
/* 0x0000, */ 0x0000000000000000UL,
|
||||
/* 0x0008, */ 0x0000000000000000UL,
|
||||
/* 0x0010, */ 0x0000000000000000UL,
|
||||
/* 0x0018, */ 0x0000000000000000UL,
|
||||
/* 0x0020, */ 0x0000000000000000UL,
|
||||
/* 0x0028, */ 0x0000000000000000UL,
|
||||
/* 0x0030, */ 0x001010C40000FFFFUL,
|
||||
/* 0x0038, */ 0x001010C40000FFFFUL,
|
||||
/* 0x0040, */ 0x0000000000000000UL,
|
||||
/* 0x0048, */ 0x0000000000000000UL,
|
||||
/* 0x0050, */ 0x0000000000000000UL,
|
||||
/* 0x0058, */ 0x00142A4B0000FFFFUL,
|
||||
/* 0x0060, */ 0x00142A4B0000FFFFUL,
|
||||
/* 0x0068, */ 0x0000000000000000UL,
|
||||
/* 0x0070, */ 0x0000000000000000UL,
|
||||
/* 0x0078, */ 0x0000000000000000UL,
|
||||
/* 0x0080, */ 0x0000000000000000UL,
|
||||
/* 0x0088, */ 0x001429260000FFFFUL,
|
||||
/* 0x0090, */ 0x0000000000000000UL,
|
||||
/* 0x0098, */ 0x0000000000000000UL,
|
||||
/* 0x00a0, */ 0x000C10700000FFFFUL,
|
||||
/* 0x00a8, */ 0x000C08210000FFFFUL,
|
||||
/* 0x00b0, */ 0x000C08210000FFFFUL,
|
||||
/* 0x00b8, */ 0x0000000000000000UL,
|
||||
/* 0x00c0, */ 0x000C10700000FFFFUL,
|
||||
/* 0x00c8, */ 0x000C08210000FFFFUL,
|
||||
/* 0x00d0, */ 0x000C08210000FFFFUL,
|
||||
/* 0x00d8, */ 0x0000000000000000UL,
|
||||
/* 0x00e0, */ 0x0000000000000000UL,
|
||||
/* 0x00e8, */ 0x0000000000000000UL,
|
||||
/* 0x00f0, */ 0x00102CAF0000FFFFUL,
|
||||
/* 0x00f8, */ 0x000C087F0000FFFFUL,
|
||||
/* 0x0100, */ 0x0000000000000000UL,
|
||||
/* 0x0108, */ 0x0000000000000000UL,
|
||||
/* 0x0110, */ 0x00100CAF0000FFFFUL,
|
||||
/* 0x0118, */ 0x000C32CC0000FFFFUL,
|
||||
/* 0x0120, */ 0x0000000000000000UL,
|
||||
/* 0x0128, */ 0x0000000000000000UL,
|
||||
/* 0x0130, */ 0x0000000000000000UL,
|
||||
/* 0x0138, */ 0x00100CA50000FFFFUL,
|
||||
/* 0x0140, */ 0x0000000000000000UL,
|
||||
/* 0x0148, */ 0x0000000000000000UL,
|
||||
/* 0x0150, */ 0x0010152C0000FFFFUL,
|
||||
/* 0x0158, */ 0x0000000000000000UL,
|
||||
/* 0x0160, */ 0x00100CA50000FFFFUL,
|
||||
/* 0x0168, */ 0x0000000000000000UL,
|
||||
/* 0x0170, */ 0x0000000000000000UL,
|
||||
/* 0x0178, */ 0x001008530000FFFFUL,
|
||||
/* 0x0180, */ 0x0000000000000000UL,
|
||||
/* 0x0188, */ 0x0000000000000000UL,
|
||||
/* 0x0190, */ 0x001037190000FFFFUL,
|
||||
/* 0x0198, */ 0x0000000000000000UL,
|
||||
/* 0x01a0, */ 0x00100CA50000FFFFUL,
|
||||
/* 0x01a8, */ 0x0000000000000000UL,
|
||||
/* 0x01b0, */ 0x0000000000000000UL,
|
||||
/* 0x01b8, */ 0x0000000000000000UL,
|
||||
/* 0x01c0, */ 0x000C04010000FFFFUL,
|
||||
/* 0x01c8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x01d0, */ 0x0000000000000000UL,
|
||||
/* 0x01d8, */ 0x0000000000000000UL,
|
||||
/* 0x01e0, */ 0x0000000000000000UL,
|
||||
/* 0x01e8, */ 0x000C04040000FFFFUL,
|
||||
/* 0x01f0, */ 0x000C08110000FFFFUL,
|
||||
/* 0x01f8, */ 0x0000000000000000UL,
|
||||
/* 0x0200, */ 0x0000000000000000UL,
|
||||
/* 0x0208, */ 0x000C04110000FFFFUL,
|
||||
/* 0x0210, */ 0x000C08110000FFFFUL,
|
||||
/* 0x0218, */ 0x0000000000000000UL,
|
||||
/* 0x0220, */ 0x0000000000000000UL,
|
||||
/* 0x0228, */ 0x0000000000000000UL,
|
||||
/* 0x0230, */ 0x0000000000000000UL,
|
||||
/* 0x0238, */ 0x0000000000000000UL,
|
||||
/* 0x0240, */ 0x0000000000000000UL,
|
||||
/* 0x0248, */ 0x0000000000000000UL,
|
||||
/* 0x0250, */ 0x0000000000000000UL,
|
||||
/* 0x0258, */ 0x0000000000000000UL,
|
||||
/* 0x0260, */ 0x000C18530000FFFFUL,
|
||||
/* 0x0268, */ 0x00141C070000FFFFUL,
|
||||
/* 0x0270, */ 0x001404040000FFFFUL,
|
||||
/* 0x0278, */ 0x000C0C210000FFFFUL,
|
||||
/* 0x0280, */ 0x0000000000000000UL,
|
||||
/* 0x0288, */ 0x0000000000000000UL,
|
||||
/* 0x0290, */ 0x00141C070000FFFFUL,
|
||||
/* 0x0298, */ 0x001404040000FFFFUL,
|
||||
/* 0x02a0, */ 0x000C04110000FFFFUL,
|
||||
/* 0x02a8, */ 0x000C04110000FFFFUL,
|
||||
/* 0x02b0, */ 0x0000000000000000UL,
|
||||
/* 0x02b8, */ 0x000C04040000FFFFUL,
|
||||
/* 0x02c0, */ 0x0000000000000000UL,
|
||||
/* 0x02c8, */ 0x0000000000000000UL,
|
||||
/* 0x02d0, */ 0x000C04110000FFFFUL,
|
||||
/* 0x02d8, */ 0x000C04110000FFFFUL,
|
||||
/* 0x02e0, */ 0x0000000000000000UL,
|
||||
/* 0x02e8, */ 0x000C04040000FFFFUL,
|
||||
/* 0x02f0, */ 0x0000000000000000UL,
|
||||
/* 0x02f8, */ 0x0000000000000000UL,
|
||||
/* 0x0300, */ 0x0000000000000000UL,
|
||||
/* 0x0308, */ 0x0000000000000000UL,
|
||||
/* 0x0310, */ 0x0000000000000000UL,
|
||||
/* 0x0318, */ 0x0000000000000000UL,
|
||||
/* 0x0320, */ 0x0000000000000000UL,
|
||||
/* 0x0328, */ 0x0000000000000000UL,
|
||||
/* 0x0330, */ 0x0000000000000000UL,
|
||||
/* 0x0338, */ 0x0000000000000000UL,
|
||||
/* 0x0340, */ 0x0000000000000000UL,
|
||||
/* 0x0348, */ 0x0000000000000000UL,
|
||||
/* 0x0350, */ 0x0000000000000000UL,
|
||||
/* 0x0358, */ 0x0000000000000000UL,
|
||||
/* 0x0360, */ 0x0000000000000000UL,
|
||||
/* 0x0368, */ 0x0000000000000000UL,
|
||||
/* 0x0370, */ 0x000C04040000FFFFUL,
|
||||
/* 0x0378, */ 0x000C04040000FFFFUL,
|
||||
/* 0x0380, */ 0x000C04110000FFFFUL,
|
||||
/* 0x0388, */ 0x000C04110000FFFFUL,
|
||||
/* 0x0390, */ 0x0000000000000000UL,
|
||||
};
|
||||
|
||||
static uint64_t mstat_be[] = {
|
||||
/* 0x0000, */ 0x0000000000000000UL,
|
||||
/* 0x0008, */ 0x0000000000000000UL,
|
||||
/* 0x0010, */ 0x0000000000000000UL,
|
||||
/* 0x0018, */ 0x0000000000000000UL,
|
||||
/* 0x0020, */ 0x0000000000000000UL,
|
||||
/* 0x0028, */ 0x0012001002F03401UL,
|
||||
/* 0x0030, */ 0x0000000000000000UL,
|
||||
/* 0x0038, */ 0x0000000000000000UL,
|
||||
/* 0x0040, */ 0x0000000000000000UL,
|
||||
/* 0x0048, */ 0x0000000000000000UL,
|
||||
/* 0x0050, */ 0x0000000000000000UL,
|
||||
/* 0x0058, */ 0x0000000000000000UL,
|
||||
/* 0x0060, */ 0x0000000000000000UL,
|
||||
/* 0x0068, */ 0x0000000000000000UL,
|
||||
/* 0x0070, */ 0x0000000000000000UL,
|
||||
/* 0x0078, */ 0x0000000000000000UL,
|
||||
/* 0x0080, */ 0x0000000000000000UL,
|
||||
/* 0x0088, */ 0x0000000000000000UL,
|
||||
/* 0x0090, */ 0x0000000000000000UL,
|
||||
/* 0x0098, */ 0x0000000000000000UL,
|
||||
/* 0x00a0, */ 0x0000000000000000UL,
|
||||
/* 0x00a8, */ 0x0000000000000000UL,
|
||||
/* 0x00b0, */ 0x0000000000000000UL,
|
||||
/* 0x00b8, */ 0x0000000000000000UL,
|
||||
/* 0x00c0, */ 0x0000000000000000UL,
|
||||
/* 0x00c8, */ 0x0000000000000000UL,
|
||||
/* 0x00d0, */ 0x0000000000000000UL,
|
||||
/* 0x00d8, */ 0x0000000000000000UL,
|
||||
/* 0x00e0, */ 0x0000000000000000UL,
|
||||
/* 0x00e8, */ 0x0000000000000000UL,
|
||||
/* 0x00f0, */ 0x0000000000000000UL,
|
||||
/* 0x00f8, */ 0x0000000000000000UL,
|
||||
/* 0x0100, */ 0x0000000000000000UL,
|
||||
/* 0x0108, */ 0x0000000000000000UL,
|
||||
/* 0x0110, */ 0x0000000000000000UL,
|
||||
/* 0x0118, */ 0x0000000000000000UL,
|
||||
/* 0x0120, */ 0x0000000000000000UL,
|
||||
/* 0x0128, */ 0x0000000000000000UL,
|
||||
/* 0x0130, */ 0x0000000000000000UL,
|
||||
/* 0x0138, */ 0x0000000000000000UL,
|
||||
/* 0x0140, */ 0x0000000000000000UL,
|
||||
/* 0x0148, */ 0x0000000000000000UL,
|
||||
/* 0x0150, */ 0x0000000000000000UL,
|
||||
/* 0x0158, */ 0x0000000000000000UL,
|
||||
/* 0x0160, */ 0x0000000000000000UL,
|
||||
/* 0x0168, */ 0x0000000000000000UL,
|
||||
/* 0x0170, */ 0x0000000000000000UL,
|
||||
/* 0x0178, */ 0x0000000000000000UL,
|
||||
/* 0x0180, */ 0x0000000000000000UL,
|
||||
/* 0x0188, */ 0x0000000000000000UL,
|
||||
/* 0x0190, */ 0x0000000000000000UL,
|
||||
/* 0x0198, */ 0x0000000000000000UL,
|
||||
/* 0x01a0, */ 0x0000000000000000UL,
|
||||
/* 0x01a8, */ 0x0000000000000000UL,
|
||||
/* 0x01b0, */ 0x0000000000000000UL,
|
||||
/* 0x01b8, */ 0x0000000000000000UL,
|
||||
/* 0x01c0, */ 0x0021060002FFFC01UL,
|
||||
/* 0x01c8, */ 0x0021060002FFFC01UL,
|
||||
/* 0x01d0, */ 0x0000000000000000UL,
|
||||
/* 0x01d8, */ 0x0000000000000000UL,
|
||||
/* 0x01e0, */ 0x0000000000000000UL,
|
||||
/* 0x01e8, */ 0x0000000000000000UL,
|
||||
/* 0x01f0, */ 0x0021010002F3CC01UL,
|
||||
/* 0x01f8, */ 0x0000000000000000UL,
|
||||
/* 0x0200, */ 0x0000000000000000UL,
|
||||
/* 0x0208, */ 0x0000000000000000UL,
|
||||
/* 0x0210, */ 0x0021010002F3CC01UL,
|
||||
/* 0x0218, */ 0x0011010002F3CC01UL,
|
||||
/* 0x0220, */ 0x0011010002F3CC01UL,
|
||||
/* 0x0228, */ 0x0000000000000000UL,
|
||||
/* 0x0230, */ 0x0011010002F3CC01UL,
|
||||
/* 0x0238, */ 0x0011010002F3CC01UL,
|
||||
/* 0x0240, */ 0x0012010002F3CC01UL,
|
||||
/* 0x0248, */ 0x0011010002F3CC01UL,
|
||||
/* 0x0250, */ 0x0012010002F3CC01UL,
|
||||
/* 0x0258, */ 0x0011010002F3CC01UL,
|
||||
/* 0x0260, */ 0x0000000000000000UL,
|
||||
/* 0x0268, */ 0x0000000000000000UL,
|
||||
/* 0x0270, */ 0x0000000000000000UL,
|
||||
/* 0x0278, */ 0x0000000000000000UL,
|
||||
/* 0x0280, */ 0x0000000000000000UL,
|
||||
/* 0x0288, */ 0x0000000000000000UL,
|
||||
/* 0x0290, */ 0x0000000000000000UL,
|
||||
/* 0x0298, */ 0x0000000000000000UL,
|
||||
/* 0x02a0, */ 0x0000000000000000UL,
|
||||
/* 0x02a8, */ 0x0000000000000000UL,
|
||||
/* 0x02b0, */ 0x0000000000000000UL,
|
||||
/* 0x02b8, */ 0x0000000000000000UL,
|
||||
/* 0x02c0, */ 0x0000000000000000UL,
|
||||
/* 0x02c8, */ 0x0000000000000000UL,
|
||||
/* 0x02d0, */ 0x0000000000000000UL,
|
||||
/* 0x02d8, */ 0x0000000000000000UL,
|
||||
/* 0x02e0, */ 0x0000000000000000UL,
|
||||
/* 0x02e8, */ 0x0000000000000000UL,
|
||||
/* 0x02f0, */ 0x0011060002FFFC01UL,
|
||||
/* 0x02f8, */ 0x0011060002FFFC01UL,
|
||||
/* 0x0300, */ 0x0000000000000000UL,
|
||||
/* 0x0308, */ 0x0000000000000000UL,
|
||||
/* 0x0310, */ 0x0000000000000000UL,
|
||||
/* 0x0318, */ 0x0012001002F03401UL,
|
||||
/* 0x0320, */ 0x0000000000000000UL,
|
||||
/* 0x0328, */ 0x0000000000000000UL,
|
||||
/* 0x0330, */ 0x0000000000000000UL,
|
||||
/* 0x0338, */ 0x0000000000000000UL,
|
||||
/* 0x0340, */ 0x0000000000000000UL,
|
||||
/* 0x0348, */ 0x0000000000000000UL,
|
||||
/* 0x0350, */ 0x0000000000000000UL,
|
||||
/* 0x0358, */ 0x0012060002FFFC01UL,
|
||||
/* 0x0360, */ 0x0012060002FFFC01UL,
|
||||
/* 0x0368, */ 0x0012001002F03401UL,
|
||||
/* 0x0370, */ 0x0000000000000000UL,
|
||||
/* 0x0378, */ 0x0000000000000000UL,
|
||||
/* 0x0380, */ 0x0000000000000000UL,
|
||||
/* 0x0388, */ 0x0000000000000000UL,
|
||||
/* 0x0390, */ 0x0012001002F03401UL,
|
||||
};
|
357
drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v10.c
Normal file
357
drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v10.c
Normal file
|
@ -0,0 +1,357 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <debug.h>
|
||||
#include "../qos_common.h"
|
||||
#include "qos_init_h3_v10.h"
|
||||
|
||||
#define RCAR_QOS_VERSION "rev.0.36"
|
||||
|
||||
#define RCAR_QOS_NONE (3U)
|
||||
#define RCAR_QOS_TYPE_DEFAULT (0U)
|
||||
|
||||
#define RCAR_DRAM_SPLIT_LINEAR (0U)
|
||||
#define RCAR_DRAM_SPLIT_4CH (1U)
|
||||
#define RCAR_DRAM_SPLIT_2CH (2U)
|
||||
#define RCAR_DRAM_SPLIT_AUTO (3U)
|
||||
|
||||
#define AXI_BASE (0xE6784000U)
|
||||
#define AXI_ADSPLCR0 (AXI_BASE + 0x0008U)
|
||||
#define AXI_ADSPLCR1 (AXI_BASE + 0x000CU)
|
||||
#define AXI_ADSPLCR2 (AXI_BASE + 0x0010U)
|
||||
#define AXI_ADSPLCR3 (AXI_BASE + 0x0014U)
|
||||
#define ADSPLCR0_ADRMODE_DEFAULT ((uint32_t)0U << 31U)
|
||||
#define ADSPLCR0_ADRMODE_GEN2 ((uint32_t)1U << 31U)
|
||||
#define ADSPLCR0_SPLITSEL(x) ((uint32_t)(x) << 16U)
|
||||
#define ADSPLCR0_AREA(x) ((uint32_t)(x) << 8U)
|
||||
#define ADSPLCR0_SWP (0x0CU)
|
||||
|
||||
#define MSTAT_BASE (0xE67E0000U)
|
||||
#define MSTAT_FIX_QOS_BANK0 (MSTAT_BASE + 0x0000U)
|
||||
#define MSTAT_FIX_QOS_BANK1 (MSTAT_BASE + 0x1000U)
|
||||
#define MSTAT_BE_QOS_BANK0 (MSTAT_BASE + 0x2000U)
|
||||
#define MSTAT_BE_QOS_BANK1 (MSTAT_BASE + 0x3000U)
|
||||
#define MSTAT_SL_INIT (MSTAT_BASE + 0x8000U)
|
||||
#define MSTAT_REF_ARS (MSTAT_BASE + 0x8004U)
|
||||
#define MSTAT_STATQC (MSTAT_BASE + 0x8008U)
|
||||
|
||||
#define RALLOC_BASE (0xE67F0000U)
|
||||
#define RALLOC_RAS (RALLOC_BASE + 0x0000U)
|
||||
#define RALLOC_FIXTH (RALLOC_BASE + 0x0004U)
|
||||
#define RALLOC_RAEN (RALLOC_BASE + 0x0018U)
|
||||
#define RALLOC_REGGD (RALLOC_BASE + 0x0020U)
|
||||
#define RALLOC_DANN (RALLOC_BASE + 0x0030U)
|
||||
#define RALLOC_DANT (RALLOC_BASE + 0x0038U)
|
||||
#define RALLOC_EC (RALLOC_BASE + 0x003CU)
|
||||
#define RALLOC_EMS (RALLOC_BASE + 0x0040U)
|
||||
#define RALLOC_INSFC (RALLOC_BASE + 0x0050U)
|
||||
#define RALLOC_BERR (RALLOC_BASE + 0x0054U)
|
||||
|
||||
#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
|
||||
static const mstat_slot_t mstat_fix[] = {
|
||||
{0x0000U, 0x0000000000000000UL},
|
||||
{0x0008U, 0x0000000000000000UL},
|
||||
{0x0010U, 0x0000000000000000UL},
|
||||
{0x0018U, 0x0000000000000000UL},
|
||||
{0x0020U, 0x0000000000000000UL},
|
||||
{0x0028U, 0x0000000000000000UL},
|
||||
{0x0030U, 0x0000000000000000UL},
|
||||
{0x0038U, 0x0000000000000000UL},
|
||||
{0x0040U, 0x00140C050000FFFFUL},
|
||||
{0x0048U, 0x0000000000000000UL},
|
||||
{0x0050U, 0x0000000000000000UL},
|
||||
{0x0058U, 0x001404030000FFFFUL},
|
||||
{0x0060U, 0x001408060000FFFFUL},
|
||||
{0x0068U, 0x0000000000000000UL},
|
||||
{0x0070U, 0x0000000000000000UL},
|
||||
{0x0078U, 0x0000000000000000UL},
|
||||
{0x0080U, 0x0000000000000000UL},
|
||||
{0x0088U, 0x00140C050000FFFFUL},
|
||||
{0x0090U, 0x001408060000FFFFUL},
|
||||
{0x0098U, 0x001404020000FFFFUL},
|
||||
{0x00A0U, 0x0000000000000000UL},
|
||||
{0x00A8U, 0x0000000000000000UL},
|
||||
{0x00B0U, 0x0000000000000000UL},
|
||||
{0x00B8U, 0x0000000000000000UL},
|
||||
{0x00C0U, 0x0000000000000000UL},
|
||||
{0x00C8U, 0x0000000000000000UL},
|
||||
{0x00D0U, 0x0000000000000000UL},
|
||||
{0x00D8U, 0x0000000000000000UL},
|
||||
{0x00E0U, 0x0000000000000000UL},
|
||||
{0x00E8U, 0x0000000000000000UL},
|
||||
{0x00F0U, 0x0000000000000000UL},
|
||||
{0x00F8U, 0x0000000000000000UL},
|
||||
{0x0100U, 0x0000000000000000UL},
|
||||
{0x0108U, 0x0000000000000000UL},
|
||||
{0x0110U, 0x0000000000000000UL},
|
||||
{0x0118U, 0x0000000000000000UL},
|
||||
{0x0120U, 0x0000000000000000UL},
|
||||
{0x0128U, 0x0000000000000000UL},
|
||||
{0x0130U, 0x0000000000000000UL},
|
||||
{0x0138U, 0x001004020000FFFFUL},
|
||||
{0x0140U, 0x001004020000FFFFUL},
|
||||
{0x0148U, 0x001004020000FFFFUL},
|
||||
{0x0150U, 0x001008050000FFFFUL},
|
||||
{0x0158U, 0x001008050000FFFFUL},
|
||||
{0x0160U, 0x001008050000FFFFUL},
|
||||
{0x0168U, 0x001008050000FFFFUL},
|
||||
{0x0170U, 0x001008050000FFFFUL},
|
||||
{0x0178U, 0x001004030000FFFFUL},
|
||||
{0x0180U, 0x001004030000FFFFUL},
|
||||
{0x0188U, 0x001004030000FFFFUL},
|
||||
{0x0190U, 0x001014140000FFFFUL},
|
||||
{0x0198U, 0x001014140000FFFFUL},
|
||||
{0x01A0U, 0x001008060000FFFFUL},
|
||||
{0x01A8U, 0x001008060000FFFFUL},
|
||||
{0x01B0U, 0x001008060000FFFFUL},
|
||||
{0x01B8U, 0x0000000000000000UL},
|
||||
{0x01C0U, 0x0000000000000000UL},
|
||||
{0x01C8U, 0x0000000000000000UL},
|
||||
{0x01D0U, 0x0000000000000000UL},
|
||||
{0x01D8U, 0x0000000000000000UL},
|
||||
{0x01E0U, 0x0000000000000000UL},
|
||||
{0x01E8U, 0x0000000000000000UL},
|
||||
{0x01F0U, 0x0000000000000000UL},
|
||||
{0x01F8U, 0x0000000000000000UL},
|
||||
{0x0200U, 0x0000000000000000UL},
|
||||
{0x0208U, 0x0000000000000000UL},
|
||||
{0x0210U, 0x0000000000000000UL},
|
||||
{0x0218U, 0x0000000000000000UL},
|
||||
{0x0220U, 0x0000000000000000UL},
|
||||
{0x0228U, 0x0000000000000000UL},
|
||||
{0x0230U, 0x0000000000000000UL},
|
||||
{0x0238U, 0x0000000000000000UL},
|
||||
{0x0240U, 0x0000000000000000UL},
|
||||
{0x0248U, 0x0000000000000000UL},
|
||||
{0x0250U, 0x0000000000000000UL},
|
||||
{0x0258U, 0x0000000000000000UL},
|
||||
{0x0260U, 0x0000000000000000UL},
|
||||
{0x0268U, 0x0000000000000000UL},
|
||||
{0x0270U, 0x0000000000000000UL},
|
||||
{0x0278U, 0x0000000000000000UL},
|
||||
{0x0280U, 0x0000000000000000UL},
|
||||
{0x0288U, 0x0000000000000000UL},
|
||||
{0x0290U, 0x0000000000000000UL},
|
||||
{0x0298U, 0x0000000000000000UL},
|
||||
{0x02A0U, 0x0000000000000000UL},
|
||||
{0x02A8U, 0x0000000000000000UL},
|
||||
{0x02B0U, 0x0000000000000000UL},
|
||||
{0x02B8U, 0x0000000000000000UL},
|
||||
{0x02C0U, 0x0000000000000000UL},
|
||||
{0x02C8U, 0x0000000000000000UL},
|
||||
{0x02D0U, 0x0000000000000000UL},
|
||||
{0x02D8U, 0x0000000000000000UL},
|
||||
{0x02E0U, 0x0000000000000000UL},
|
||||
{0x02E8U, 0x0000000000000000UL},
|
||||
{0x02F0U, 0x0000000000000000UL},
|
||||
{0x02F8U, 0x0000000000000000UL},
|
||||
{0x0300U, 0x0000000000000000UL},
|
||||
{0x0308U, 0x0000000000000000UL},
|
||||
{0x0310U, 0x0000000000000000UL},
|
||||
{0x0318U, 0x0000000000000000UL},
|
||||
{0x0320U, 0x0000000000000000UL},
|
||||
{0x0328U, 0x0000000000000000UL},
|
||||
{0x0330U, 0x0000000000000000UL},
|
||||
{0x0338U, 0x0000000000000000UL},
|
||||
};
|
||||
|
||||
static const mstat_slot_t mstat_be[] = {
|
||||
{0x0000U, 0x001000100C8FFC01UL},
|
||||
{0x0008U, 0x001000100C8FFC01UL},
|
||||
{0x0010U, 0x001000100C8FFC01UL},
|
||||
{0x0018U, 0x001000100C8FFC01UL},
|
||||
{0x0020U, 0x001000100C8FFC01UL},
|
||||
{0x0028U, 0x001000100C8FFC01UL},
|
||||
{0x0030U, 0x001000100C8FFC01UL},
|
||||
{0x0038U, 0x001000100C8FFC01UL},
|
||||
{0x0040U, 0x0000000000000000UL},
|
||||
{0x0048U, 0x0000000000000000UL},
|
||||
{0x0050U, 0x001000100C8FFC01UL},
|
||||
{0x0058U, 0x0000000000000000UL},
|
||||
{0x0060U, 0x0000000000000000UL},
|
||||
{0x0068U, 0x001000100C8FFC01UL},
|
||||
{0x0070U, 0x001000100C8FFC01UL},
|
||||
{0x0078U, 0x001000100C8FFC01UL},
|
||||
{0x0080U, 0x001000100C8FFC01UL},
|
||||
{0x0088U, 0x0000000000000000UL},
|
||||
{0x0090U, 0x0000000000000000UL},
|
||||
{0x0098U, 0x0000000000000000UL},
|
||||
{0x00A0U, 0x001000100C8FFC01UL},
|
||||
{0x00A8U, 0x001000100C8FFC01UL},
|
||||
{0x00B0U, 0x001000100C8FFC01UL},
|
||||
{0x00B8U, 0x001000100C8FFC01UL},
|
||||
{0x00C0U, 0x001000100C8FFC01UL},
|
||||
{0x00C8U, 0x001000100C8FFC01UL},
|
||||
{0x00D0U, 0x001000100C8FFC01UL},
|
||||
{0x00D8U, 0x002000200C8FFC01UL},
|
||||
{0x00E0U, 0x002000200C8FFC01UL},
|
||||
{0x00E8U, 0x001000100C8FFC01UL},
|
||||
{0x00F0U, 0x001000100C8FFC01UL},
|
||||
{0x00F8U, 0x001000100C8FFC01UL},
|
||||
{0x0100U, 0x0000000000000000UL},
|
||||
{0x0108U, 0x002000200C8FFC01UL},
|
||||
{0x0110U, 0x001000100C8FFC01UL},
|
||||
{0x0118U, 0x001000100C8FFC01UL},
|
||||
{0x0120U, 0x0000000000000000UL},
|
||||
{0x0128U, 0x002000200C8FFC01UL},
|
||||
{0x0130U, 0x001000100C8FFC01UL},
|
||||
{0x0138U, 0x0000000000000000UL},
|
||||
{0x0140U, 0x0000000000000000UL},
|
||||
{0x0148U, 0x0000000000000000UL},
|
||||
{0x0150U, 0x0000000000000000UL},
|
||||
{0x0158U, 0x0000000000000000UL},
|
||||
{0x0160U, 0x0000000000000000UL},
|
||||
{0x0168U, 0x0000000000000000UL},
|
||||
{0x0170U, 0x0000000000000000UL},
|
||||
{0x0178U, 0x0000000000000000UL},
|
||||
{0x0180U, 0x0000000000000000UL},
|
||||
{0x0188U, 0x0000000000000000UL},
|
||||
{0x0190U, 0x0000000000000000UL},
|
||||
{0x0198U, 0x0000000000000000UL},
|
||||
{0x01A0U, 0x0000000000000000UL},
|
||||
{0x01A8U, 0x0000000000000000UL},
|
||||
{0x01B0U, 0x0000000000000000UL},
|
||||
{0x01B8U, 0x001000100C8FFC01UL},
|
||||
{0x01C0U, 0x001000200C8FFC01UL},
|
||||
{0x01C8U, 0x001000200C8FFC01UL},
|
||||
{0x01D0U, 0x001000200C8FFC01UL},
|
||||
{0x01D8U, 0x001000200C8FFC01UL},
|
||||
{0x01E0U, 0x001000100C8FFC01UL},
|
||||
{0x01E8U, 0x001000100C8FFC01UL},
|
||||
{0x01F0U, 0x001000100C8FFC01UL},
|
||||
{0x01F8U, 0x001000100C8FFC01UL},
|
||||
{0x0200U, 0x001000100C8FFC01UL},
|
||||
{0x0208U, 0x001000100C8FFC01UL},
|
||||
{0x0210U, 0x001000100C8FFC01UL},
|
||||
{0x0218U, 0x001000100C8FFC01UL},
|
||||
{0x0220U, 0x001000100C8FFC01UL},
|
||||
{0x0228U, 0x001000100C8FFC01UL},
|
||||
{0x0230U, 0x001000100C8FFC01UL},
|
||||
{0x0238U, 0x001000100C8FFC01UL},
|
||||
{0x0240U, 0x001000100C8FFC01UL},
|
||||
{0x0248U, 0x001000100C8FFC01UL},
|
||||
{0x0250U, 0x001000100C8FFC01UL},
|
||||
{0x0258U, 0x001000100C8FFC01UL},
|
||||
{0x0260U, 0x001000100C8FFC01UL},
|
||||
{0x0268U, 0x001000100C8FFC01UL},
|
||||
{0x0270U, 0x001000100C8FFC01UL},
|
||||
{0x0278U, 0x001000100C8FFC01UL},
|
||||
{0x0280U, 0x001000100C8FFC01UL},
|
||||
{0x0288U, 0x001000100C8FFC01UL},
|
||||
{0x0290U, 0x001000100C8FFC01UL},
|
||||
{0x0298U, 0x001000100C8FFC01UL},
|
||||
{0x02A0U, 0x001000100C8FFC01UL},
|
||||
{0x02A8U, 0x001000100C8FFC01UL},
|
||||
{0x02B0U, 0x001000100C8FFC01UL},
|
||||
{0x02B8U, 0x001000100C8FFC01UL},
|
||||
{0x02C0U, 0x001000100C8FFC01UL},
|
||||
{0x02C8U, 0x001000100C8FFC01UL},
|
||||
{0x02D0U, 0x001000100C8FFC01UL},
|
||||
{0x02D8U, 0x001000100C8FFC01UL},
|
||||
{0x02E0U, 0x001000100C8FFC01UL},
|
||||
{0x02E8U, 0x001000100C8FFC01UL},
|
||||
{0x02F0U, 0x001000200C8FFC01UL},
|
||||
{0x02F8U, 0x001000300C8FFC01UL},
|
||||
{0x0300U, 0x0000000000000000UL},
|
||||
{0x0308U, 0x001000200C8FFC01UL},
|
||||
{0x0310U, 0x001000300C8FFC01UL},
|
||||
{0x0318U, 0x0000000000000000UL},
|
||||
{0x0320U, 0x001000200C8FFC01UL},
|
||||
{0x0328U, 0x001000300C8FFC01UL},
|
||||
{0x0330U, 0x001000200C8FFC01UL},
|
||||
{0x0338U, 0x001000300C8FFC01UL},
|
||||
};
|
||||
#endif
|
||||
|
||||
void qos_init_h3_v10(void)
|
||||
{
|
||||
/* DRAM Split Address mapping */
|
||||
#if (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH) || \
|
||||
(RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO)
|
||||
NOTICE("BL2: DRAM Split is 4ch\n");
|
||||
io_write_32(AXI_ADSPLCR0, ADSPLCR0_ADRMODE_DEFAULT
|
||||
| ADSPLCR0_SPLITSEL(0xFFU)
|
||||
| ADSPLCR0_AREA(0x1BU)
|
||||
| ADSPLCR0_SWP);
|
||||
io_write_32(AXI_ADSPLCR1, 0x00000000U);
|
||||
io_write_32(AXI_ADSPLCR2, 0xA8A90000U);
|
||||
io_write_32(AXI_ADSPLCR3, 0x00000000U);
|
||||
#elif RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH
|
||||
NOTICE("BL2: DRAM Split is 2ch\n");
|
||||
io_write_32(AXI_ADSPLCR0, 0x00000000U);
|
||||
io_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT
|
||||
| ADSPLCR0_SPLITSEL(0xFFU)
|
||||
| ADSPLCR0_AREA(0x1BU)
|
||||
| ADSPLCR0_SWP);
|
||||
io_write_32(AXI_ADSPLCR2, 0x00000000U);
|
||||
io_write_32(AXI_ADSPLCR3, 0x00000000U);
|
||||
#else
|
||||
NOTICE("BL2: DRAM Split is OFF\n");
|
||||
#endif
|
||||
|
||||
#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
|
||||
#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
|
||||
NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
|
||||
#endif
|
||||
|
||||
/* AR Cache setting */
|
||||
io_write_32(0xE67D1000U, 0x00000100U);
|
||||
io_write_32(0xE67D1008U, 0x00000100U);
|
||||
|
||||
/* Resource Alloc setting */
|
||||
io_write_32(RALLOC_RAS, 0x00000040U);
|
||||
io_write_32(RALLOC_FIXTH, 0x000F0005U);
|
||||
io_write_32(RALLOC_REGGD, 0x00000004U);
|
||||
io_write_64(RALLOC_DANN, 0x0202000004040404UL);
|
||||
io_write_32(RALLOC_DANT, 0x003C1110U);
|
||||
io_write_32(RALLOC_EC, 0x00080001U); /* need for H3 v1.* */
|
||||
io_write_64(RALLOC_EMS, 0x0000000000000000UL);
|
||||
io_write_32(RALLOC_INSFC, 0xC7840001U);
|
||||
io_write_32(RALLOC_BERR, 0x00000000U);
|
||||
|
||||
/* MSTAT setting */
|
||||
io_write_32(MSTAT_SL_INIT,
|
||||
SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT | SL_INIT_SSLOTCLK);
|
||||
io_write_32(MSTAT_REF_ARS, 0x00330000U);
|
||||
|
||||
/* MSTAT SRAM setting */
|
||||
for (uint32_t i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
|
||||
io_write_64(MSTAT_FIX_QOS_BANK0 + mstat_fix[i].addr,
|
||||
mstat_fix[i].value);
|
||||
io_write_64(MSTAT_FIX_QOS_BANK1 + mstat_fix[i].addr,
|
||||
mstat_fix[i].value);
|
||||
}
|
||||
for (uint32_t i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
|
||||
io_write_64(MSTAT_BE_QOS_BANK0 + mstat_be[i].addr,
|
||||
mstat_be[i].value);
|
||||
io_write_64(MSTAT_BE_QOS_BANK1 + mstat_be[i].addr,
|
||||
mstat_be[i].value);
|
||||
}
|
||||
|
||||
/* 3DG bus Leaf setting */
|
||||
io_write_32(0xFD820808U, 0x00001234U);
|
||||
io_write_32(0xFD820800U, 0x0000003FU);
|
||||
io_write_32(0xFD821800U, 0x0000003FU);
|
||||
io_write_32(0xFD822800U, 0x0000003FU);
|
||||
io_write_32(0xFD823800U, 0x0000003FU);
|
||||
io_write_32(0xFD824800U, 0x0000003FU);
|
||||
io_write_32(0xFD825800U, 0x0000003FU);
|
||||
io_write_32(0xFD826800U, 0x0000003FU);
|
||||
io_write_32(0xFD827800U, 0x0000003FU);
|
||||
|
||||
/* Resource Alloc start */
|
||||
io_write_32(RALLOC_RAEN, 0x00000001U);
|
||||
|
||||
/* MSTAT start */
|
||||
io_write_32(MSTAT_STATQC, 0x00000001U);
|
||||
#else
|
||||
NOTICE("BL2: QoS is None\n");
|
||||
|
||||
/* Resource Alloc setting */
|
||||
io_write_32(RALLOC_EC, 0x00080001U); /* need for H3 v1.* */
|
||||
#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
|
||||
}
|
12
drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v10.h
Normal file
12
drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v10.h
Normal file
|
@ -0,0 +1,12 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef QOS_INIT_H_H3_V10__
|
||||
#define QOS_INIT_H_H3_V10__
|
||||
|
||||
void qos_init_h3_v10(void);
|
||||
|
||||
#endif /* QOS_INIT_H_H3_V10__ */
|
607
drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v11.c
Normal file
607
drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v11.c
Normal file
|
@ -0,0 +1,607 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <debug.h>
|
||||
#include <rcar_def.h>
|
||||
#include "../qos_common.h"
|
||||
#include "qos_init_h3_v11.h"
|
||||
|
||||
#define RCAR_QOS_VERSION "rev.0.37"
|
||||
|
||||
#define RCAR_QOS_NONE (3U)
|
||||
#define RCAR_QOS_TYPE_DEFAULT (0U)
|
||||
|
||||
#define RCAR_DRAM_SPLIT_LINEAR (0U)
|
||||
#define RCAR_DRAM_SPLIT_4CH (1U)
|
||||
#define RCAR_DRAM_SPLIT_2CH (2U)
|
||||
#define RCAR_DRAM_SPLIT_AUTO (3U)
|
||||
|
||||
#define RST_BASE (0xE6160000U)
|
||||
#define RST_MODEMR (RST_BASE + 0x0060U)
|
||||
|
||||
#define RCAR_PWRSR8 (0xE6180340U) /* A3VP_PWRSR0 */
|
||||
#define RCAR_PWRONCR8 (0xE618034CU) /* A3VP_PWRONCR */
|
||||
#define RCAR_PWRSR9 (0xE6180380U) /* A3VC_PWRSR0 */
|
||||
#define RCAR_PWRONCR9 (0xE618038CU) /* A3VC_PWRONCR */
|
||||
#define RCAR_PWRSR10 (0xE61803C0U) /* A2VC_PWRSR0 */
|
||||
#define RCAR_PWRONCR10 (0xE61803CCU) /* A2VC_PWRONCR */
|
||||
|
||||
#define DBSC_BASE (0xE6790000U)
|
||||
#define DBSC_DBCAM0CNF0 (DBSC_BASE + 0x0900U)
|
||||
#define DBSC_DBCAM0CNF1 (DBSC_BASE + 0x0904U)
|
||||
#define DBSC_DBCAM0CNF2 (DBSC_BASE + 0x0908U)
|
||||
#define DBSC_DBCAM0CNF3 (DBSC_BASE + 0x090CU)
|
||||
#define DBSC_DBCAMDIS (DBSC_BASE + 0x09fCU)
|
||||
#define DBSC_DBSCHCNT0 (DBSC_BASE + 0x1000U)
|
||||
#define DBSC_DBSCHCNT1 (DBSC_BASE + 0x1004U)
|
||||
#define DBSC_DBSCHSZ0 (DBSC_BASE + 0x1010U)
|
||||
#define DBSC_DBSCHRW0 (DBSC_BASE + 0x1020U)
|
||||
#define DBSC_DBSCHQOS_0_0 (DBSC_BASE + 0x1030U)
|
||||
#define DBSC_DBSCHQOS_0_1 (DBSC_BASE + 0x1034U)
|
||||
#define DBSC_DBSCHQOS_0_2 (DBSC_BASE + 0x1038U)
|
||||
#define DBSC_DBSCHQOS_0_3 (DBSC_BASE + 0x103CU)
|
||||
#define DBSC_DBSCHQOS_1_0 (DBSC_BASE + 0x1040U)
|
||||
#define DBSC_DBSCHQOS_1_1 (DBSC_BASE + 0x1044U)
|
||||
#define DBSC_DBSCHQOS_1_2 (DBSC_BASE + 0x1048U)
|
||||
#define DBSC_DBSCHQOS_1_3 (DBSC_BASE + 0x104CU)
|
||||
#define DBSC_DBSCHQOS_2_0 (DBSC_BASE + 0x1050U)
|
||||
#define DBSC_DBSCHQOS_2_1 (DBSC_BASE + 0x1054U)
|
||||
#define DBSC_DBSCHQOS_2_2 (DBSC_BASE + 0x1058U)
|
||||
#define DBSC_DBSCHQOS_2_3 (DBSC_BASE + 0x105CU)
|
||||
#define DBSC_DBSCHQOS_3_0 (DBSC_BASE + 0x1060U)
|
||||
#define DBSC_DBSCHQOS_3_1 (DBSC_BASE + 0x1064U)
|
||||
#define DBSC_DBSCHQOS_3_2 (DBSC_BASE + 0x1068U)
|
||||
#define DBSC_DBSCHQOS_3_3 (DBSC_BASE + 0x106CU)
|
||||
#define DBSC_DBSCHQOS_4_0 (DBSC_BASE + 0x1070U)
|
||||
#define DBSC_DBSCHQOS_4_1 (DBSC_BASE + 0x1074U)
|
||||
#define DBSC_DBSCHQOS_4_2 (DBSC_BASE + 0x1078U)
|
||||
#define DBSC_DBSCHQOS_4_3 (DBSC_BASE + 0x107CU)
|
||||
#define DBSC_DBSCHQOS_5_0 (DBSC_BASE + 0x1080U)
|
||||
#define DBSC_DBSCHQOS_5_1 (DBSC_BASE + 0x1084U)
|
||||
#define DBSC_DBSCHQOS_5_2 (DBSC_BASE + 0x1088U)
|
||||
#define DBSC_DBSCHQOS_5_3 (DBSC_BASE + 0x108CU)
|
||||
#define DBSC_DBSCHQOS_6_0 (DBSC_BASE + 0x1090U)
|
||||
#define DBSC_DBSCHQOS_6_1 (DBSC_BASE + 0x1094U)
|
||||
#define DBSC_DBSCHQOS_6_2 (DBSC_BASE + 0x1098U)
|
||||
#define DBSC_DBSCHQOS_6_3 (DBSC_BASE + 0x109CU)
|
||||
#define DBSC_DBSCHQOS_7_0 (DBSC_BASE + 0x10A0U)
|
||||
#define DBSC_DBSCHQOS_7_1 (DBSC_BASE + 0x10A4U)
|
||||
#define DBSC_DBSCHQOS_7_2 (DBSC_BASE + 0x10A8U)
|
||||
#define DBSC_DBSCHQOS_7_3 (DBSC_BASE + 0x10ACU)
|
||||
#define DBSC_DBSCHQOS_8_0 (DBSC_BASE + 0x10B0U)
|
||||
#define DBSC_DBSCHQOS_8_1 (DBSC_BASE + 0x10B4U)
|
||||
#define DBSC_DBSCHQOS_8_2 (DBSC_BASE + 0x10B8U)
|
||||
#define DBSC_DBSCHQOS_8_3 (DBSC_BASE + 0x10BCU)
|
||||
#define DBSC_DBSCHQOS_9_0 (DBSC_BASE + 0x10C0U)
|
||||
#define DBSC_DBSCHQOS_9_1 (DBSC_BASE + 0x10C4U)
|
||||
#define DBSC_DBSCHQOS_9_2 (DBSC_BASE + 0x10C8U)
|
||||
#define DBSC_DBSCHQOS_9_3 (DBSC_BASE + 0x10CCU)
|
||||
#define DBSC_DBSCHQOS_10_0 (DBSC_BASE + 0x10D0U)
|
||||
#define DBSC_DBSCHQOS_10_1 (DBSC_BASE + 0x10D4U)
|
||||
#define DBSC_DBSCHQOS_10_2 (DBSC_BASE + 0x10D8U)
|
||||
#define DBSC_DBSCHQOS_10_3 (DBSC_BASE + 0x10DCU)
|
||||
#define DBSC_DBSCHQOS_11_0 (DBSC_BASE + 0x10E0U)
|
||||
#define DBSC_DBSCHQOS_11_1 (DBSC_BASE + 0x10E4U)
|
||||
#define DBSC_DBSCHQOS_11_2 (DBSC_BASE + 0x10E8U)
|
||||
#define DBSC_DBSCHQOS_11_3 (DBSC_BASE + 0x10ECU)
|
||||
#define DBSC_DBSCHQOS_12_0 (DBSC_BASE + 0x10F0U)
|
||||
#define DBSC_DBSCHQOS_12_1 (DBSC_BASE + 0x10F4U)
|
||||
#define DBSC_DBSCHQOS_12_2 (DBSC_BASE + 0x10F8U)
|
||||
#define DBSC_DBSCHQOS_12_3 (DBSC_BASE + 0x10FCU)
|
||||
#define DBSC_DBSCHQOS_13_0 (DBSC_BASE + 0x1100U)
|
||||
#define DBSC_DBSCHQOS_13_1 (DBSC_BASE + 0x1104U)
|
||||
#define DBSC_DBSCHQOS_13_2 (DBSC_BASE + 0x1108U)
|
||||
#define DBSC_DBSCHQOS_13_3 (DBSC_BASE + 0x110CU)
|
||||
#define DBSC_DBSCHQOS_14_0 (DBSC_BASE + 0x1110U)
|
||||
#define DBSC_DBSCHQOS_14_1 (DBSC_BASE + 0x1114U)
|
||||
#define DBSC_DBSCHQOS_14_2 (DBSC_BASE + 0x1118U)
|
||||
#define DBSC_DBSCHQOS_14_3 (DBSC_BASE + 0x111CU)
|
||||
#define DBSC_DBSCHQOS_15_0 (DBSC_BASE + 0x1120U)
|
||||
#define DBSC_DBSCHQOS_15_1 (DBSC_BASE + 0x1124U)
|
||||
#define DBSC_DBSCHQOS_15_2 (DBSC_BASE + 0x1128U)
|
||||
#define DBSC_DBSCHQOS_15_3 (DBSC_BASE + 0x112CU)
|
||||
#define DBSC_SCFCTST2 (DBSC_BASE + 0x170CU)
|
||||
|
||||
#define AXI_BASE (0xE6784000U)
|
||||
#define AXI_ADSPLCR0 (AXI_BASE + 0x0008U)
|
||||
#define AXI_ADSPLCR1 (AXI_BASE + 0x000CU)
|
||||
#define AXI_ADSPLCR2 (AXI_BASE + 0x0010U)
|
||||
#define AXI_ADSPLCR3 (AXI_BASE + 0x0014U)
|
||||
#define ADSPLCR0_ADRMODE_DEFAULT ((uint32_t)0U << 31U)
|
||||
#define ADSPLCR0_ADRMODE_GEN2 ((uint32_t)1U << 31U)
|
||||
#define ADSPLCR0_SPLITSEL(x) ((uint32_t)(x) << 16U)
|
||||
#define ADSPLCR0_AREA(x) ((uint32_t)(x) << 8U)
|
||||
#define ADSPLCR0_SWP (0x0CU)
|
||||
|
||||
#define MSTAT_BASE (0xE67E0000U)
|
||||
#define MSTAT_FIX_QOS_BANK0 (MSTAT_BASE + 0x0000U)
|
||||
#define MSTAT_FIX_QOS_BANK1 (MSTAT_BASE + 0x1000U)
|
||||
#define MSTAT_BE_QOS_BANK0 (MSTAT_BASE + 0x2000U)
|
||||
#define MSTAT_BE_QOS_BANK1 (MSTAT_BASE + 0x3000U)
|
||||
#define MSTAT_SL_INIT (MSTAT_BASE + 0x8000U)
|
||||
#define MSTAT_REF_ARS (MSTAT_BASE + 0x8004U)
|
||||
#define MSTAT_STATQC (MSTAT_BASE + 0x8008U)
|
||||
|
||||
#define RALLOC_BASE (0xE67F0000U)
|
||||
#define RALLOC_RAS (RALLOC_BASE + 0x0000U)
|
||||
#define RALLOC_FIXTH (RALLOC_BASE + 0x0004U)
|
||||
#define RALLOC_RAEN (RALLOC_BASE + 0x0018U)
|
||||
#define RALLOC_REGGD (RALLOC_BASE + 0x0020U)
|
||||
#define RALLOC_DANN (RALLOC_BASE + 0x0030U)
|
||||
#define RALLOC_DANT (RALLOC_BASE + 0x0038U)
|
||||
#define RALLOC_EC (RALLOC_BASE + 0x003CU)
|
||||
#define RALLOC_EMS (RALLOC_BASE + 0x0040U)
|
||||
#define RALLOC_INSFC (RALLOC_BASE + 0x0050U)
|
||||
#define RALLOC_BERR (RALLOC_BASE + 0x0054U)
|
||||
#define RALLOC_RACNT0 (RALLOC_BASE + 0x0080U)
|
||||
|
||||
#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
|
||||
static const mstat_slot_t mstat_fix[] = {
|
||||
{0x0000U, 0x0000000000000000UL},
|
||||
{0x0008U, 0x0000000000000000UL},
|
||||
{0x0010U, 0x0000000000000000UL},
|
||||
{0x0018U, 0x0000000000000000UL},
|
||||
{0x0020U, 0x0000000000000000UL},
|
||||
{0x0028U, 0x0000000000000000UL},
|
||||
{0x0030U, 0x001004030000FFFFUL},
|
||||
{0x0038U, 0x001008060000FFFFUL},
|
||||
{0x0040U, 0x001414090000FFFFUL},
|
||||
{0x0048U, 0x0000000000000000UL},
|
||||
{0x0050U, 0x001410010000FFFFUL},
|
||||
{0x0058U, 0x00140C0C0000FFFFUL},
|
||||
{0x0060U, 0x00140C0C0000FFFFUL},
|
||||
{0x0068U, 0x0000000000000000UL},
|
||||
{0x0070U, 0x001410010000FFFFUL},
|
||||
{0x0078U, 0x001008060000FFFFUL},
|
||||
{0x0080U, 0x001004020000FFFFUL},
|
||||
{0x0088U, 0x001414090000FFFFUL},
|
||||
{0x0090U, 0x00140C0C0000FFFFUL},
|
||||
{0x0098U, 0x001408080000FFFFUL},
|
||||
{0x00A0U, 0x000C08020000FFFFUL},
|
||||
{0x00A8U, 0x000C04010000FFFFUL},
|
||||
{0x00B0U, 0x000C04010000FFFFUL},
|
||||
{0x00B8U, 0x0000000000000000UL},
|
||||
{0x00C0U, 0x000C08020000FFFFUL},
|
||||
{0x00C8U, 0x000C04010000FFFFUL},
|
||||
{0x00D0U, 0x000C04010000FFFFUL},
|
||||
{0x00D8U, 0x000C04030000FFFFUL},
|
||||
{0x00E0U, 0x000C100F0000FFFFUL},
|
||||
{0x00E8U, 0x0000000000000000UL},
|
||||
{0x00F0U, 0x001010080000FFFFUL},
|
||||
{0x00F8U, 0x001010080000FFFFUL},
|
||||
{0x0100U, 0x0000000000000000UL},
|
||||
{0x0108U, 0x000C04030000FFFFUL},
|
||||
{0x0110U, 0x001010080000FFFFUL},
|
||||
{0x0118U, 0x001010080000FFFFUL},
|
||||
{0x0120U, 0x0000000000000000UL},
|
||||
{0x0128U, 0x000C100E0000FFFFUL},
|
||||
{0x0130U, 0x0000000000000000UL},
|
||||
{0x0138U, 0x001008050000FFFFUL},
|
||||
{0x0140U, 0x001008050000FFFFUL},
|
||||
{0x0148U, 0x001008050000FFFFUL},
|
||||
{0x0150U, 0x001008050000FFFFUL},
|
||||
{0x0158U, 0x001008050000FFFFUL},
|
||||
{0x0160U, 0x001008050000FFFFUL},
|
||||
{0x0168U, 0x001008050000FFFFUL},
|
||||
{0x0170U, 0x001008050000FFFFUL},
|
||||
{0x0178U, 0x001004030000FFFFUL},
|
||||
{0x0180U, 0x001004030000FFFFUL},
|
||||
{0x0188U, 0x001004030000FFFFUL},
|
||||
{0x0190U, 0x001014140000FFFFUL},
|
||||
{0x0198U, 0x001014140000FFFFUL},
|
||||
{0x01A0U, 0x001008050000FFFFUL},
|
||||
{0x01A8U, 0x001008050000FFFFUL},
|
||||
{0x01B0U, 0x001008050000FFFFUL},
|
||||
{0x01B8U, 0x0000000000000000UL},
|
||||
{0x01C0U, 0x0000000000000000UL},
|
||||
{0x01C8U, 0x0000000000000000UL},
|
||||
{0x01D0U, 0x0000000000000000UL},
|
||||
{0x01D8U, 0x0000000000000000UL},
|
||||
{0x01E0U, 0x0000000000000000UL},
|
||||
{0x01E8U, 0x0000000000000000UL},
|
||||
{0x01F0U, 0x0000000000000000UL},
|
||||
{0x01F8U, 0x0000000000000000UL},
|
||||
{0x0200U, 0x0000000000000000UL},
|
||||
{0x0208U, 0x0000000000000000UL},
|
||||
{0x0210U, 0x0000000000000000UL},
|
||||
{0x0218U, 0x0000000000000000UL},
|
||||
{0x0220U, 0x0000000000000000UL},
|
||||
{0x0228U, 0x0000000000000000UL},
|
||||
{0x0230U, 0x0000000000000000UL},
|
||||
{0x0238U, 0x0000000000000000UL},
|
||||
{0x0240U, 0x0000000000000000UL},
|
||||
{0x0248U, 0x0000000000000000UL},
|
||||
{0x0250U, 0x0000000000000000UL},
|
||||
{0x0258U, 0x0000000000000000UL},
|
||||
{0x0260U, 0x0000000000000000UL},
|
||||
{0x0268U, 0x001408010000FFFFUL},
|
||||
{0x0270U, 0x001404010000FFFFUL},
|
||||
{0x0278U, 0x0000000000000000UL},
|
||||
{0x0280U, 0x0000000000000000UL},
|
||||
{0x0288U, 0x0000000000000000UL},
|
||||
{0x0290U, 0x001408010000FFFFUL},
|
||||
{0x0298U, 0x001404010000FFFFUL},
|
||||
{0x02A0U, 0x000C04010000FFFFUL},
|
||||
{0x02A8U, 0x000C04010000FFFFUL},
|
||||
{0x02B0U, 0x001404010000FFFFUL},
|
||||
{0x02B8U, 0x0000000000000000UL},
|
||||
{0x02C0U, 0x0000000000000000UL},
|
||||
{0x02C8U, 0x0000000000000000UL},
|
||||
{0x02D0U, 0x000C04010000FFFFUL},
|
||||
{0x02D8U, 0x000C04010000FFFFUL},
|
||||
{0x02E0U, 0x001404010000FFFFUL},
|
||||
{0x02E8U, 0x0000000000000000UL},
|
||||
{0x02F0U, 0x0000000000000000UL},
|
||||
{0x02F8U, 0x0000000000000000UL},
|
||||
{0x0300U, 0x0000000000000000UL},
|
||||
{0x0308U, 0x0000000000000000UL},
|
||||
{0x0310U, 0x0000000000000000UL},
|
||||
{0x0318U, 0x0000000000000000UL},
|
||||
{0x0320U, 0x0000000000000000UL},
|
||||
{0x0328U, 0x0000000000000000UL},
|
||||
{0x0330U, 0x0000000000000000UL},
|
||||
{0x0338U, 0x0000000000000000UL},
|
||||
};
|
||||
|
||||
static const mstat_slot_t mstat_be[] = {
|
||||
{0x0000U, 0x001200100C89C401UL},
|
||||
{0x0008U, 0x001200100C89C401UL},
|
||||
{0x0010U, 0x001200100C89C401UL},
|
||||
{0x0018U, 0x001200100C89C401UL},
|
||||
{0x0020U, 0x001100100C803401UL},
|
||||
{0x0028U, 0x001100100C80FC01UL},
|
||||
{0x0030U, 0x0000000000000000UL},
|
||||
{0x0038U, 0x0000000000000000UL},
|
||||
{0x0040U, 0x0000000000000000UL},
|
||||
{0x0048U, 0x0000000000000000UL},
|
||||
{0x0050U, 0x0000000000000000UL},
|
||||
{0x0058U, 0x0000000000000000UL},
|
||||
{0x0060U, 0x0000000000000000UL},
|
||||
{0x0068U, 0x001100100C803401UL},
|
||||
{0x0070U, 0x0000000000000000UL},
|
||||
{0x0078U, 0x0000000000000000UL},
|
||||
{0x0080U, 0x0000000000000000UL},
|
||||
{0x0088U, 0x0000000000000000UL},
|
||||
{0x0090U, 0x0000000000000000UL},
|
||||
{0x0098U, 0x0000000000000000UL},
|
||||
{0x00A0U, 0x0000000000000000UL},
|
||||
{0x00A8U, 0x0000000000000000UL},
|
||||
{0x00B0U, 0x0000000000000000UL},
|
||||
{0x00B8U, 0x001100100C803401UL},
|
||||
{0x00C0U, 0x0000000000000000UL},
|
||||
{0x00C8U, 0x0000000000000000UL},
|
||||
{0x00D0U, 0x0000000000000000UL},
|
||||
{0x00D8U, 0x0000000000000000UL},
|
||||
{0x00E0U, 0x0000000000000000UL},
|
||||
{0x00E8U, 0x001100100C803401UL},
|
||||
{0x00F0U, 0x0000000000000000UL},
|
||||
{0x00F8U, 0x0000000000000000UL},
|
||||
{0x0100U, 0x0000000000000000UL},
|
||||
{0x0108U, 0x0000000000000000UL},
|
||||
{0x0110U, 0x0000000000000000UL},
|
||||
{0x0118U, 0x0000000000000000UL},
|
||||
{0x0120U, 0x0000000000000000UL},
|
||||
{0x0128U, 0x0000000000000000UL},
|
||||
{0x0130U, 0x001100100C803401UL},
|
||||
{0x0138U, 0x0000000000000000UL},
|
||||
{0x0140U, 0x0000000000000000UL},
|
||||
{0x0148U, 0x0000000000000000UL},
|
||||
{0x0150U, 0x0000000000000000UL},
|
||||
{0x0158U, 0x0000000000000000UL},
|
||||
{0x0160U, 0x0000000000000000UL},
|
||||
{0x0168U, 0x0000000000000000UL},
|
||||
{0x0170U, 0x0000000000000000UL},
|
||||
{0x0178U, 0x0000000000000000UL},
|
||||
{0x0180U, 0x0000000000000000UL},
|
||||
{0x0188U, 0x0000000000000000UL},
|
||||
{0x0190U, 0x0000000000000000UL},
|
||||
{0x0198U, 0x0000000000000000UL},
|
||||
{0x01A0U, 0x0000000000000000UL},
|
||||
{0x01A8U, 0x0000000000000000UL},
|
||||
{0x01B0U, 0x0000000000000000UL},
|
||||
{0x01B8U, 0x001100100C803401UL},
|
||||
{0x01C0U, 0x001100800C8FFC01UL},
|
||||
{0x01C8U, 0x001100800C8FFC01UL},
|
||||
{0x01D0U, 0x001100800C8FFC01UL},
|
||||
{0x01D8U, 0x001100800C8FFC01UL},
|
||||
{0x01E0U, 0x001100100C80FC01UL},
|
||||
{0x01E8U, 0x001200100C80FC01UL},
|
||||
{0x01F0U, 0x001100100C80FC01UL},
|
||||
{0x01F8U, 0x001100100C803401UL},
|
||||
{0x0200U, 0x001100100C80FC01UL},
|
||||
{0x0208U, 0x001200100C80FC01UL},
|
||||
{0x0210U, 0x001100100C80FC01UL},
|
||||
{0x0218U, 0x001100100C825801UL},
|
||||
{0x0220U, 0x001100100C825801UL},
|
||||
{0x0228U, 0x001100100C803401UL},
|
||||
{0x0230U, 0x001100100C825801UL},
|
||||
{0x0238U, 0x001100100C825801UL},
|
||||
{0x0240U, 0x001200100C8BB801UL},
|
||||
{0x0248U, 0x001100200C8FFC01UL},
|
||||
{0x0250U, 0x001200100C8BB801UL},
|
||||
{0x0258U, 0x001100200C8FFC01UL},
|
||||
{0x0260U, 0x001100100C84E401UL},
|
||||
{0x0268U, 0x0000000000000000UL},
|
||||
{0x0270U, 0x0000000000000000UL},
|
||||
{0x0278U, 0x001100100C81F401UL},
|
||||
{0x0280U, 0x001100100C803401UL},
|
||||
{0x0288U, 0x001100100C803401UL},
|
||||
{0x0290U, 0x0000000000000000UL},
|
||||
{0x0298U, 0x0000000000000000UL},
|
||||
{0x02A0U, 0x0000000000000000UL},
|
||||
{0x02A8U, 0x0000000000000000UL},
|
||||
{0x02B0U, 0x0000000000000000UL},
|
||||
{0x02B8U, 0x001100100C803401UL},
|
||||
{0x02C0U, 0x001100100C803401UL},
|
||||
{0x02C8U, 0x001100100C803401UL},
|
||||
{0x02D0U, 0x0000000000000000UL},
|
||||
{0x02D8U, 0x0000000000000000UL},
|
||||
{0x02E0U, 0x0000000000000000UL},
|
||||
{0x02E8U, 0x001100100C803401UL},
|
||||
{0x02F0U, 0x001100300C8FFC01UL},
|
||||
{0x02F8U, 0x001100500C8FFC01UL},
|
||||
{0x0300U, 0x001100100C803401UL},
|
||||
{0x0308U, 0x001100300C8FFC01UL},
|
||||
{0x0310U, 0x001100500C8FFC01UL},
|
||||
{0x0318U, 0x001200100C803401UL},
|
||||
{0x0320U, 0x001100300C8FFC01UL},
|
||||
{0x0328U, 0x001100500C8FFC01UL},
|
||||
{0x0330U, 0x001100300C8FFC01UL},
|
||||
{0x0338U, 0x001100500C8FFC01UL},
|
||||
};
|
||||
#endif
|
||||
|
||||
static void dbsc_setting(void)
|
||||
{
|
||||
uint32_t md = 0;
|
||||
|
||||
/* BUFCAM settings */
|
||||
/* DBSC_DBCAM0CNF0 not set */
|
||||
io_write_32(DBSC_DBCAM0CNF1, 0x00044218); /* dbcam0cnf1 */
|
||||
io_write_32(DBSC_DBCAM0CNF2, 0x000000F4); /* dbcam0cnf2 */
|
||||
/* DBSC_DBCAM0CNF3 not set */
|
||||
io_write_32(DBSC_DBSCHCNT0, 0x080F0037); /* dbschcnt0 */
|
||||
io_write_32(DBSC_DBSCHCNT1, 0x00001010); /* dbschcnt1 */
|
||||
io_write_32(DBSC_DBSCHSZ0, 0x00000001); /* dbschsz0 */
|
||||
io_write_32(DBSC_DBSCHRW0, 0x22421111); /* dbschrw0 */
|
||||
|
||||
md = (*((volatile uint32_t *)RST_MODEMR) & 0x000A0000) >> 17;
|
||||
|
||||
switch (md) {
|
||||
case 0x0:
|
||||
/* DDR3200 */
|
||||
io_write_32(DBSC_SCFCTST2, 0x012F1123);
|
||||
break;
|
||||
case 0x1: /* MD19=0,MD17=1 : LPDDR4-3000, 4GByte(1GByte x4) */
|
||||
/* DDR2800 */
|
||||
io_write_32(DBSC_SCFCTST2, 0x012F1123);
|
||||
break;
|
||||
case 0x4: /* MD19=1,MD17=0 : LPDDR4-2400, 4GByte(1GByte x4) */
|
||||
/* DDR2400 */
|
||||
io_write_32(DBSC_SCFCTST2, 0x012F1123);
|
||||
break;
|
||||
default: /* MD19=1,MD17=1 : LPDDR4-1600, 4GByte(1GByte x4) */
|
||||
/* DDR1600 */
|
||||
io_write_32(DBSC_SCFCTST2, 0x012F1123);
|
||||
break;
|
||||
}
|
||||
|
||||
/* QoS Settings */
|
||||
io_write_32(DBSC_DBSCHQOS_0_0, 0x0000F000);
|
||||
io_write_32(DBSC_DBSCHQOS_0_1, 0x0000E000);
|
||||
io_write_32(DBSC_DBSCHQOS_0_2, 0x00007000);
|
||||
io_write_32(DBSC_DBSCHQOS_0_3, 0x00000000);
|
||||
/* DBSC_DBSCHQOS_1_0 not set */
|
||||
/* DBSC_DBSCHQOS_1_1 not set */
|
||||
/* DBSC_DBSCHQOS_1_2 not set */
|
||||
/* DBSC_DBSCHQOS_1_3 not set */
|
||||
/* DBSC_DBSCHQOS_2_0 not set */
|
||||
/* DBSC_DBSCHQOS_2_1 not set */
|
||||
/* DBSC_DBSCHQOS_2_2 not set */
|
||||
/* DBSC_DBSCHQOS_2_3 not set */
|
||||
/* DBSC_DBSCHQOS_3_0 not set */
|
||||
/* DBSC_DBSCHQOS_3_1 not set */
|
||||
/* DBSC_DBSCHQOS_3_2 not set */
|
||||
/* DBSC_DBSCHQOS_3_3 not set */
|
||||
io_write_32(DBSC_DBSCHQOS_4_0, 0x00000E00);
|
||||
io_write_32(DBSC_DBSCHQOS_4_1, 0x00000DFF);
|
||||
io_write_32(DBSC_DBSCHQOS_4_2, 0x00000400);
|
||||
io_write_32(DBSC_DBSCHQOS_4_3, 0x00000200);
|
||||
/* DBSC_DBSCHQOS_5_0 not set */
|
||||
/* DBSC_DBSCHQOS_5_1 not set */
|
||||
/* DBSC_DBSCHQOS_5_2 not set */
|
||||
/* DBSC_DBSCHQOS_5_3 not set */
|
||||
/* DBSC_DBSCHQOS_6_0 not set */
|
||||
/* DBSC_DBSCHQOS_6_1 not set */
|
||||
/* DBSC_DBSCHQOS_6_2 not set */
|
||||
/* DBSC_DBSCHQOS_6_3 not set */
|
||||
/* DBSC_DBSCHQOS_7_0 not set */
|
||||
/* DBSC_DBSCHQOS_7_1 not set */
|
||||
/* DBSC_DBSCHQOS_7_2 not set */
|
||||
/* DBSC_DBSCHQOS_7_3 not set */
|
||||
/* DBSC_DBSCHQOS_8_0 not set */
|
||||
/* DBSC_DBSCHQOS_8_1 not set */
|
||||
/* DBSC_DBSCHQOS_8_2 not set */
|
||||
/* DBSC_DBSCHQOS_8_3 not set */
|
||||
io_write_32(DBSC_DBSCHQOS_9_0, 0x00000C00);
|
||||
io_write_32(DBSC_DBSCHQOS_9_1, 0x00000BFF);
|
||||
io_write_32(DBSC_DBSCHQOS_9_2, 0x00000400);
|
||||
io_write_32(DBSC_DBSCHQOS_9_3, 0x00000200);
|
||||
/* DBSC_DBSCHQOS_10_0 not set */
|
||||
/* DBSC_DBSCHQOS_10_1 not set */
|
||||
/* DBSC_DBSCHQOS_10_2 not set */
|
||||
/* DBSC_DBSCHQOS_10_3 not set */
|
||||
/* DBSC_DBSCHQOS_11_0 not set */
|
||||
/* DBSC_DBSCHQOS_11_1 not set */
|
||||
/* DBSC_DBSCHQOS_11_2 not set */
|
||||
/* DBSC_DBSCHQOS_11_3 not set */
|
||||
/* DBSC_DBSCHQOS_12_0 not set */
|
||||
/* DBSC_DBSCHQOS_12_1 not set */
|
||||
/* DBSC_DBSCHQOS_12_2 not set */
|
||||
/* DBSC_DBSCHQOS_12_3 not set */
|
||||
io_write_32(DBSC_DBSCHQOS_13_0, 0x00000980);
|
||||
io_write_32(DBSC_DBSCHQOS_13_1, 0x0000097F);
|
||||
io_write_32(DBSC_DBSCHQOS_13_2, 0x00000300);
|
||||
io_write_32(DBSC_DBSCHQOS_13_3, 0x00000180);
|
||||
io_write_32(DBSC_DBSCHQOS_14_0, 0x00000800);
|
||||
io_write_32(DBSC_DBSCHQOS_14_1, 0x000007FF);
|
||||
io_write_32(DBSC_DBSCHQOS_14_2, 0x00000300);
|
||||
io_write_32(DBSC_DBSCHQOS_14_3, 0x00000180);
|
||||
io_write_32(DBSC_DBSCHQOS_15_0, 0x000007D0);
|
||||
io_write_32(DBSC_DBSCHQOS_15_1, 0x000007CF);
|
||||
io_write_32(DBSC_DBSCHQOS_15_2, 0x000005D0);
|
||||
io_write_32(DBSC_DBSCHQOS_15_3, 0x000003D0);
|
||||
}
|
||||
|
||||
void qos_init_h3_v11(void)
|
||||
{
|
||||
dbsc_setting();
|
||||
|
||||
/* DRAM Split Address mapping */
|
||||
#if (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH) || \
|
||||
(RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO)
|
||||
NOTICE("BL2: DRAM Split is 4ch\n");
|
||||
io_write_32(AXI_ADSPLCR0, ADSPLCR0_ADRMODE_DEFAULT
|
||||
| ADSPLCR0_SPLITSEL(0xFFU)
|
||||
| ADSPLCR0_AREA(0x1BU)
|
||||
| ADSPLCR0_SWP);
|
||||
io_write_32(AXI_ADSPLCR1, 0x00000000U);
|
||||
io_write_32(AXI_ADSPLCR2, 0xA8A90000U);
|
||||
io_write_32(AXI_ADSPLCR3, 0x00000000U);
|
||||
#elif RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH
|
||||
NOTICE("BL2: DRAM Split is 2ch\n");
|
||||
io_write_32(AXI_ADSPLCR0, 0x00000000U);
|
||||
io_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT
|
||||
| ADSPLCR0_SPLITSEL(0xFFU)
|
||||
| ADSPLCR0_AREA(0x1BU)
|
||||
| ADSPLCR0_SWP);
|
||||
io_write_32(AXI_ADSPLCR2, 0x00000000U);
|
||||
io_write_32(AXI_ADSPLCR3, 0x00000000U);
|
||||
#else
|
||||
NOTICE("BL2: DRAM Split is OFF\n");
|
||||
#endif
|
||||
|
||||
#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
|
||||
#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
|
||||
NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
|
||||
#endif
|
||||
|
||||
/* AR Cache setting */
|
||||
io_write_32(0xE67D1000U, 0x00000100U);
|
||||
io_write_32(0xE67D1008U, 0x00000100U);
|
||||
|
||||
/* Resource Alloc setting */
|
||||
#if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH
|
||||
io_write_32(RALLOC_RAS, 0x00000020U);
|
||||
#else
|
||||
io_write_32(RALLOC_RAS, 0x00000040U);
|
||||
#endif
|
||||
io_write_32(RALLOC_FIXTH, 0x000F0005U);
|
||||
io_write_32(RALLOC_REGGD, 0x00000000U);
|
||||
#if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH
|
||||
io_write_64(RALLOC_DANN, 0x0101010102020201UL);
|
||||
io_write_32(RALLOC_DANT, 0x00181008U);
|
||||
#else
|
||||
io_write_64(RALLOC_DANN, 0x0101000004040401UL);
|
||||
io_write_32(RALLOC_DANT, 0x003C2010U);
|
||||
#endif
|
||||
io_write_32(RALLOC_EC, 0x00080001U); /* need for H3 v1.* */
|
||||
io_write_64(RALLOC_EMS, 0x0000000000000000UL);
|
||||
io_write_32(RALLOC_INSFC, 0xC7840001U);
|
||||
io_write_32(RALLOC_BERR, 0x00000000U);
|
||||
io_write_32(RALLOC_RACNT0, 0x00000000U);
|
||||
|
||||
/* MSTAT setting */
|
||||
io_write_32(MSTAT_SL_INIT,
|
||||
SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT | SL_INIT_SSLOTCLK);
|
||||
io_write_32(MSTAT_REF_ARS, 0x00330000U);
|
||||
|
||||
/* MSTAT SRAM setting */
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
|
||||
io_write_64(MSTAT_FIX_QOS_BANK0 + mstat_fix[i].addr,
|
||||
mstat_fix[i].value);
|
||||
io_write_64(MSTAT_FIX_QOS_BANK1 + mstat_fix[i].addr,
|
||||
mstat_fix[i].value);
|
||||
}
|
||||
for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
|
||||
io_write_64(MSTAT_BE_QOS_BANK0 + mstat_be[i].addr,
|
||||
mstat_be[i].value);
|
||||
io_write_64(MSTAT_BE_QOS_BANK1 + mstat_be[i].addr,
|
||||
mstat_be[i].value);
|
||||
}
|
||||
}
|
||||
|
||||
/* 3DG bus Leaf setting */
|
||||
io_write_32(0xFD820808U, 0x00001234U);
|
||||
io_write_32(0xFD820800U, 0x0000003FU);
|
||||
io_write_32(0xFD821800U, 0x0000003FU);
|
||||
io_write_32(0xFD822800U, 0x0000003FU);
|
||||
io_write_32(0xFD823800U, 0x0000003FU);
|
||||
io_write_32(0xFD824800U, 0x0000003FU);
|
||||
io_write_32(0xFD825800U, 0x0000003FU);
|
||||
io_write_32(0xFD826800U, 0x0000003FU);
|
||||
io_write_32(0xFD827800U, 0x0000003FU);
|
||||
|
||||
/* VIO bus Leaf setting */
|
||||
io_write_32(0xFEB89800, 0x00000001U);
|
||||
io_write_32(0xFEB8A800, 0x00000001U);
|
||||
io_write_32(0xFEB8B800, 0x00000001U);
|
||||
io_write_32(0xFEB8C800, 0x00000001U);
|
||||
|
||||
/* HSC bus Leaf setting */
|
||||
io_write_32(0xE6430800, 0x00000001U);
|
||||
io_write_32(0xE6431800, 0x00000001U);
|
||||
io_write_32(0xE6432800, 0x00000001U);
|
||||
io_write_32(0xE6433800, 0x00000001U);
|
||||
|
||||
/* MP bus Leaf setting */
|
||||
io_write_32(0xEC620800, 0x00000001U);
|
||||
io_write_32(0xEC621800, 0x00000001U);
|
||||
|
||||
/* PERIE bus Leaf setting */
|
||||
io_write_32(0xE7760800, 0x00000001U);
|
||||
io_write_32(0xE7768800, 0x00000001U);
|
||||
|
||||
/* PERIW bus Leaf setting */
|
||||
io_write_32(0xE6760800, 0x00000001U);
|
||||
io_write_32(0xE6768800, 0x00000001U);
|
||||
|
||||
/* RT bus Leaf setting */
|
||||
io_write_32(0xFFC50800, 0x00000001U);
|
||||
io_write_32(0xFFC51800, 0x00000001U);
|
||||
|
||||
/* CCI bus Leaf setting */
|
||||
{
|
||||
|
||||
uint32_t modemr = io_read_32(RCAR_MODEMR);
|
||||
|
||||
modemr &= MODEMR_BOOT_CPU_MASK;
|
||||
|
||||
if ((modemr == MODEMR_BOOT_CPU_CA57) ||
|
||||
(modemr == MODEMR_BOOT_CPU_CA53)) {
|
||||
io_write_32(0xF1300800, 0x00000001U);
|
||||
io_write_32(0xF1340800, 0x00000001U);
|
||||
io_write_32(0xF1380800, 0x00000001U);
|
||||
io_write_32(0xF13C0800, 0x00000001U);
|
||||
}
|
||||
}
|
||||
|
||||
/* Resource Alloc start */
|
||||
io_write_32(RALLOC_RAEN, 0x00000001U);
|
||||
|
||||
/* MSTAT start */
|
||||
io_write_32(MSTAT_STATQC, 0x00000001U);
|
||||
#else
|
||||
NOTICE("BL2: QoS is None\n");
|
||||
|
||||
/* Resource Alloc setting */
|
||||
io_write_32(RALLOC_EC, 0x00080001U); /* need for H3 v1.* */
|
||||
#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
|
||||
}
|
12
drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v11.h
Normal file
12
drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v11.h
Normal file
|
@ -0,0 +1,12 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef QOS_INIT_H_H3_V11__
|
||||
#define QOS_INIT_H_H3_V11__
|
||||
|
||||
void qos_init_h3_v11(void);
|
||||
|
||||
#endif /* QOS_INIT_H_H3_V11__ */
|
255
drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20.c
Normal file
255
drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20.c
Normal file
|
@ -0,0 +1,255 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <debug.h>
|
||||
#include "../qos_common.h"
|
||||
#include "../qos_reg.h"
|
||||
#include "qos_init_h3_v20.h"
|
||||
|
||||
#define RCAR_QOS_VERSION "rev.0.19"
|
||||
|
||||
#define QOSWT_TIME_BANK0 (20000000U) /* unit:ns */
|
||||
|
||||
#define QOSWT_WTEN_ENABLE (0x1U)
|
||||
|
||||
#define QOSCTRL_REF_ARS_ARBSTOPCYCLE_H3_20 (SL_INIT_SSLOTCLK_H3_20 - 0x5U)
|
||||
|
||||
#define OSWT_WTREF_SLOT0_EN_REQ1_SLOT (3U)
|
||||
#define OSWT_WTREF_SLOT0_EN_REQ2_SLOT (9U)
|
||||
#define QOSWT_WTREF_SLOT0_EN ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
|
||||
#define QOSWT_WTREF_SLOT1_EN ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
|
||||
|
||||
#define QOSWT_WTSET0_REQ_SSLOT0 (5U)
|
||||
#define WT_BASE_SUB_SLOT_NUM0 (12U)
|
||||
#define QOSWT_WTSET0_PERIOD0_H3_20 ((QOSWT_TIME_BANK0/QOSWT_WTSET0_CYCLE_H3_20)-1U)
|
||||
#define QOSWT_WTSET0_SSLOT0 (QOSWT_WTSET0_REQ_SSLOT0 -1U)
|
||||
#define QOSWT_WTSET0_SLOTSLOT0 (WT_BASE_SUB_SLOT_NUM0 -1U)
|
||||
|
||||
#define QOSWT_WTSET1_PERIOD1_H3_20 ((QOSWT_TIME_BANK0/QOSWT_WTSET0_CYCLE_H3_20)-1U)
|
||||
#define QOSWT_WTSET1_SSLOT1 (QOSWT_WTSET0_REQ_SSLOT0 -1U)
|
||||
#define QOSWT_WTSET1_SLOTSLOT1 (WT_BASE_SUB_SLOT_NUM0 -1U)
|
||||
|
||||
#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
|
||||
|
||||
#if RCAR_REF_INT == RCAR_REF_DEFAULT
|
||||
#include "qos_init_h3_v20_mstat195.h"
|
||||
#else
|
||||
#include "qos_init_h3_v20_mstat390.h"
|
||||
#endif
|
||||
|
||||
#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
|
||||
|
||||
#if RCAR_REF_INT == RCAR_REF_DEFAULT
|
||||
#include "qos_init_h3_v20_qoswt195.h"
|
||||
#else
|
||||
#include "qos_init_h3_v20_qoswt390.h"
|
||||
#endif
|
||||
|
||||
#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
|
||||
|
||||
#endif
|
||||
|
||||
static void dbsc_setting(void)
|
||||
{
|
||||
uint32_t md = 0;
|
||||
|
||||
/* Register write enable */
|
||||
io_write_32(DBSC_DBSYSCNT0, 0x00001234U);
|
||||
|
||||
/* BUFCAM settings */
|
||||
io_write_32(DBSC_DBCAM0CNF1, 0x00043218U); /* dbcam0cnf1 */
|
||||
io_write_32(DBSC_DBCAM0CNF2, 0x000000F4U); /* dbcam0cnf2 */
|
||||
io_write_32(DBSC_DBCAM0CNF3, 0x00000000U); /* dbcam0cnf3 */
|
||||
io_write_32(DBSC_DBSCHCNT0, 0x000F0037U); /* dbschcnt0 */
|
||||
io_write_32(DBSC_DBSCHSZ0, 0x00000001U); /* dbschsz0 */
|
||||
io_write_32(DBSC_DBSCHRW0, 0x22421111U); /* dbschrw0 */
|
||||
|
||||
md = (*((volatile uint32_t *)RST_MODEMR) & 0x000A0000) >> 17;
|
||||
|
||||
switch (md) {
|
||||
case 0x0:
|
||||
/* DDR3200 */
|
||||
io_write_32(DBSC_SCFCTST2, 0x012F1123U);
|
||||
break;
|
||||
case 0x1: /* MD19=0,MD17=1 : LPDDR4-3000, 4GByte(1GByte x4) */
|
||||
/* DDR2800 */
|
||||
io_write_32(DBSC_SCFCTST2, 0x012F1123U);
|
||||
break;
|
||||
case 0x4: /* MD19=1,MD17=0 : LPDDR4-2400, 4GByte(1GByte x4) */
|
||||
/* DDR2400 */
|
||||
io_write_32(DBSC_SCFCTST2, 0x012F1123U);
|
||||
break;
|
||||
default: /* MD19=1,MD17=1 : LPDDR4-1600, 4GByte(1GByte x4) */
|
||||
/* DDR1600 */
|
||||
io_write_32(DBSC_SCFCTST2, 0x012F1123U);
|
||||
break;
|
||||
}
|
||||
|
||||
/* QoS Settings */
|
||||
io_write_32(DBSC_DBSCHQOS00, 0x00000F00U);
|
||||
io_write_32(DBSC_DBSCHQOS01, 0x00000B00U);
|
||||
io_write_32(DBSC_DBSCHQOS02, 0x00000000U);
|
||||
io_write_32(DBSC_DBSCHQOS03, 0x00000000U);
|
||||
io_write_32(DBSC_DBSCHQOS40, 0x00000300U);
|
||||
io_write_32(DBSC_DBSCHQOS41, 0x000002F0U);
|
||||
io_write_32(DBSC_DBSCHQOS42, 0x00000200U);
|
||||
io_write_32(DBSC_DBSCHQOS43, 0x00000100U);
|
||||
io_write_32(DBSC_DBSCHQOS90, 0x00000100U);
|
||||
io_write_32(DBSC_DBSCHQOS91, 0x000000F0U);
|
||||
io_write_32(DBSC_DBSCHQOS92, 0x000000A0U);
|
||||
io_write_32(DBSC_DBSCHQOS93, 0x00000040U);
|
||||
io_write_32(DBSC_DBSCHQOS120, 0x00000040U);
|
||||
io_write_32(DBSC_DBSCHQOS121, 0x00000030U);
|
||||
io_write_32(DBSC_DBSCHQOS122, 0x00000020U);
|
||||
io_write_32(DBSC_DBSCHQOS123, 0x00000010U);
|
||||
io_write_32(DBSC_DBSCHQOS130, 0x00000100U);
|
||||
io_write_32(DBSC_DBSCHQOS131, 0x000000F0U);
|
||||
io_write_32(DBSC_DBSCHQOS132, 0x000000A0U);
|
||||
io_write_32(DBSC_DBSCHQOS133, 0x00000040U);
|
||||
io_write_32(DBSC_DBSCHQOS140, 0x000000C0U);
|
||||
io_write_32(DBSC_DBSCHQOS141, 0x000000B0U);
|
||||
io_write_32(DBSC_DBSCHQOS142, 0x00000080U);
|
||||
io_write_32(DBSC_DBSCHQOS143, 0x00000040U);
|
||||
io_write_32(DBSC_DBSCHQOS150, 0x00000040U);
|
||||
io_write_32(DBSC_DBSCHQOS151, 0x00000030U);
|
||||
io_write_32(DBSC_DBSCHQOS152, 0x00000020U);
|
||||
io_write_32(DBSC_DBSCHQOS153, 0x00000010U);
|
||||
|
||||
/* Register write protect */
|
||||
io_write_32(DBSC_DBSYSCNT0, 0x00000000U);
|
||||
}
|
||||
|
||||
void qos_init_h3_v20(void)
|
||||
{
|
||||
dbsc_setting();
|
||||
|
||||
/* DRAM Split Address mapping */
|
||||
#if (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH) || \
|
||||
(RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO)
|
||||
NOTICE("BL2: DRAM Split is 4ch\n");
|
||||
io_write_32(AXI_ADSPLCR0, ADSPLCR0_ADRMODE_DEFAULT
|
||||
| ADSPLCR0_SPLITSEL(0xFFU)
|
||||
| ADSPLCR0_AREA(0x1BU)
|
||||
| ADSPLCR0_SWP);
|
||||
io_write_32(AXI_ADSPLCR1, 0x00000000U);
|
||||
io_write_32(AXI_ADSPLCR2, 0x00001054U);
|
||||
io_write_32(AXI_ADSPLCR3, 0x00000000U);
|
||||
#elif RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH
|
||||
NOTICE("BL2: DRAM Split is 2ch\n");
|
||||
io_write_32(AXI_ADSPLCR0, 0x00000000U);
|
||||
io_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT
|
||||
| ADSPLCR0_SPLITSEL(0xFFU)
|
||||
| ADSPLCR0_AREA(0x1BU)
|
||||
| ADSPLCR0_SWP);
|
||||
io_write_32(AXI_ADSPLCR2, 0x00001004U);
|
||||
io_write_32(AXI_ADSPLCR3, 0x00000000U);
|
||||
#else
|
||||
NOTICE("BL2: DRAM Split is OFF\n");
|
||||
#endif
|
||||
|
||||
#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
|
||||
#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
|
||||
NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
|
||||
#endif
|
||||
|
||||
#if RCAR_REF_INT == RCAR_REF_DEFAULT
|
||||
NOTICE("BL2: DRAM refresh interval 1.95 usec\n");
|
||||
#else
|
||||
NOTICE("BL2: DRAM refresh interval 3.9 usec\n");
|
||||
#endif
|
||||
|
||||
#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
|
||||
NOTICE("BL2: Periodic Write DQ Training\n");
|
||||
#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
|
||||
|
||||
io_write_32(QOSCTRL_RAS, 0x00000044U);
|
||||
io_write_64(QOSCTRL_DANN, 0x0404010002020201UL);
|
||||
io_write_32(QOSCTRL_DANT, 0x0020100AU);
|
||||
io_write_32(QOSCTRL_INSFC, 0x06330001U);
|
||||
io_write_32(QOSCTRL_RACNT0, 0x00010003U);
|
||||
|
||||
/* GPU Boost Mode */
|
||||
io_write_32(QOSCTRL_STATGEN0, 0x00000001U);
|
||||
|
||||
io_write_32(QOSCTRL_SL_INIT,
|
||||
SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT |
|
||||
SL_INIT_SSLOTCLK_H3_20);
|
||||
#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
|
||||
io_write_32(QOSCTRL_REF_ARS,
|
||||
((QOSCTRL_REF_ARS_ARBSTOPCYCLE_H3_20 << 16)));
|
||||
#else
|
||||
io_write_32(QOSCTRL_REF_ARS, 0x00330000U);
|
||||
#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
|
||||
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
|
||||
io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
|
||||
io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
|
||||
}
|
||||
for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
|
||||
io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
|
||||
io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
|
||||
}
|
||||
#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
|
||||
for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) {
|
||||
io_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8,
|
||||
qoswt_fix[i]);
|
||||
io_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8,
|
||||
qoswt_fix[i]);
|
||||
}
|
||||
for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) {
|
||||
io_write_64(QOSWT_BE_WTQOS_BANK0 + i * 8, qoswt_be[i]);
|
||||
io_write_64(QOSWT_BE_WTQOS_BANK1 + i * 8, qoswt_be[i]);
|
||||
}
|
||||
#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
|
||||
}
|
||||
|
||||
/* 3DG bus Leaf setting */
|
||||
io_write_32(GPU_ACT0, 0x00000000U);
|
||||
io_write_32(GPU_ACT1, 0x00000000U);
|
||||
io_write_32(GPU_ACT2, 0x00000000U);
|
||||
io_write_32(GPU_ACT3, 0x00000000U);
|
||||
io_write_32(GPU_ACT4, 0x00000000U);
|
||||
io_write_32(GPU_ACT5, 0x00000000U);
|
||||
io_write_32(GPU_ACT6, 0x00000000U);
|
||||
io_write_32(GPU_ACT7, 0x00000000U);
|
||||
|
||||
/* RT bus Leaf setting */
|
||||
io_write_32(RT_ACT0, 0x00000000U);
|
||||
io_write_32(RT_ACT1, 0x00000000U);
|
||||
|
||||
/* CCI bus Leaf setting */
|
||||
io_write_32(CPU_ACT0, 0x00000003U);
|
||||
io_write_32(CPU_ACT1, 0x00000003U);
|
||||
io_write_32(CPU_ACT2, 0x00000003U);
|
||||
io_write_32(CPU_ACT3, 0x00000003U);
|
||||
|
||||
io_write_32(QOSCTRL_RAEN, 0x00000001U);
|
||||
|
||||
#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
|
||||
/* re-write training setting */
|
||||
io_write_32(QOSWT_WTREF,
|
||||
((QOSWT_WTREF_SLOT1_EN << 16) | QOSWT_WTREF_SLOT0_EN));
|
||||
io_write_32(QOSWT_WTSET0,
|
||||
((QOSWT_WTSET0_PERIOD0_H3_20 << 16) |
|
||||
(QOSWT_WTSET0_SSLOT0 << 8) | QOSWT_WTSET0_SLOTSLOT0));
|
||||
io_write_32(QOSWT_WTSET1,
|
||||
((QOSWT_WTSET1_PERIOD1_H3_20 << 16) |
|
||||
(QOSWT_WTSET1_SSLOT1 << 8) | QOSWT_WTSET1_SLOTSLOT1));
|
||||
|
||||
io_write_32(QOSWT_WTEN, QOSWT_WTEN_ENABLE);
|
||||
#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
|
||||
|
||||
io_write_32(QOSCTRL_STATQC, 0x00000001U);
|
||||
#else
|
||||
NOTICE("BL2: QoS is None\n");
|
||||
|
||||
io_write_32(QOSCTRL_RAEN, 0x00000001U);
|
||||
#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
|
||||
}
|
12
drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20.h
Normal file
12
drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20.h
Normal file
|
@ -0,0 +1,12 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef QOS_INIT_H_H3_V20__
|
||||
#define QOS_INIT_H_H3_V20__
|
||||
|
||||
void qos_init_h3_v20(void);
|
||||
|
||||
#endif /* QOS_INIT_H_H3_V20__ */
|
231
drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20_mstat195.h
Normal file
231
drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20_mstat195.h
Normal file
|
@ -0,0 +1,231 @@
|
|||
/*
|
||||
* Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
static uint64_t mstat_fix[] = {
|
||||
/* 0x0000, */ 0x0000000000000000UL,
|
||||
/* 0x0008, */ 0x0000000000000000UL,
|
||||
/* 0x0010, */ 0x0000000000000000UL,
|
||||
/* 0x0018, */ 0x0000000000000000UL,
|
||||
/* 0x0020, */ 0x0000000000000000UL,
|
||||
/* 0x0028, */ 0x0000000000000000UL,
|
||||
/* 0x0030, */ 0x001004040000FFFFUL,
|
||||
/* 0x0038, */ 0x001008070000FFFFUL,
|
||||
/* 0x0040, */ 0x001424110000FFFFUL,
|
||||
/* 0x0048, */ 0x0000000000000000UL,
|
||||
/* 0x0050, */ 0x001404010000FFFFUL,
|
||||
/* 0x0058, */ 0x001410100000FFFFUL,
|
||||
/* 0x0060, */ 0x0014100D0000FFFFUL,
|
||||
/* 0x0068, */ 0x0000000000000000UL,
|
||||
/* 0x0070, */ 0x001404010000FFFFUL,
|
||||
/* 0x0078, */ 0x001008070000FFFFUL,
|
||||
/* 0x0080, */ 0x0000000000000000UL,
|
||||
/* 0x0088, */ 0x001424110000FFFFUL,
|
||||
/* 0x0090, */ 0x0014100D0000FFFFUL,
|
||||
/* 0x0098, */ 0x0000000000000000UL,
|
||||
/* 0x00a0, */ 0x000C04020000FFFFUL,
|
||||
/* 0x00a8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x00b0, */ 0x000C04010000FFFFUL,
|
||||
/* 0x00b8, */ 0x0000000000000000UL,
|
||||
/* 0x00c0, */ 0x000C04020000FFFFUL,
|
||||
/* 0x00c8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x00d0, */ 0x000C04010000FFFFUL,
|
||||
/* 0x00d8, */ 0x001024090000FFFFUL,
|
||||
/* 0x00e0, */ 0x00100C090000FFFFUL,
|
||||
/* 0x00e8, */ 0x0000000000000000UL,
|
||||
/* 0x00f0, */ 0x001024090000FFFFUL,
|
||||
/* 0x00f8, */ 0x000C08070000FFFFUL,
|
||||
/* 0x0100, */ 0x0000000000000000UL,
|
||||
/* 0x0108, */ 0x0000000000000000UL,
|
||||
/* 0x0110, */ 0x00100C090000FFFFUL,
|
||||
/* 0x0118, */ 0x000C10100000FFFFUL,
|
||||
/* 0x0120, */ 0x000C10100000FFFFUL,
|
||||
/* 0x0128, */ 0x0000000000000000UL,
|
||||
/* 0x0130, */ 0x0000000000000000UL,
|
||||
/* 0x0138, */ 0x00100C0B0000FFFFUL,
|
||||
/* 0x0140, */ 0x00100C0B0000FFFFUL,
|
||||
/* 0x0148, */ 0x0000000000000000UL,
|
||||
/* 0x0150, */ 0x0010100D0000FFFFUL,
|
||||
/* 0x0158, */ 0x0010100D0000FFFFUL,
|
||||
/* 0x0160, */ 0x00100C0B0000FFFFUL,
|
||||
/* 0x0168, */ 0x00100C0B0000FFFFUL,
|
||||
/* 0x0170, */ 0x0000000000000000UL,
|
||||
/* 0x0178, */ 0x001008060000FFFFUL,
|
||||
/* 0x0180, */ 0x001008060000FFFFUL,
|
||||
/* 0x0188, */ 0x0000000000000000UL,
|
||||
/* 0x0190, */ 0x00102C2C0000FFFFUL,
|
||||
/* 0x0198, */ 0x00102C2C0000FFFFUL,
|
||||
/* 0x01a0, */ 0x00100C0B0000FFFFUL,
|
||||
/* 0x01a8, */ 0x00100C0B0000FFFFUL,
|
||||
/* 0x01b0, */ 0x0000000000000000UL,
|
||||
/* 0x01b8, */ 0x0000000000000000UL,
|
||||
/* 0x01c0, */ 0x000C04010000FFFFUL,
|
||||
/* 0x01c8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x01d0, */ 0x000C04010000FFFFUL,
|
||||
/* 0x01d8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x01e0, */ 0x0000000000000000UL,
|
||||
/* 0x01e8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x01f0, */ 0x000C04010000FFFFUL,
|
||||
/* 0x01f8, */ 0x0000000000000000UL,
|
||||
/* 0x0200, */ 0x0000000000000000UL,
|
||||
/* 0x0208, */ 0x000C04010000FFFFUL,
|
||||
/* 0x0210, */ 0x000C04010000FFFFUL,
|
||||
/* 0x0218, */ 0x0000000000000000UL,
|
||||
/* 0x0220, */ 0x0000000000000000UL,
|
||||
/* 0x0228, */ 0x0000000000000000UL,
|
||||
/* 0x0230, */ 0x0000000000000000UL,
|
||||
/* 0x0238, */ 0x0000000000000000UL,
|
||||
/* 0x0240, */ 0x0000000000000000UL,
|
||||
/* 0x0248, */ 0x0000000000000000UL,
|
||||
/* 0x0250, */ 0x0000000000000000UL,
|
||||
/* 0x0258, */ 0x0000000000000000UL,
|
||||
/* 0x0260, */ 0x000C08020000FFFFUL,
|
||||
/* 0x0268, */ 0x001408010000FFFFUL,
|
||||
/* 0x0270, */ 0x001404010000FFFFUL,
|
||||
/* 0x0278, */ 0x000C04010000FFFFUL,
|
||||
/* 0x0280, */ 0x0000000000000000UL,
|
||||
/* 0x0288, */ 0x0000000000000000UL,
|
||||
/* 0x0290, */ 0x001408010000FFFFUL,
|
||||
/* 0x0298, */ 0x001404010000FFFFUL,
|
||||
/* 0x02a0, */ 0x000C04010000FFFFUL,
|
||||
/* 0x02a8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x02b0, */ 0x001408010000FFFFUL,
|
||||
/* 0x02b8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x02c0, */ 0x0000000000000000UL,
|
||||
/* 0x02c8, */ 0x0000000000000000UL,
|
||||
/* 0x02d0, */ 0x000C04010000FFFFUL,
|
||||
/* 0x02d8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x02e0, */ 0x001408010000FFFFUL,
|
||||
/* 0x02e8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x02f0, */ 0x0000000000000000UL,
|
||||
/* 0x02f8, */ 0x0000000000000000UL,
|
||||
/* 0x0300, */ 0x0000000000000000UL,
|
||||
/* 0x0308, */ 0x0000000000000000UL,
|
||||
/* 0x0310, */ 0x0000000000000000UL,
|
||||
/* 0x0318, */ 0x0000000000000000UL,
|
||||
/* 0x0320, */ 0x0000000000000000UL,
|
||||
/* 0x0328, */ 0x0000000000000000UL,
|
||||
/* 0x0330, */ 0x0000000000000000UL,
|
||||
/* 0x0338, */ 0x0000000000000000UL,
|
||||
/* 0x0340, */ 0x0000000000000000UL,
|
||||
/* 0x0348, */ 0x0000000000000000UL,
|
||||
/* 0x0350, */ 0x0000000000000000UL,
|
||||
/* 0x0358, */ 0x0000000000000000UL,
|
||||
/* 0x0360, */ 0x0000000000000000UL,
|
||||
/* 0x0368, */ 0x0000000000000000UL,
|
||||
};
|
||||
|
||||
static uint64_t mstat_be[] = {
|
||||
/* 0x0000, */ 0x001200200BDFFC01UL,
|
||||
/* 0x0008, */ 0x001200200BDFFC01UL,
|
||||
/* 0x0010, */ 0x001200200BDFFC01UL,
|
||||
/* 0x0018, */ 0x001200200BDFFC01UL,
|
||||
/* 0x0020, */ 0x0000000000000000UL,
|
||||
/* 0x0028, */ 0x001200100BD0FC01UL,
|
||||
/* 0x0030, */ 0x0000000000000000UL,
|
||||
/* 0x0038, */ 0x0000000000000000UL,
|
||||
/* 0x0040, */ 0x0000000000000000UL,
|
||||
/* 0x0048, */ 0x0000000000000000UL,
|
||||
/* 0x0050, */ 0x0000000000000000UL,
|
||||
/* 0x0058, */ 0x0000000000000000UL,
|
||||
/* 0x0060, */ 0x0000000000000000UL,
|
||||
/* 0x0068, */ 0x0000000000000000UL,
|
||||
/* 0x0070, */ 0x0000000000000000UL,
|
||||
/* 0x0078, */ 0x0000000000000000UL,
|
||||
/* 0x0080, */ 0x0000000000000000UL,
|
||||
/* 0x0088, */ 0x0000000000000000UL,
|
||||
/* 0x0090, */ 0x0000000000000000UL,
|
||||
/* 0x0098, */ 0x0000000000000000UL,
|
||||
/* 0x00a0, */ 0x0000000000000000UL,
|
||||
/* 0x00a8, */ 0x0000000000000000UL,
|
||||
/* 0x00b0, */ 0x0000000000000000UL,
|
||||
/* 0x00b8, */ 0x0000000000000000UL,
|
||||
/* 0x00c0, */ 0x0000000000000000UL,
|
||||
/* 0x00c8, */ 0x0000000000000000UL,
|
||||
/* 0x00d0, */ 0x0000000000000000UL,
|
||||
/* 0x00d8, */ 0x0000000000000000UL,
|
||||
/* 0x00e0, */ 0x0000000000000000UL,
|
||||
/* 0x00e8, */ 0x0000000000000000UL,
|
||||
/* 0x00f0, */ 0x0000000000000000UL,
|
||||
/* 0x00f8, */ 0x0000000000000000UL,
|
||||
/* 0x0100, */ 0x0000000000000000UL,
|
||||
/* 0x0108, */ 0x0000000000000000UL,
|
||||
/* 0x0110, */ 0x0000000000000000UL,
|
||||
/* 0x0118, */ 0x0000000000000000UL,
|
||||
/* 0x0120, */ 0x0000000000000000UL,
|
||||
/* 0x0128, */ 0x0000000000000000UL,
|
||||
/* 0x0130, */ 0x0000000000000000UL,
|
||||
/* 0x0138, */ 0x0000000000000000UL,
|
||||
/* 0x0140, */ 0x0000000000000000UL,
|
||||
/* 0x0148, */ 0x0000000000000000UL,
|
||||
/* 0x0150, */ 0x0000000000000000UL,
|
||||
/* 0x0158, */ 0x0000000000000000UL,
|
||||
/* 0x0160, */ 0x0000000000000000UL,
|
||||
/* 0x0168, */ 0x0000000000000000UL,
|
||||
/* 0x0170, */ 0x0000000000000000UL,
|
||||
/* 0x0178, */ 0x0000000000000000UL,
|
||||
/* 0x0180, */ 0x0000000000000000UL,
|
||||
/* 0x0188, */ 0x0000000000000000UL,
|
||||
/* 0x0190, */ 0x0000000000000000UL,
|
||||
/* 0x0198, */ 0x0000000000000000UL,
|
||||
/* 0x01a0, */ 0x0000000000000000UL,
|
||||
/* 0x01a8, */ 0x0000000000000000UL,
|
||||
/* 0x01b0, */ 0x0000000000000000UL,
|
||||
/* 0x01b8, */ 0x0000000000000000UL,
|
||||
/* 0x01c0, */ 0x002100700BDFFC01UL,
|
||||
/* 0x01c8, */ 0x002100700BDFFC01UL,
|
||||
/* 0x01d0, */ 0x002100700BDFFC01UL,
|
||||
/* 0x01d8, */ 0x002100700BDFFC01UL,
|
||||
/* 0x01e0, */ 0x0000000000000000UL,
|
||||
/* 0x01e8, */ 0x0000000000000000UL,
|
||||
/* 0x01f0, */ 0x002100200BDFFC01UL,
|
||||
/* 0x01f8, */ 0x0000000000000000UL,
|
||||
/* 0x0200, */ 0x0000000000000000UL,
|
||||
/* 0x0208, */ 0x0000000000000000UL,
|
||||
/* 0x0210, */ 0x002100200BDFFC01UL,
|
||||
/* 0x0218, */ 0x001100200BDFFC01UL,
|
||||
/* 0x0220, */ 0x001100200BDFFC01UL,
|
||||
/* 0x0228, */ 0x0000000000000000UL,
|
||||
/* 0x0230, */ 0x001100200BDFFC01UL,
|
||||
/* 0x0238, */ 0x001100200BDFFC01UL,
|
||||
/* 0x0240, */ 0x001200200BDFFC01UL,
|
||||
/* 0x0248, */ 0x001100200BDFFC01UL,
|
||||
/* 0x0250, */ 0x001200200BDFFC01UL,
|
||||
/* 0x0258, */ 0x001100200BDFFC01UL,
|
||||
/* 0x0260, */ 0x0000000000000000UL,
|
||||
/* 0x0268, */ 0x0000000000000000UL,
|
||||
/* 0x0270, */ 0x0000000000000000UL,
|
||||
/* 0x0278, */ 0x0000000000000000UL,
|
||||
/* 0x0280, */ 0x0000000000000000UL,
|
||||
/* 0x0288, */ 0x0000000000000000UL,
|
||||
/* 0x0290, */ 0x0000000000000000UL,
|
||||
/* 0x0298, */ 0x0000000000000000UL,
|
||||
/* 0x02a0, */ 0x0000000000000000UL,
|
||||
/* 0x02a8, */ 0x0000000000000000UL,
|
||||
/* 0x02b0, */ 0x0000000000000000UL,
|
||||
/* 0x02b8, */ 0x0000000000000000UL,
|
||||
/* 0x02c0, */ 0x0000000000000000UL,
|
||||
/* 0x02c8, */ 0x0000000000000000UL,
|
||||
/* 0x02d0, */ 0x0000000000000000UL,
|
||||
/* 0x02d8, */ 0x0000000000000000UL,
|
||||
/* 0x02e0, */ 0x0000000000000000UL,
|
||||
/* 0x02e8, */ 0x0000000000000000UL,
|
||||
/* 0x02f0, */ 0x001100400BDFFC01UL,
|
||||
/* 0x02f8, */ 0x001100600BDFFC01UL,
|
||||
/* 0x0300, */ 0x0000000000000000UL,
|
||||
/* 0x0308, */ 0x001100400BDFFC01UL,
|
||||
/* 0x0310, */ 0x001100600BDFFC01UL,
|
||||
/* 0x0318, */ 0x001200100BD03401UL,
|
||||
/* 0x0320, */ 0x001100400BDFFC01UL,
|
||||
/* 0x0328, */ 0x001100600BDFFC01UL,
|
||||
/* 0x0330, */ 0x001100400BDFFC01UL,
|
||||
/* 0x0338, */ 0x001100600BDFFC01UL,
|
||||
/* 0x0340, */ 0x0000000000000000UL,
|
||||
/* 0x0348, */ 0x0000000000000000UL,
|
||||
/* 0x0350, */ 0x0000000000000000UL,
|
||||
/* 0x0358, */ 0x0000000000000000UL,
|
||||
/* 0x0360, */ 0x0000000000000000UL,
|
||||
/* 0x0368, */ 0x001200100BD0FC01UL,
|
||||
};
|
231
drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20_mstat390.h
Normal file
231
drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20_mstat390.h
Normal file
|
@ -0,0 +1,231 @@
|
|||
/*
|
||||
* Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
static uint64_t mstat_fix[] = {
|
||||
/* 0x0000, */ 0x0000000000000000UL,
|
||||
/* 0x0008, */ 0x0000000000000000UL,
|
||||
/* 0x0010, */ 0x0000000000000000UL,
|
||||
/* 0x0018, */ 0x0000000000000000UL,
|
||||
/* 0x0020, */ 0x0000000000000000UL,
|
||||
/* 0x0028, */ 0x0000000000000000UL,
|
||||
/* 0x0030, */ 0x001008070000FFFFUL,
|
||||
/* 0x0038, */ 0x0010100D0000FFFFUL,
|
||||
/* 0x0040, */ 0x001444210000FFFFUL,
|
||||
/* 0x0048, */ 0x0000000000000000UL,
|
||||
/* 0x0050, */ 0x001404010000FFFFUL,
|
||||
/* 0x0058, */ 0x0014201F0000FFFFUL,
|
||||
/* 0x0060, */ 0x00141C190000FFFFUL,
|
||||
/* 0x0068, */ 0x0000000000000000UL,
|
||||
/* 0x0070, */ 0x001404010000FFFFUL,
|
||||
/* 0x0078, */ 0x0010100D0000FFFFUL,
|
||||
/* 0x0080, */ 0x0000000000000000UL,
|
||||
/* 0x0088, */ 0x001444210000FFFFUL,
|
||||
/* 0x0090, */ 0x00141C190000FFFFUL,
|
||||
/* 0x0098, */ 0x0000000000000000UL,
|
||||
/* 0x00a0, */ 0x000C08040000FFFFUL,
|
||||
/* 0x00a8, */ 0x000C04020000FFFFUL,
|
||||
/* 0x00b0, */ 0x000C04020000FFFFUL,
|
||||
/* 0x00b8, */ 0x0000000000000000UL,
|
||||
/* 0x00c0, */ 0x000C08040000FFFFUL,
|
||||
/* 0x00c8, */ 0x000C04020000FFFFUL,
|
||||
/* 0x00d0, */ 0x000C04020000FFFFUL,
|
||||
/* 0x00d8, */ 0x001044110000FFFFUL,
|
||||
/* 0x00e0, */ 0x001014110000FFFFUL,
|
||||
/* 0x00e8, */ 0x0000000000000000UL,
|
||||
/* 0x00f0, */ 0x001044110000FFFFUL,
|
||||
/* 0x00f8, */ 0x000C100D0000FFFFUL,
|
||||
/* 0x0100, */ 0x0000000000000000UL,
|
||||
/* 0x0108, */ 0x0000000000000000UL,
|
||||
/* 0x0110, */ 0x001014110000FFFFUL,
|
||||
/* 0x0118, */ 0x000C20200000FFFFUL,
|
||||
/* 0x0120, */ 0x000C20200000FFFFUL,
|
||||
/* 0x0128, */ 0x0000000000000000UL,
|
||||
/* 0x0130, */ 0x0000000000000000UL,
|
||||
/* 0x0138, */ 0x001018150000FFFFUL,
|
||||
/* 0x0140, */ 0x001018150000FFFFUL,
|
||||
/* 0x0148, */ 0x0000000000000000UL,
|
||||
/* 0x0150, */ 0x00101C190000FFFFUL,
|
||||
/* 0x0158, */ 0x00101C190000FFFFUL,
|
||||
/* 0x0160, */ 0x001018150000FFFFUL,
|
||||
/* 0x0168, */ 0x001018150000FFFFUL,
|
||||
/* 0x0170, */ 0x0000000000000000UL,
|
||||
/* 0x0178, */ 0x00100C0B0000FFFFUL,
|
||||
/* 0x0180, */ 0x00100C0B0000FFFFUL,
|
||||
/* 0x0188, */ 0x0000000000000000UL,
|
||||
/* 0x0190, */ 0x001058570000FFFFUL,
|
||||
/* 0x0198, */ 0x001058570000FFFFUL,
|
||||
/* 0x01a0, */ 0x001018150000FFFFUL,
|
||||
/* 0x01a8, */ 0x001018150000FFFFUL,
|
||||
/* 0x01b0, */ 0x0000000000000000UL,
|
||||
/* 0x01b8, */ 0x0000000000000000UL,
|
||||
/* 0x01c0, */ 0x000C04010000FFFFUL,
|
||||
/* 0x01c8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x01d0, */ 0x000C04010000FFFFUL,
|
||||
/* 0x01d8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x01e0, */ 0x0000000000000000UL,
|
||||
/* 0x01e8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x01f0, */ 0x000C04010000FFFFUL,
|
||||
/* 0x01f8, */ 0x0000000000000000UL,
|
||||
/* 0x0200, */ 0x0000000000000000UL,
|
||||
/* 0x0208, */ 0x000C04010000FFFFUL,
|
||||
/* 0x0210, */ 0x000C04010000FFFFUL,
|
||||
/* 0x0218, */ 0x0000000000000000UL,
|
||||
/* 0x0220, */ 0x0000000000000000UL,
|
||||
/* 0x0228, */ 0x0000000000000000UL,
|
||||
/* 0x0230, */ 0x0000000000000000UL,
|
||||
/* 0x0238, */ 0x0000000000000000UL,
|
||||
/* 0x0240, */ 0x0000000000000000UL,
|
||||
/* 0x0248, */ 0x0000000000000000UL,
|
||||
/* 0x0250, */ 0x0000000000000000UL,
|
||||
/* 0x0258, */ 0x0000000000000000UL,
|
||||
/* 0x0260, */ 0x000C0C030000FFFFUL,
|
||||
/* 0x0268, */ 0x001410010000FFFFUL,
|
||||
/* 0x0270, */ 0x001404010000FFFFUL,
|
||||
/* 0x0278, */ 0x000C08020000FFFFUL,
|
||||
/* 0x0280, */ 0x0000000000000000UL,
|
||||
/* 0x0288, */ 0x0000000000000000UL,
|
||||
/* 0x0290, */ 0x001410010000FFFFUL,
|
||||
/* 0x0298, */ 0x001404010000FFFFUL,
|
||||
/* 0x02a0, */ 0x000C04010000FFFFUL,
|
||||
/* 0x02a8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x02b0, */ 0x00140C010000FFFFUL,
|
||||
/* 0x02b8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x02c0, */ 0x0000000000000000UL,
|
||||
/* 0x02c8, */ 0x0000000000000000UL,
|
||||
/* 0x02d0, */ 0x000C04010000FFFFUL,
|
||||
/* 0x02d8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x02e0, */ 0x00140C010000FFFFUL,
|
||||
/* 0x02e8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x02f0, */ 0x0000000000000000UL,
|
||||
/* 0x02f8, */ 0x0000000000000000UL,
|
||||
/* 0x0300, */ 0x0000000000000000UL,
|
||||
/* 0x0308, */ 0x0000000000000000UL,
|
||||
/* 0x0310, */ 0x0000000000000000UL,
|
||||
/* 0x0318, */ 0x0000000000000000UL,
|
||||
/* 0x0320, */ 0x0000000000000000UL,
|
||||
/* 0x0328, */ 0x0000000000000000UL,
|
||||
/* 0x0330, */ 0x0000000000000000UL,
|
||||
/* 0x0338, */ 0x0000000000000000UL,
|
||||
/* 0x0340, */ 0x0000000000000000UL,
|
||||
/* 0x0348, */ 0x0000000000000000UL,
|
||||
/* 0x0350, */ 0x0000000000000000UL,
|
||||
/* 0x0358, */ 0x0000000000000000UL,
|
||||
/* 0x0360, */ 0x0000000000000000UL,
|
||||
/* 0x0368, */ 0x0000000000000000UL,
|
||||
};
|
||||
|
||||
static uint64_t mstat_be[] = {
|
||||
/* 0x0000, */ 0x0012003005EFFC01UL,
|
||||
/* 0x0008, */ 0x0012003005EFFC01UL,
|
||||
/* 0x0010, */ 0x0012003005EFFC01UL,
|
||||
/* 0x0018, */ 0x0012003005EFFC01UL,
|
||||
/* 0x0020, */ 0x0000000000000000UL,
|
||||
/* 0x0028, */ 0x0012001005E0FC01UL,
|
||||
/* 0x0030, */ 0x0000000000000000UL,
|
||||
/* 0x0038, */ 0x0000000000000000UL,
|
||||
/* 0x0040, */ 0x0000000000000000UL,
|
||||
/* 0x0048, */ 0x0000000000000000UL,
|
||||
/* 0x0050, */ 0x0000000000000000UL,
|
||||
/* 0x0058, */ 0x0000000000000000UL,
|
||||
/* 0x0060, */ 0x0000000000000000UL,
|
||||
/* 0x0068, */ 0x0000000000000000UL,
|
||||
/* 0x0070, */ 0x0000000000000000UL,
|
||||
/* 0x0078, */ 0x0000000000000000UL,
|
||||
/* 0x0080, */ 0x0000000000000000UL,
|
||||
/* 0x0088, */ 0x0000000000000000UL,
|
||||
/* 0x0090, */ 0x0000000000000000UL,
|
||||
/* 0x0098, */ 0x0000000000000000UL,
|
||||
/* 0x00a0, */ 0x0000000000000000UL,
|
||||
/* 0x00a8, */ 0x0000000000000000UL,
|
||||
/* 0x00b0, */ 0x0000000000000000UL,
|
||||
/* 0x00b8, */ 0x0000000000000000UL,
|
||||
/* 0x00c0, */ 0x0000000000000000UL,
|
||||
/* 0x00c8, */ 0x0000000000000000UL,
|
||||
/* 0x00d0, */ 0x0000000000000000UL,
|
||||
/* 0x00d8, */ 0x0000000000000000UL,
|
||||
/* 0x00e0, */ 0x0000000000000000UL,
|
||||
/* 0x00e8, */ 0x0000000000000000UL,
|
||||
/* 0x00f0, */ 0x0000000000000000UL,
|
||||
/* 0x00f8, */ 0x0000000000000000UL,
|
||||
/* 0x0100, */ 0x0000000000000000UL,
|
||||
/* 0x0108, */ 0x0000000000000000UL,
|
||||
/* 0x0110, */ 0x0000000000000000UL,
|
||||
/* 0x0118, */ 0x0000000000000000UL,
|
||||
/* 0x0120, */ 0x0000000000000000UL,
|
||||
/* 0x0128, */ 0x0000000000000000UL,
|
||||
/* 0x0130, */ 0x0000000000000000UL,
|
||||
/* 0x0138, */ 0x0000000000000000UL,
|
||||
/* 0x0140, */ 0x0000000000000000UL,
|
||||
/* 0x0148, */ 0x0000000000000000UL,
|
||||
/* 0x0150, */ 0x0000000000000000UL,
|
||||
/* 0x0158, */ 0x0000000000000000UL,
|
||||
/* 0x0160, */ 0x0000000000000000UL,
|
||||
/* 0x0168, */ 0x0000000000000000UL,
|
||||
/* 0x0170, */ 0x0000000000000000UL,
|
||||
/* 0x0178, */ 0x0000000000000000UL,
|
||||
/* 0x0180, */ 0x0000000000000000UL,
|
||||
/* 0x0188, */ 0x0000000000000000UL,
|
||||
/* 0x0190, */ 0x0000000000000000UL,
|
||||
/* 0x0198, */ 0x0000000000000000UL,
|
||||
/* 0x01a0, */ 0x0000000000000000UL,
|
||||
/* 0x01a8, */ 0x0000000000000000UL,
|
||||
/* 0x01b0, */ 0x0000000000000000UL,
|
||||
/* 0x01b8, */ 0x0000000000000000UL,
|
||||
/* 0x01c0, */ 0x002100D005EFFC01UL,
|
||||
/* 0x01c8, */ 0x002100D005EFFC01UL,
|
||||
/* 0x01d0, */ 0x002100D005EFFC01UL,
|
||||
/* 0x01d8, */ 0x002100D005EFFC01UL,
|
||||
/* 0x01e0, */ 0x0000000000000000UL,
|
||||
/* 0x01e8, */ 0x0000000000000000UL,
|
||||
/* 0x01f0, */ 0x0021003005EFFC01UL,
|
||||
/* 0x01f8, */ 0x0000000000000000UL,
|
||||
/* 0x0200, */ 0x0000000000000000UL,
|
||||
/* 0x0208, */ 0x0000000000000000UL,
|
||||
/* 0x0210, */ 0x0021003005EFFC01UL,
|
||||
/* 0x0218, */ 0x0011003005EFFC01UL,
|
||||
/* 0x0220, */ 0x0011003005EFFC01UL,
|
||||
/* 0x0228, */ 0x0000000000000000UL,
|
||||
/* 0x0230, */ 0x0011003005EFFC01UL,
|
||||
/* 0x0238, */ 0x0011003005EFFC01UL,
|
||||
/* 0x0240, */ 0x0012003005EFFC01UL,
|
||||
/* 0x0248, */ 0x0011003005EFFC01UL,
|
||||
/* 0x0250, */ 0x0012003005EFFC01UL,
|
||||
/* 0x0258, */ 0x0011003005EFFC01UL,
|
||||
/* 0x0260, */ 0x0000000000000000UL,
|
||||
/* 0x0268, */ 0x0000000000000000UL,
|
||||
/* 0x0270, */ 0x0000000000000000UL,
|
||||
/* 0x0278, */ 0x0000000000000000UL,
|
||||
/* 0x0280, */ 0x0000000000000000UL,
|
||||
/* 0x0288, */ 0x0000000000000000UL,
|
||||
/* 0x0290, */ 0x0000000000000000UL,
|
||||
/* 0x0298, */ 0x0000000000000000UL,
|
||||
/* 0x02a0, */ 0x0000000000000000UL,
|
||||
/* 0x02a8, */ 0x0000000000000000UL,
|
||||
/* 0x02b0, */ 0x0000000000000000UL,
|
||||
/* 0x02b8, */ 0x0000000000000000UL,
|
||||
/* 0x02c0, */ 0x0000000000000000UL,
|
||||
/* 0x02c8, */ 0x0000000000000000UL,
|
||||
/* 0x02d0, */ 0x0000000000000000UL,
|
||||
/* 0x02d8, */ 0x0000000000000000UL,
|
||||
/* 0x02e0, */ 0x0000000000000000UL,
|
||||
/* 0x02e8, */ 0x0000000000000000UL,
|
||||
/* 0x02f0, */ 0x0011007005EFFC01UL,
|
||||
/* 0x02f8, */ 0x001100B005EFFC01UL,
|
||||
/* 0x0300, */ 0x0000000000000000UL,
|
||||
/* 0x0308, */ 0x0011007005EFFC01UL,
|
||||
/* 0x0310, */ 0x001100B005EFFC01UL,
|
||||
/* 0x0318, */ 0x0012001005E03401UL,
|
||||
/* 0x0320, */ 0x0011007005EFFC01UL,
|
||||
/* 0x0328, */ 0x001100B005EFFC01UL,
|
||||
/* 0x0330, */ 0x0011007005EFFC01UL,
|
||||
/* 0x0338, */ 0x001100B005EFFC01UL,
|
||||
/* 0x0340, */ 0x0000000000000000UL,
|
||||
/* 0x0348, */ 0x0000000000000000UL,
|
||||
/* 0x0350, */ 0x0000000000000000UL,
|
||||
/* 0x0358, */ 0x0000000000000000UL,
|
||||
/* 0x0360, */ 0x0000000000000000UL,
|
||||
/* 0x0368, */ 0x0012001005E0FC01UL,
|
||||
};
|
231
drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20_qoswt195.h
Normal file
231
drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20_qoswt195.h
Normal file
|
@ -0,0 +1,231 @@
|
|||
/*
|
||||
* Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
static uint64_t qoswt_fix[] = {
|
||||
/* 0x0000, */ 0x0000000000000000UL,
|
||||
/* 0x0008, */ 0x0000000000000000UL,
|
||||
/* 0x0010, */ 0x0000000000000000UL,
|
||||
/* 0x0018, */ 0x0000000000000000UL,
|
||||
/* 0x0020, */ 0x0000000000000000UL,
|
||||
/* 0x0028, */ 0x0000000000000000UL,
|
||||
/* 0x0030, */ 0x001004040000C010UL,
|
||||
/* 0x0038, */ 0x001008070000C010UL,
|
||||
/* 0x0040, */ 0x001424110000FFF0UL,
|
||||
/* 0x0048, */ 0x0000000000000000UL,
|
||||
/* 0x0050, */ 0x0000000000000000UL,
|
||||
/* 0x0058, */ 0x001410100000C010UL,
|
||||
/* 0x0060, */ 0x0014100D0000C010UL,
|
||||
/* 0x0068, */ 0x0000000000000000UL,
|
||||
/* 0x0070, */ 0x0000000000000000UL,
|
||||
/* 0x0078, */ 0x001008070000C010UL,
|
||||
/* 0x0080, */ 0x0000000000000000UL,
|
||||
/* 0x0088, */ 0x001424110000FFF0UL,
|
||||
/* 0x0090, */ 0x0014100D0000C010UL,
|
||||
/* 0x0098, */ 0x0000000000000000UL,
|
||||
/* 0x00a0, */ 0x0000000000000000UL,
|
||||
/* 0x00a8, */ 0x0000000000000000UL,
|
||||
/* 0x00b0, */ 0x0000000000000000UL,
|
||||
/* 0x00b8, */ 0x0000000000000000UL,
|
||||
/* 0x00c0, */ 0x0000000000000000UL,
|
||||
/* 0x00c8, */ 0x0000000000000000UL,
|
||||
/* 0x00d0, */ 0x0000000000000000UL,
|
||||
/* 0x00d8, */ 0x0000000000000000UL,
|
||||
/* 0x00e0, */ 0x0000000000000000UL,
|
||||
/* 0x00e8, */ 0x0000000000000000UL,
|
||||
/* 0x00f0, */ 0x0000000000000000UL,
|
||||
/* 0x00f8, */ 0x0000000000000000UL,
|
||||
/* 0x0100, */ 0x0000000000000000UL,
|
||||
/* 0x0108, */ 0x0000000000000000UL,
|
||||
/* 0x0110, */ 0x0000000000000000UL,
|
||||
/* 0x0118, */ 0x0000000000000000UL,
|
||||
/* 0x0120, */ 0x0000000000000000UL,
|
||||
/* 0x0128, */ 0x0000000000000000UL,
|
||||
/* 0x0130, */ 0x0000000000000000UL,
|
||||
/* 0x0138, */ 0x0000000000000000UL,
|
||||
/* 0x0140, */ 0x0000000000000000UL,
|
||||
/* 0x0148, */ 0x0000000000000000UL,
|
||||
/* 0x0150, */ 0x0000000000000000UL,
|
||||
/* 0x0158, */ 0x0000000000000000UL,
|
||||
/* 0x0160, */ 0x0000000000000000UL,
|
||||
/* 0x0168, */ 0x0000000000000000UL,
|
||||
/* 0x0170, */ 0x0000000000000000UL,
|
||||
/* 0x0178, */ 0x0000000000000000UL,
|
||||
/* 0x0180, */ 0x0000000000000000UL,
|
||||
/* 0x0188, */ 0x0000000000000000UL,
|
||||
/* 0x0190, */ 0x0000000000000000UL,
|
||||
/* 0x0198, */ 0x0000000000000000UL,
|
||||
/* 0x01a0, */ 0x0000000000000000UL,
|
||||
/* 0x01a8, */ 0x0000000000000000UL,
|
||||
/* 0x01b0, */ 0x0000000000000000UL,
|
||||
/* 0x01b8, */ 0x0000000000000000UL,
|
||||
/* 0x01c0, */ 0x0000000000000000UL,
|
||||
/* 0x01c8, */ 0x0000000000000000UL,
|
||||
/* 0x01d0, */ 0x0000000000000000UL,
|
||||
/* 0x01d8, */ 0x0000000000000000UL,
|
||||
/* 0x01e0, */ 0x0000000000000000UL,
|
||||
/* 0x01e8, */ 0x0000000000000000UL,
|
||||
/* 0x01f0, */ 0x0000000000000000UL,
|
||||
/* 0x01f8, */ 0x0000000000000000UL,
|
||||
/* 0x0200, */ 0x0000000000000000UL,
|
||||
/* 0x0208, */ 0x0000000000000000UL,
|
||||
/* 0x0210, */ 0x0000000000000000UL,
|
||||
/* 0x0218, */ 0x0000000000000000UL,
|
||||
/* 0x0220, */ 0x0000000000000000UL,
|
||||
/* 0x0228, */ 0x0000000000000000UL,
|
||||
/* 0x0230, */ 0x0000000000000000UL,
|
||||
/* 0x0238, */ 0x0000000000000000UL,
|
||||
/* 0x0240, */ 0x0000000000000000UL,
|
||||
/* 0x0248, */ 0x0000000000000000UL,
|
||||
/* 0x0250, */ 0x0000000000000000UL,
|
||||
/* 0x0258, */ 0x0000000000000000UL,
|
||||
/* 0x0260, */ 0x000C08020000FFF0UL,
|
||||
/* 0x0268, */ 0x001408010000FFF0UL,
|
||||
/* 0x0270, */ 0x001404010000FFF0UL,
|
||||
/* 0x0278, */ 0x000C04010000FFF0UL,
|
||||
/* 0x0280, */ 0x0000000000000000UL,
|
||||
/* 0x0288, */ 0x0000000000000000UL,
|
||||
/* 0x0290, */ 0x001408010000FFF0UL,
|
||||
/* 0x0298, */ 0x001404010000FFF0UL,
|
||||
/* 0x02a0, */ 0x0000000000000000UL,
|
||||
/* 0x02a8, */ 0x0000000000000000UL,
|
||||
/* 0x02b0, */ 0x0000000000000000UL,
|
||||
/* 0x02b8, */ 0x0000000000000000UL,
|
||||
/* 0x02c0, */ 0x0000000000000000UL,
|
||||
/* 0x02c8, */ 0x0000000000000000UL,
|
||||
/* 0x02d0, */ 0x0000000000000000UL,
|
||||
/* 0x02d8, */ 0x0000000000000000UL,
|
||||
/* 0x02e0, */ 0x0000000000000000UL,
|
||||
/* 0x02e8, */ 0x0000000000000000UL,
|
||||
/* 0x02f0, */ 0x0000000000000000UL,
|
||||
/* 0x02f8, */ 0x0000000000000000UL,
|
||||
/* 0x0300, */ 0x0000000000000000UL,
|
||||
/* 0x0308, */ 0x0000000000000000UL,
|
||||
/* 0x0310, */ 0x0000000000000000UL,
|
||||
/* 0x0318, */ 0x0000000000000000UL,
|
||||
/* 0x0320, */ 0x0000000000000000UL,
|
||||
/* 0x0328, */ 0x0000000000000000UL,
|
||||
/* 0x0330, */ 0x0000000000000000UL,
|
||||
/* 0x0338, */ 0x0000000000000000UL,
|
||||
/* 0x0340, */ 0x0000000000000000UL,
|
||||
/* 0x0348, */ 0x0000000000000000UL,
|
||||
/* 0x0350, */ 0x0000000000000000UL,
|
||||
/* 0x0358, */ 0x0000000000000000UL,
|
||||
/* 0x0360, */ 0x0000000000000000UL,
|
||||
/* 0x0368, */ 0x0000000000000000UL,
|
||||
};
|
||||
|
||||
static uint64_t qoswt_be[] = {
|
||||
/* 0x0000, */ 0x0000000000000000UL,
|
||||
/* 0x0008, */ 0x0000000000000000UL,
|
||||
/* 0x0010, */ 0x0000000000000000UL,
|
||||
/* 0x0018, */ 0x0000000000000000UL,
|
||||
/* 0x0020, */ 0x0000000000000000UL,
|
||||
/* 0x0028, */ 0x0000000000000000UL,
|
||||
/* 0x0030, */ 0x0000000000000000UL,
|
||||
/* 0x0038, */ 0x0000000000000000UL,
|
||||
/* 0x0040, */ 0x0000000000000000UL,
|
||||
/* 0x0048, */ 0x0000000000000000UL,
|
||||
/* 0x0050, */ 0x0000000000000000UL,
|
||||
/* 0x0058, */ 0x0000000000000000UL,
|
||||
/* 0x0060, */ 0x0000000000000000UL,
|
||||
/* 0x0068, */ 0x0000000000000000UL,
|
||||
/* 0x0070, */ 0x0000000000000000UL,
|
||||
/* 0x0078, */ 0x0000000000000000UL,
|
||||
/* 0x0080, */ 0x0000000000000000UL,
|
||||
/* 0x0088, */ 0x0000000000000000UL,
|
||||
/* 0x0090, */ 0x0000000000000000UL,
|
||||
/* 0x0098, */ 0x0000000000000000UL,
|
||||
/* 0x00a0, */ 0x0000000000000000UL,
|
||||
/* 0x00a8, */ 0x0000000000000000UL,
|
||||
/* 0x00b0, */ 0x0000000000000000UL,
|
||||
/* 0x00b8, */ 0x0000000000000000UL,
|
||||
/* 0x00c0, */ 0x0000000000000000UL,
|
||||
/* 0x00c8, */ 0x0000000000000000UL,
|
||||
/* 0x00d0, */ 0x0000000000000000UL,
|
||||
/* 0x00d8, */ 0x0000000000000000UL,
|
||||
/* 0x00e0, */ 0x0000000000000000UL,
|
||||
/* 0x00e8, */ 0x0000000000000000UL,
|
||||
/* 0x00f0, */ 0x0000000000000000UL,
|
||||
/* 0x00f8, */ 0x0000000000000000UL,
|
||||
/* 0x0100, */ 0x0000000000000000UL,
|
||||
/* 0x0108, */ 0x0000000000000000UL,
|
||||
/* 0x0110, */ 0x0000000000000000UL,
|
||||
/* 0x0118, */ 0x0000000000000000UL,
|
||||
/* 0x0120, */ 0x0000000000000000UL,
|
||||
/* 0x0128, */ 0x0000000000000000UL,
|
||||
/* 0x0130, */ 0x0000000000000000UL,
|
||||
/* 0x0138, */ 0x0000000000000000UL,
|
||||
/* 0x0140, */ 0x0000000000000000UL,
|
||||
/* 0x0148, */ 0x0000000000000000UL,
|
||||
/* 0x0150, */ 0x0000000000000000UL,
|
||||
/* 0x0158, */ 0x0000000000000000UL,
|
||||
/* 0x0160, */ 0x0000000000000000UL,
|
||||
/* 0x0168, */ 0x0000000000000000UL,
|
||||
/* 0x0170, */ 0x0000000000000000UL,
|
||||
/* 0x0178, */ 0x0000000000000000UL,
|
||||
/* 0x0180, */ 0x0000000000000000UL,
|
||||
/* 0x0188, */ 0x0000000000000000UL,
|
||||
/* 0x0190, */ 0x0000000000000000UL,
|
||||
/* 0x0198, */ 0x0000000000000000UL,
|
||||
/* 0x01a0, */ 0x0000000000000000UL,
|
||||
/* 0x01a8, */ 0x0000000000000000UL,
|
||||
/* 0x01b0, */ 0x0000000000000000UL,
|
||||
/* 0x01b8, */ 0x0000000000000000UL,
|
||||
/* 0x01c0, */ 0x0000000000000000UL,
|
||||
/* 0x01c8, */ 0x0000000000000000UL,
|
||||
/* 0x01d0, */ 0x0000000000000000UL,
|
||||
/* 0x01d8, */ 0x0000000000000000UL,
|
||||
/* 0x01e0, */ 0x0000000000000000UL,
|
||||
/* 0x01e8, */ 0x0000000000000000UL,
|
||||
/* 0x01f0, */ 0x0000000000000000UL,
|
||||
/* 0x01f8, */ 0x0000000000000000UL,
|
||||
/* 0x0200, */ 0x0000000000000000UL,
|
||||
/* 0x0208, */ 0x0000000000000000UL,
|
||||
/* 0x0210, */ 0x0000000000000000UL,
|
||||
/* 0x0218, */ 0x0000000000000000UL,
|
||||
/* 0x0220, */ 0x0000000000000000UL,
|
||||
/* 0x0228, */ 0x0000000000000000UL,
|
||||
/* 0x0230, */ 0x0000000000000000UL,
|
||||
/* 0x0238, */ 0x0000000000000000UL,
|
||||
/* 0x0240, */ 0x0000000000000000UL,
|
||||
/* 0x0248, */ 0x0000000000000000UL,
|
||||
/* 0x0250, */ 0x0000000000000000UL,
|
||||
/* 0x0258, */ 0x0000000000000000UL,
|
||||
/* 0x0260, */ 0x0000000000000000UL,
|
||||
/* 0x0268, */ 0x0000000000000000UL,
|
||||
/* 0x0270, */ 0x0000000000000000UL,
|
||||
/* 0x0278, */ 0x0000000000000000UL,
|
||||
/* 0x0280, */ 0x0000000000000000UL,
|
||||
/* 0x0288, */ 0x0000000000000000UL,
|
||||
/* 0x0290, */ 0x0000000000000000UL,
|
||||
/* 0x0298, */ 0x0000000000000000UL,
|
||||
/* 0x02a0, */ 0x0000000000000000UL,
|
||||
/* 0x02a8, */ 0x0000000000000000UL,
|
||||
/* 0x02b0, */ 0x0000000000000000UL,
|
||||
/* 0x02b8, */ 0x0000000000000000UL,
|
||||
/* 0x02c0, */ 0x0000000000000000UL,
|
||||
/* 0x02c8, */ 0x0000000000000000UL,
|
||||
/* 0x02d0, */ 0x0000000000000000UL,
|
||||
/* 0x02d8, */ 0x0000000000000000UL,
|
||||
/* 0x02e0, */ 0x0000000000000000UL,
|
||||
/* 0x02e8, */ 0x0000000000000000UL,
|
||||
/* 0x02f0, */ 0x0000000000000000UL,
|
||||
/* 0x02f8, */ 0x0000000000000000UL,
|
||||
/* 0x0300, */ 0x0000000000000000UL,
|
||||
/* 0x0308, */ 0x0000000000000000UL,
|
||||
/* 0x0310, */ 0x0000000000000000UL,
|
||||
/* 0x0318, */ 0x0000000000000000UL,
|
||||
/* 0x0320, */ 0x0000000000000000UL,
|
||||
/* 0x0328, */ 0x0000000000000000UL,
|
||||
/* 0x0330, */ 0x0000000000000000UL,
|
||||
/* 0x0338, */ 0x0000000000000000UL,
|
||||
/* 0x0340, */ 0x0000000000000000UL,
|
||||
/* 0x0348, */ 0x0000000000000000UL,
|
||||
/* 0x0350, */ 0x0000000000000000UL,
|
||||
/* 0x0358, */ 0x0000000000000000UL,
|
||||
/* 0x0360, */ 0x0000000000000000UL,
|
||||
/* 0x0368, */ 0x0000000000000000UL,
|
||||
};
|
231
drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20_qoswt390.h
Normal file
231
drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20_qoswt390.h
Normal file
|
@ -0,0 +1,231 @@
|
|||
/*
|
||||
* Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
static uint64_t qoswt_fix[] = {
|
||||
/* 0x0000, */ 0x0000000000000000UL,
|
||||
/* 0x0008, */ 0x0000000000000000UL,
|
||||
/* 0x0010, */ 0x0000000000000000UL,
|
||||
/* 0x0018, */ 0x0000000000000000UL,
|
||||
/* 0x0020, */ 0x0000000000000000UL,
|
||||
/* 0x0028, */ 0x0000000000000000UL,
|
||||
/* 0x0030, */ 0x001008070000C010UL,
|
||||
/* 0x0038, */ 0x0010100D0000C010UL,
|
||||
/* 0x0040, */ 0x001444210000FFF0UL,
|
||||
/* 0x0048, */ 0x0000000000000000UL,
|
||||
/* 0x0050, */ 0x0000000000000000UL,
|
||||
/* 0x0058, */ 0x0014201F0000C010UL,
|
||||
/* 0x0060, */ 0x00141C190000C010UL,
|
||||
/* 0x0068, */ 0x0000000000000000UL,
|
||||
/* 0x0070, */ 0x0000000000000000UL,
|
||||
/* 0x0078, */ 0x0010100D0000C010UL,
|
||||
/* 0x0080, */ 0x0000000000000000UL,
|
||||
/* 0x0088, */ 0x001444210000FFF0UL,
|
||||
/* 0x0090, */ 0x00141C190000C010UL,
|
||||
/* 0x0098, */ 0x0000000000000000UL,
|
||||
/* 0x00a0, */ 0x0000000000000000UL,
|
||||
/* 0x00a8, */ 0x0000000000000000UL,
|
||||
/* 0x00b0, */ 0x0000000000000000UL,
|
||||
/* 0x00b8, */ 0x0000000000000000UL,
|
||||
/* 0x00c0, */ 0x0000000000000000UL,
|
||||
/* 0x00c8, */ 0x0000000000000000UL,
|
||||
/* 0x00d0, */ 0x0000000000000000UL,
|
||||
/* 0x00d8, */ 0x0000000000000000UL,
|
||||
/* 0x00e0, */ 0x0000000000000000UL,
|
||||
/* 0x00e8, */ 0x0000000000000000UL,
|
||||
/* 0x00f0, */ 0x0000000000000000UL,
|
||||
/* 0x00f8, */ 0x0000000000000000UL,
|
||||
/* 0x0100, */ 0x0000000000000000UL,
|
||||
/* 0x0108, */ 0x0000000000000000UL,
|
||||
/* 0x0110, */ 0x0000000000000000UL,
|
||||
/* 0x0118, */ 0x0000000000000000UL,
|
||||
/* 0x0120, */ 0x0000000000000000UL,
|
||||
/* 0x0128, */ 0x0000000000000000UL,
|
||||
/* 0x0130, */ 0x0000000000000000UL,
|
||||
/* 0x0138, */ 0x0000000000000000UL,
|
||||
/* 0x0140, */ 0x0000000000000000UL,
|
||||
/* 0x0148, */ 0x0000000000000000UL,
|
||||
/* 0x0150, */ 0x0000000000000000UL,
|
||||
/* 0x0158, */ 0x0000000000000000UL,
|
||||
/* 0x0160, */ 0x0000000000000000UL,
|
||||
/* 0x0168, */ 0x0000000000000000UL,
|
||||
/* 0x0170, */ 0x0000000000000000UL,
|
||||
/* 0x0178, */ 0x0000000000000000UL,
|
||||
/* 0x0180, */ 0x0000000000000000UL,
|
||||
/* 0x0188, */ 0x0000000000000000UL,
|
||||
/* 0x0190, */ 0x0000000000000000UL,
|
||||
/* 0x0198, */ 0x0000000000000000UL,
|
||||
/* 0x01a0, */ 0x0000000000000000UL,
|
||||
/* 0x01a8, */ 0x0000000000000000UL,
|
||||
/* 0x01b0, */ 0x0000000000000000UL,
|
||||
/* 0x01b8, */ 0x0000000000000000UL,
|
||||
/* 0x01c0, */ 0x0000000000000000UL,
|
||||
/* 0x01c8, */ 0x0000000000000000UL,
|
||||
/* 0x01d0, */ 0x0000000000000000UL,
|
||||
/* 0x01d8, */ 0x0000000000000000UL,
|
||||
/* 0x01e0, */ 0x0000000000000000UL,
|
||||
/* 0x01e8, */ 0x0000000000000000UL,
|
||||
/* 0x01f0, */ 0x0000000000000000UL,
|
||||
/* 0x01f8, */ 0x0000000000000000UL,
|
||||
/* 0x0200, */ 0x0000000000000000UL,
|
||||
/* 0x0208, */ 0x0000000000000000UL,
|
||||
/* 0x0210, */ 0x0000000000000000UL,
|
||||
/* 0x0218, */ 0x0000000000000000UL,
|
||||
/* 0x0220, */ 0x0000000000000000UL,
|
||||
/* 0x0228, */ 0x0000000000000000UL,
|
||||
/* 0x0230, */ 0x0000000000000000UL,
|
||||
/* 0x0238, */ 0x0000000000000000UL,
|
||||
/* 0x0240, */ 0x0000000000000000UL,
|
||||
/* 0x0248, */ 0x0000000000000000UL,
|
||||
/* 0x0250, */ 0x0000000000000000UL,
|
||||
/* 0x0258, */ 0x0000000000000000UL,
|
||||
/* 0x0260, */ 0x000C0C030000FFF0UL,
|
||||
/* 0x0268, */ 0x001410010000FFF0UL,
|
||||
/* 0x0270, */ 0x001404010000FFF0UL,
|
||||
/* 0x0278, */ 0x000C08020000FFF0UL,
|
||||
/* 0x0280, */ 0x0000000000000000UL,
|
||||
/* 0x0288, */ 0x0000000000000000UL,
|
||||
/* 0x0290, */ 0x001410010000FFF0UL,
|
||||
/* 0x0298, */ 0x001404010000FFF0UL,
|
||||
/* 0x02a0, */ 0x0000000000000000UL,
|
||||
/* 0x02a8, */ 0x0000000000000000UL,
|
||||
/* 0x02b0, */ 0x0000000000000000UL,
|
||||
/* 0x02b8, */ 0x0000000000000000UL,
|
||||
/* 0x02c0, */ 0x0000000000000000UL,
|
||||
/* 0x02c8, */ 0x0000000000000000UL,
|
||||
/* 0x02d0, */ 0x0000000000000000UL,
|
||||
/* 0x02d8, */ 0x0000000000000000UL,
|
||||
/* 0x02e0, */ 0x0000000000000000UL,
|
||||
/* 0x02e8, */ 0x0000000000000000UL,
|
||||
/* 0x02f0, */ 0x0000000000000000UL,
|
||||
/* 0x02f8, */ 0x0000000000000000UL,
|
||||
/* 0x0300, */ 0x0000000000000000UL,
|
||||
/* 0x0308, */ 0x0000000000000000UL,
|
||||
/* 0x0310, */ 0x0000000000000000UL,
|
||||
/* 0x0318, */ 0x0000000000000000UL,
|
||||
/* 0x0320, */ 0x0000000000000000UL,
|
||||
/* 0x0328, */ 0x0000000000000000UL,
|
||||
/* 0x0330, */ 0x0000000000000000UL,
|
||||
/* 0x0338, */ 0x0000000000000000UL,
|
||||
/* 0x0340, */ 0x0000000000000000UL,
|
||||
/* 0x0348, */ 0x0000000000000000UL,
|
||||
/* 0x0350, */ 0x0000000000000000UL,
|
||||
/* 0x0358, */ 0x0000000000000000UL,
|
||||
/* 0x0360, */ 0x0000000000000000UL,
|
||||
/* 0x0368, */ 0x0000000000000000UL,
|
||||
};
|
||||
|
||||
static uint64_t qoswt_be[] = {
|
||||
/* 0x0000, */ 0x0000000000000000UL,
|
||||
/* 0x0008, */ 0x0000000000000000UL,
|
||||
/* 0x0010, */ 0x0000000000000000UL,
|
||||
/* 0x0018, */ 0x0000000000000000UL,
|
||||
/* 0x0020, */ 0x0000000000000000UL,
|
||||
/* 0x0028, */ 0x0000000000000000UL,
|
||||
/* 0x0030, */ 0x0000000000000000UL,
|
||||
/* 0x0038, */ 0x0000000000000000UL,
|
||||
/* 0x0040, */ 0x0000000000000000UL,
|
||||
/* 0x0048, */ 0x0000000000000000UL,
|
||||
/* 0x0050, */ 0x0000000000000000UL,
|
||||
/* 0x0058, */ 0x0000000000000000UL,
|
||||
/* 0x0060, */ 0x0000000000000000UL,
|
||||
/* 0x0068, */ 0x0000000000000000UL,
|
||||
/* 0x0070, */ 0x0000000000000000UL,
|
||||
/* 0x0078, */ 0x0000000000000000UL,
|
||||
/* 0x0080, */ 0x0000000000000000UL,
|
||||
/* 0x0088, */ 0x0000000000000000UL,
|
||||
/* 0x0090, */ 0x0000000000000000UL,
|
||||
/* 0x0098, */ 0x0000000000000000UL,
|
||||
/* 0x00a0, */ 0x0000000000000000UL,
|
||||
/* 0x00a8, */ 0x0000000000000000UL,
|
||||
/* 0x00b0, */ 0x0000000000000000UL,
|
||||
/* 0x00b8, */ 0x0000000000000000UL,
|
||||
/* 0x00c0, */ 0x0000000000000000UL,
|
||||
/* 0x00c8, */ 0x0000000000000000UL,
|
||||
/* 0x00d0, */ 0x0000000000000000UL,
|
||||
/* 0x00d8, */ 0x0000000000000000UL,
|
||||
/* 0x00e0, */ 0x0000000000000000UL,
|
||||
/* 0x00e8, */ 0x0000000000000000UL,
|
||||
/* 0x00f0, */ 0x0000000000000000UL,
|
||||
/* 0x00f8, */ 0x0000000000000000UL,
|
||||
/* 0x0100, */ 0x0000000000000000UL,
|
||||
/* 0x0108, */ 0x0000000000000000UL,
|
||||
/* 0x0110, */ 0x0000000000000000UL,
|
||||
/* 0x0118, */ 0x0000000000000000UL,
|
||||
/* 0x0120, */ 0x0000000000000000UL,
|
||||
/* 0x0128, */ 0x0000000000000000UL,
|
||||
/* 0x0130, */ 0x0000000000000000UL,
|
||||
/* 0x0138, */ 0x0000000000000000UL,
|
||||
/* 0x0140, */ 0x0000000000000000UL,
|
||||
/* 0x0148, */ 0x0000000000000000UL,
|
||||
/* 0x0150, */ 0x0000000000000000UL,
|
||||
/* 0x0158, */ 0x0000000000000000UL,
|
||||
/* 0x0160, */ 0x0000000000000000UL,
|
||||
/* 0x0168, */ 0x0000000000000000UL,
|
||||
/* 0x0170, */ 0x0000000000000000UL,
|
||||
/* 0x0178, */ 0x0000000000000000UL,
|
||||
/* 0x0180, */ 0x0000000000000000UL,
|
||||
/* 0x0188, */ 0x0000000000000000UL,
|
||||
/* 0x0190, */ 0x0000000000000000UL,
|
||||
/* 0x0198, */ 0x0000000000000000UL,
|
||||
/* 0x01a0, */ 0x0000000000000000UL,
|
||||
/* 0x01a8, */ 0x0000000000000000UL,
|
||||
/* 0x01b0, */ 0x0000000000000000UL,
|
||||
/* 0x01b8, */ 0x0000000000000000UL,
|
||||
/* 0x01c0, */ 0x0000000000000000UL,
|
||||
/* 0x01c8, */ 0x0000000000000000UL,
|
||||
/* 0x01d0, */ 0x0000000000000000UL,
|
||||
/* 0x01d8, */ 0x0000000000000000UL,
|
||||
/* 0x01e0, */ 0x0000000000000000UL,
|
||||
/* 0x01e8, */ 0x0000000000000000UL,
|
||||
/* 0x01f0, */ 0x0000000000000000UL,
|
||||
/* 0x01f8, */ 0x0000000000000000UL,
|
||||
/* 0x0200, */ 0x0000000000000000UL,
|
||||
/* 0x0208, */ 0x0000000000000000UL,
|
||||
/* 0x0210, */ 0x0000000000000000UL,
|
||||
/* 0x0218, */ 0x0000000000000000UL,
|
||||
/* 0x0220, */ 0x0000000000000000UL,
|
||||
/* 0x0228, */ 0x0000000000000000UL,
|
||||
/* 0x0230, */ 0x0000000000000000UL,
|
||||
/* 0x0238, */ 0x0000000000000000UL,
|
||||
/* 0x0240, */ 0x0000000000000000UL,
|
||||
/* 0x0248, */ 0x0000000000000000UL,
|
||||
/* 0x0250, */ 0x0000000000000000UL,
|
||||
/* 0x0258, */ 0x0000000000000000UL,
|
||||
/* 0x0260, */ 0x0000000000000000UL,
|
||||
/* 0x0268, */ 0x0000000000000000UL,
|
||||
/* 0x0270, */ 0x0000000000000000UL,
|
||||
/* 0x0278, */ 0x0000000000000000UL,
|
||||
/* 0x0280, */ 0x0000000000000000UL,
|
||||
/* 0x0288, */ 0x0000000000000000UL,
|
||||
/* 0x0290, */ 0x0000000000000000UL,
|
||||
/* 0x0298, */ 0x0000000000000000UL,
|
||||
/* 0x02a0, */ 0x0000000000000000UL,
|
||||
/* 0x02a8, */ 0x0000000000000000UL,
|
||||
/* 0x02b0, */ 0x0000000000000000UL,
|
||||
/* 0x02b8, */ 0x0000000000000000UL,
|
||||
/* 0x02c0, */ 0x0000000000000000UL,
|
||||
/* 0x02c8, */ 0x0000000000000000UL,
|
||||
/* 0x02d0, */ 0x0000000000000000UL,
|
||||
/* 0x02d8, */ 0x0000000000000000UL,
|
||||
/* 0x02e0, */ 0x0000000000000000UL,
|
||||
/* 0x02e8, */ 0x0000000000000000UL,
|
||||
/* 0x02f0, */ 0x0000000000000000UL,
|
||||
/* 0x02f8, */ 0x0000000000000000UL,
|
||||
/* 0x0300, */ 0x0000000000000000UL,
|
||||
/* 0x0308, */ 0x0000000000000000UL,
|
||||
/* 0x0310, */ 0x0000000000000000UL,
|
||||
/* 0x0318, */ 0x0000000000000000UL,
|
||||
/* 0x0320, */ 0x0000000000000000UL,
|
||||
/* 0x0328, */ 0x0000000000000000UL,
|
||||
/* 0x0330, */ 0x0000000000000000UL,
|
||||
/* 0x0338, */ 0x0000000000000000UL,
|
||||
/* 0x0340, */ 0x0000000000000000UL,
|
||||
/* 0x0348, */ 0x0000000000000000UL,
|
||||
/* 0x0350, */ 0x0000000000000000UL,
|
||||
/* 0x0358, */ 0x0000000000000000UL,
|
||||
/* 0x0360, */ 0x0000000000000000UL,
|
||||
/* 0x0368, */ 0x0000000000000000UL,
|
||||
};
|
261
drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30.c
Normal file
261
drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30.c
Normal file
|
@ -0,0 +1,261 @@
|
|||
/*
|
||||
* Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <debug.h>
|
||||
#include "../qos_common.h"
|
||||
#include "../qos_reg.h"
|
||||
#include "qos_init_h3_v30.h"
|
||||
|
||||
#define RCAR_QOS_VERSION "rev.0.07"
|
||||
|
||||
#define QOSCTRL_FSS (QOS_BASE1 + 0x0048U)
|
||||
|
||||
#define QOSWT_TIME_BANK0 (20000000U) /* unit:ns */
|
||||
|
||||
#define QOSWT_WTEN_ENABLE (0x1U)
|
||||
|
||||
#define QOSCTRL_REF_ARS_ARBSTOPCYCLE_H3_30 (SL_INIT_SSLOTCLK_H3_30 - 0x5U)
|
||||
|
||||
#define OSWT_WTREF_SLOT0_EN_REQ1_SLOT (3U)
|
||||
#define OSWT_WTREF_SLOT0_EN_REQ2_SLOT (9U)
|
||||
#define QOSWT_WTREF_SLOT0_EN ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
|
||||
#define QOSWT_WTREF_SLOT1_EN ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
|
||||
|
||||
#define QOSWT_WTSET0_REQ_SSLOT0 (5U)
|
||||
#define WT_BASE_SUB_SLOT_NUM0 (12U)
|
||||
#define QOSWT_WTSET0_PERIOD0_H3_30 ((QOSWT_TIME_BANK0/QOSWT_WTSET0_CYCLE_H3_30)-1U)
|
||||
#define QOSWT_WTSET0_SSLOT0 (QOSWT_WTSET0_REQ_SSLOT0 -1U)
|
||||
#define QOSWT_WTSET0_SLOTSLOT0 (WT_BASE_SUB_SLOT_NUM0 -1U)
|
||||
|
||||
#define QOSWT_WTSET1_PERIOD1_H3_30 (QOSWT_WTSET0_PERIOD0_H3_30)
|
||||
#define QOSWT_WTSET1_SSLOT1 (QOSWT_WTSET0_SSLOT0)
|
||||
#define QOSWT_WTSET1_SLOTSLOT1 (QOSWT_WTSET0_SLOTSLOT0)
|
||||
|
||||
#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
|
||||
|
||||
#if RCAR_REF_INT == RCAR_REF_DEFAULT
|
||||
#include "qos_init_h3_v30_mstat195.h"
|
||||
#else
|
||||
#include "qos_init_h3_v30_mstat390.h"
|
||||
#endif
|
||||
|
||||
#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
|
||||
|
||||
#if RCAR_REF_INT == RCAR_REF_DEFAULT
|
||||
#include "qos_init_h3_v30_qoswt195.h"
|
||||
#else
|
||||
#include "qos_init_h3_v30_qoswt390.h"
|
||||
#endif
|
||||
|
||||
#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
|
||||
|
||||
#endif
|
||||
|
||||
static void dbsc_setting(void)
|
||||
{
|
||||
uint32_t md = 0;
|
||||
|
||||
/* Register write enable */
|
||||
io_write_32(DBSC_DBSYSCNT0, 0x00001234U);
|
||||
|
||||
/* BUFCAM settings */
|
||||
io_write_32(DBSC_DBCAM0CNF1, 0x00043218U); /* dbcam0cnf1 */
|
||||
io_write_32(DBSC_DBCAM0CNF2, 0x000000F4U); /* dbcam0cnf2 */
|
||||
io_write_32(DBSC_DBCAM0CNF3, 0x00000000U); /* dbcam0cnf3 */
|
||||
io_write_32(DBSC_DBSCHCNT0, 0x000F0037U); /* dbschcnt0 */
|
||||
io_write_32(DBSC_DBSCHSZ0, 0x00000001U); /* dbschsz0 */
|
||||
io_write_32(DBSC_DBSCHRW0, 0x22421111U); /* dbschrw0 */
|
||||
|
||||
md = (*((volatile uint32_t *)RST_MODEMR) & 0x000A0000) >> 17;
|
||||
|
||||
switch (md) {
|
||||
case 0x0:
|
||||
/* DDR3200 */
|
||||
io_write_32(DBSC_SCFCTST2, 0x012F1123U);
|
||||
break;
|
||||
case 0x1: /* MD19=0,MD17=1 : LPDDR4-3000, 4GByte(1GByte x4) */
|
||||
/* DDR2800 */
|
||||
io_write_32(DBSC_SCFCTST2, 0x012F1123U);
|
||||
break;
|
||||
case 0x4: /* MD19=1,MD17=0 : LPDDR4-2400, 4GByte(1GByte x4) */
|
||||
/* DDR2400 */
|
||||
io_write_32(DBSC_SCFCTST2, 0x012F1123U);
|
||||
break;
|
||||
default: /* MD19=1,MD17=1 : LPDDR4-1600, 4GByte(1GByte x4) */
|
||||
/* DDR1600 */
|
||||
io_write_32(DBSC_SCFCTST2, 0x012F1123U);
|
||||
break;
|
||||
}
|
||||
|
||||
/* QoS Settings */
|
||||
io_write_32(DBSC_DBSCHQOS00, 0x00000F00U);
|
||||
io_write_32(DBSC_DBSCHQOS01, 0x00000B00U);
|
||||
io_write_32(DBSC_DBSCHQOS02, 0x00000000U);
|
||||
io_write_32(DBSC_DBSCHQOS03, 0x00000000U);
|
||||
io_write_32(DBSC_DBSCHQOS40, 0x00000300U);
|
||||
io_write_32(DBSC_DBSCHQOS41, 0x000002F0U);
|
||||
io_write_32(DBSC_DBSCHQOS42, 0x00000200U);
|
||||
io_write_32(DBSC_DBSCHQOS43, 0x00000100U);
|
||||
io_write_32(DBSC_DBSCHQOS90, 0x00000100U);
|
||||
io_write_32(DBSC_DBSCHQOS91, 0x000000F0U);
|
||||
io_write_32(DBSC_DBSCHQOS92, 0x000000A0U);
|
||||
io_write_32(DBSC_DBSCHQOS93, 0x00000040U);
|
||||
io_write_32(DBSC_DBSCHQOS120, 0x00000040U);
|
||||
io_write_32(DBSC_DBSCHQOS121, 0x00000030U);
|
||||
io_write_32(DBSC_DBSCHQOS122, 0x00000020U);
|
||||
io_write_32(DBSC_DBSCHQOS123, 0x00000010U);
|
||||
io_write_32(DBSC_DBSCHQOS130, 0x00000100U);
|
||||
io_write_32(DBSC_DBSCHQOS131, 0x000000F0U);
|
||||
io_write_32(DBSC_DBSCHQOS132, 0x000000A0U);
|
||||
io_write_32(DBSC_DBSCHQOS133, 0x00000040U);
|
||||
io_write_32(DBSC_DBSCHQOS140, 0x000000C0U);
|
||||
io_write_32(DBSC_DBSCHQOS141, 0x000000B0U);
|
||||
io_write_32(DBSC_DBSCHQOS142, 0x00000080U);
|
||||
io_write_32(DBSC_DBSCHQOS143, 0x00000040U);
|
||||
io_write_32(DBSC_DBSCHQOS150, 0x00000040U);
|
||||
io_write_32(DBSC_DBSCHQOS151, 0x00000030U);
|
||||
io_write_32(DBSC_DBSCHQOS152, 0x00000020U);
|
||||
io_write_32(DBSC_DBSCHQOS153, 0x00000010U);
|
||||
|
||||
/* Register write protect */
|
||||
io_write_32(DBSC_DBSYSCNT0, 0x00000000U);
|
||||
}
|
||||
|
||||
void qos_init_h3_v30(void)
|
||||
{
|
||||
unsigned int split_area;
|
||||
dbsc_setting();
|
||||
|
||||
#if RCAR_DRAM_LPDDR4_MEMCONF == 0 /* 1GB */
|
||||
split_area = 0x1BU;
|
||||
#else /* default 2GB */
|
||||
split_area = 0x1CU;
|
||||
#endif
|
||||
|
||||
/* DRAM Split Address mapping */
|
||||
#if (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH) || \
|
||||
(RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO)
|
||||
NOTICE("BL2: DRAM Split is 4ch(DDR %x)\n", (int)qos_init_ddr_phyvalid);
|
||||
|
||||
io_write_32(AXI_ADSPLCR0, ADSPLCR0_ADRMODE_DEFAULT
|
||||
| ADSPLCR0_SPLITSEL(0xFFU)
|
||||
| ADSPLCR0_AREA(split_area)
|
||||
| ADSPLCR0_SWP);
|
||||
io_write_32(AXI_ADSPLCR1, 0x00000000U);
|
||||
io_write_32(AXI_ADSPLCR2, 0x00001054U);
|
||||
io_write_32(AXI_ADSPLCR3, 0x00000000U);
|
||||
#elif RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH
|
||||
NOTICE("BL2: DRAM Split is 2ch(DDR %x)\n", (int)qos_init_ddr_phyvalid);
|
||||
|
||||
io_write_32(AXI_ADSPLCR0, ADSPLCR0_AREA(split_area));
|
||||
io_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT
|
||||
| ADSPLCR0_SPLITSEL(0xFFU)
|
||||
| ADSPLCR0_AREA(split_area)
|
||||
| ADSPLCR0_SWP);
|
||||
io_write_32(AXI_ADSPLCR2, 0x00001004U);
|
||||
io_write_32(AXI_ADSPLCR3, 0x00000000U);
|
||||
#else
|
||||
io_write_32(AXI_ADSPLCR0, ADSPLCR0_AREA(split_area));
|
||||
NOTICE("BL2: DRAM Split is OFF(DDR %x)\n", (int)qos_init_ddr_phyvalid);
|
||||
#endif
|
||||
|
||||
#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
|
||||
#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
|
||||
NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
|
||||
#endif
|
||||
|
||||
#if RCAR_REF_INT == RCAR_REF_DEFAULT
|
||||
NOTICE("BL2: DRAM refresh interval 1.95 usec\n");
|
||||
#else
|
||||
NOTICE("BL2: DRAM refresh interval 3.9 usec\n");
|
||||
#endif
|
||||
|
||||
#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
|
||||
NOTICE("BL2: Periodic Write DQ Training\n");
|
||||
#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
|
||||
|
||||
io_write_32(QOSCTRL_RAS, 0x00000044U);
|
||||
io_write_64(QOSCTRL_DANN, 0x0404010002020201UL);
|
||||
io_write_32(QOSCTRL_DANT, 0x0020100AU);
|
||||
io_write_32(QOSCTRL_FSS, 0x0000000AU);
|
||||
io_write_32(QOSCTRL_INSFC, 0x06330001U);
|
||||
io_write_32(QOSCTRL_RACNT0, 0x00010003U);
|
||||
|
||||
/* GPU Boost Mode */
|
||||
io_write_32(QOSCTRL_STATGEN0, 0x00000001U);
|
||||
|
||||
io_write_32(QOSCTRL_SL_INIT,
|
||||
SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT |
|
||||
SL_INIT_SSLOTCLK_H3_30);
|
||||
io_write_32(QOSCTRL_REF_ARS,
|
||||
((QOSCTRL_REF_ARS_ARBSTOPCYCLE_H3_30 << 16)));
|
||||
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
|
||||
io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
|
||||
io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
|
||||
}
|
||||
for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
|
||||
io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
|
||||
io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
|
||||
}
|
||||
#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
|
||||
for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) {
|
||||
io_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8,
|
||||
qoswt_fix[i]);
|
||||
io_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8,
|
||||
qoswt_fix[i]);
|
||||
}
|
||||
for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) {
|
||||
io_write_64(QOSWT_BE_WTQOS_BANK0 + i * 8, qoswt_be[i]);
|
||||
io_write_64(QOSWT_BE_WTQOS_BANK1 + i * 8, qoswt_be[i]);
|
||||
}
|
||||
#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
|
||||
}
|
||||
|
||||
/* AXI setting */
|
||||
io_write_32(AXI_MMCR, 0x00010008U);
|
||||
io_write_32(AXI_TR3CR, 0x00010000U);
|
||||
io_write_32(AXI_TR4CR, 0x00010000U);
|
||||
|
||||
/* 3DG bus Leaf setting */
|
||||
|
||||
/* RT bus Leaf setting */
|
||||
io_write_32(RT_ACT0, 0x00000000U);
|
||||
io_write_32(RT_ACT1, 0x00000000U);
|
||||
|
||||
/* CCI bus Leaf setting */
|
||||
io_write_32(CPU_ACT0, 0x00000003U);
|
||||
io_write_32(CPU_ACT1, 0x00000003U);
|
||||
io_write_32(CPU_ACT2, 0x00000003U);
|
||||
io_write_32(CPU_ACT3, 0x00000003U);
|
||||
|
||||
io_write_32(QOSCTRL_RAEN, 0x00000001U);
|
||||
|
||||
#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
|
||||
/* re-write training setting */
|
||||
io_write_32(QOSWT_WTREF,
|
||||
((QOSWT_WTREF_SLOT1_EN << 16) | QOSWT_WTREF_SLOT0_EN));
|
||||
io_write_32(QOSWT_WTSET0,
|
||||
((QOSWT_WTSET0_PERIOD0_H3_30 << 16) |
|
||||
(QOSWT_WTSET0_SSLOT0 << 8) | QOSWT_WTSET0_SLOTSLOT0));
|
||||
io_write_32(QOSWT_WTSET1,
|
||||
((QOSWT_WTSET1_PERIOD1_H3_30 << 16) |
|
||||
(QOSWT_WTSET1_SSLOT1 << 8) | QOSWT_WTSET1_SLOTSLOT1));
|
||||
|
||||
io_write_32(QOSWT_WTEN, QOSWT_WTEN_ENABLE);
|
||||
#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
|
||||
|
||||
io_write_32(QOSCTRL_STATQC, 0x00000001U);
|
||||
#else
|
||||
NOTICE("BL2: QoS is None\n");
|
||||
|
||||
io_write_32(QOSCTRL_RAEN, 0x00000001U);
|
||||
#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
|
||||
}
|
12
drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30.h
Normal file
12
drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30.h
Normal file
|
@ -0,0 +1,12 @@
|
|||
/*
|
||||
* Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef QOS_INIT_H_H3_V30__
|
||||
#define QOS_INIT_H_H3_V30__
|
||||
|
||||
void qos_init_h3_v30(void);
|
||||
|
||||
#endif /* QOS_INIT_H_H3_V20__ */
|
231
drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30_mstat195.h
Normal file
231
drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30_mstat195.h
Normal file
|
@ -0,0 +1,231 @@
|
|||
/*
|
||||
* Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
static uint64_t mstat_fix[] = {
|
||||
/* 0x0000, */ 0x0000000000000000UL,
|
||||
/* 0x0008, */ 0x0000000000000000UL,
|
||||
/* 0x0010, */ 0x0000000000000000UL,
|
||||
/* 0x0018, */ 0x0000000000000000UL,
|
||||
/* 0x0020, */ 0x0000000000000000UL,
|
||||
/* 0x0028, */ 0x0000000000000000UL,
|
||||
/* 0x0030, */ 0x001004040000FFFFUL,
|
||||
/* 0x0038, */ 0x001008070000FFFFUL,
|
||||
/* 0x0040, */ 0x001410070000FFFFUL,
|
||||
/* 0x0048, */ 0x0000000000000000UL,
|
||||
/* 0x0050, */ 0x001404010000FFFFUL,
|
||||
/* 0x0058, */ 0x0014100D0000FFFFUL,
|
||||
/* 0x0060, */ 0x0014100D0000FFFFUL,
|
||||
/* 0x0068, */ 0x0000000000000000UL,
|
||||
/* 0x0070, */ 0x001404010000FFFFUL,
|
||||
/* 0x0078, */ 0x001008070000FFFFUL,
|
||||
/* 0x0080, */ 0x0000000000000000UL,
|
||||
/* 0x0088, */ 0x001410070000FFFFUL,
|
||||
/* 0x0090, */ 0x0014100D0000FFFFUL,
|
||||
/* 0x0098, */ 0x0000000000000000UL,
|
||||
/* 0x00a0, */ 0x000C04020000FFFFUL,
|
||||
/* 0x00a8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x00b0, */ 0x000C04010000FFFFUL,
|
||||
/* 0x00b8, */ 0x0000000000000000UL,
|
||||
/* 0x00c0, */ 0x000C04020000FFFFUL,
|
||||
/* 0x00c8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x00d0, */ 0x000C04010000FFFFUL,
|
||||
/* 0x00d8, */ 0x001024090000FFFFUL,
|
||||
/* 0x00e0, */ 0x00100C090000FFFFUL,
|
||||
/* 0x00e8, */ 0x0000000000000000UL,
|
||||
/* 0x00f0, */ 0x001024090000FFFFUL,
|
||||
/* 0x00f8, */ 0x000C08080000FFFFUL,
|
||||
/* 0x0100, */ 0x0000000000000000UL,
|
||||
/* 0x0108, */ 0x0000000000000000UL,
|
||||
/* 0x0110, */ 0x00100C090000FFFFUL,
|
||||
/* 0x0118, */ 0x000C18180000FFFFUL,
|
||||
/* 0x0120, */ 0x000C18180000FFFFUL,
|
||||
/* 0x0128, */ 0x0000000000000000UL,
|
||||
/* 0x0130, */ 0x0000000000000000UL,
|
||||
/* 0x0138, */ 0x00100C0B0000FFFFUL,
|
||||
/* 0x0140, */ 0x00100C0B0000FFFFUL,
|
||||
/* 0x0148, */ 0x0000000000000000UL,
|
||||
/* 0x0150, */ 0x0010100D0000FFFFUL,
|
||||
/* 0x0158, */ 0x0010100D0000FFFFUL,
|
||||
/* 0x0160, */ 0x00100C0B0000FFFFUL,
|
||||
/* 0x0168, */ 0x00100C0B0000FFFFUL,
|
||||
/* 0x0170, */ 0x0000000000000000UL,
|
||||
/* 0x0178, */ 0x001008060000FFFFUL,
|
||||
/* 0x0180, */ 0x001008060000FFFFUL,
|
||||
/* 0x0188, */ 0x0000000000000000UL,
|
||||
/* 0x0190, */ 0x00102C2C0000FFFFUL,
|
||||
/* 0x0198, */ 0x00102C2C0000FFFFUL,
|
||||
/* 0x01a0, */ 0x00100C0B0000FFFFUL,
|
||||
/* 0x01a8, */ 0x00100C0B0000FFFFUL,
|
||||
/* 0x01b0, */ 0x0000000000000000UL,
|
||||
/* 0x01b8, */ 0x0000000000000000UL,
|
||||
/* 0x01c0, */ 0x000C04010000FFFFUL,
|
||||
/* 0x01c8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x01d0, */ 0x000C04010000FFFFUL,
|
||||
/* 0x01d8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x01e0, */ 0x0000000000000000UL,
|
||||
/* 0x01e8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x01f0, */ 0x000C04010000FFFFUL,
|
||||
/* 0x01f8, */ 0x0000000000000000UL,
|
||||
/* 0x0200, */ 0x0000000000000000UL,
|
||||
/* 0x0208, */ 0x000C04010000FFFFUL,
|
||||
/* 0x0210, */ 0x000C04010000FFFFUL,
|
||||
/* 0x0218, */ 0x0000000000000000UL,
|
||||
/* 0x0220, */ 0x0000000000000000UL,
|
||||
/* 0x0228, */ 0x0000000000000000UL,
|
||||
/* 0x0230, */ 0x0000000000000000UL,
|
||||
/* 0x0238, */ 0x0000000000000000UL,
|
||||
/* 0x0240, */ 0x0000000000000000UL,
|
||||
/* 0x0248, */ 0x0000000000000000UL,
|
||||
/* 0x0250, */ 0x0000000000000000UL,
|
||||
/* 0x0258, */ 0x0000000000000000UL,
|
||||
/* 0x0260, */ 0x000C08020000FFFFUL,
|
||||
/* 0x0268, */ 0x001408010000FFFFUL,
|
||||
/* 0x0270, */ 0x001404010000FFFFUL,
|
||||
/* 0x0278, */ 0x000C04010000FFFFUL,
|
||||
/* 0x0280, */ 0x0000000000000000UL,
|
||||
/* 0x0288, */ 0x0000000000000000UL,
|
||||
/* 0x0290, */ 0x001408010000FFFFUL,
|
||||
/* 0x0298, */ 0x001404010000FFFFUL,
|
||||
/* 0x02a0, */ 0x000C04010000FFFFUL,
|
||||
/* 0x02a8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x02b0, */ 0x001408010000FFFFUL,
|
||||
/* 0x02b8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x02c0, */ 0x0000000000000000UL,
|
||||
/* 0x02c8, */ 0x0000000000000000UL,
|
||||
/* 0x02d0, */ 0x000C04010000FFFFUL,
|
||||
/* 0x02d8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x02e0, */ 0x001408010000FFFFUL,
|
||||
/* 0x02e8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x02f0, */ 0x0000000000000000UL,
|
||||
/* 0x02f8, */ 0x0000000000000000UL,
|
||||
/* 0x0300, */ 0x0000000000000000UL,
|
||||
/* 0x0308, */ 0x0000000000000000UL,
|
||||
/* 0x0310, */ 0x0000000000000000UL,
|
||||
/* 0x0318, */ 0x0000000000000000UL,
|
||||
/* 0x0320, */ 0x0000000000000000UL,
|
||||
/* 0x0328, */ 0x0000000000000000UL,
|
||||
/* 0x0330, */ 0x0000000000000000UL,
|
||||
/* 0x0338, */ 0x0000000000000000UL,
|
||||
/* 0x0340, */ 0x0000000000000000UL,
|
||||
/* 0x0348, */ 0x0000000000000000UL,
|
||||
/* 0x0350, */ 0x0000000000000000UL,
|
||||
/* 0x0358, */ 0x0000000000000000UL,
|
||||
/* 0x0360, */ 0x0000000000000000UL,
|
||||
/* 0x0368, */ 0x0000000000000000UL,
|
||||
};
|
||||
|
||||
static uint64_t mstat_be[] = {
|
||||
/* 0x0000, */ 0x001200600BDFFC01UL,
|
||||
/* 0x0008, */ 0x001200600BDFFC01UL,
|
||||
/* 0x0010, */ 0x001200600BDFFC01UL,
|
||||
/* 0x0018, */ 0x001200600BDFFC01UL,
|
||||
/* 0x0020, */ 0x0000000000000000UL,
|
||||
/* 0x0028, */ 0x001200100BD0FC01UL,
|
||||
/* 0x0030, */ 0x0000000000000000UL,
|
||||
/* 0x0038, */ 0x0000000000000000UL,
|
||||
/* 0x0040, */ 0x0000000000000000UL,
|
||||
/* 0x0048, */ 0x0000000000000000UL,
|
||||
/* 0x0050, */ 0x0000000000000000UL,
|
||||
/* 0x0058, */ 0x0000000000000000UL,
|
||||
/* 0x0060, */ 0x0000000000000000UL,
|
||||
/* 0x0068, */ 0x0000000000000000UL,
|
||||
/* 0x0070, */ 0x0000000000000000UL,
|
||||
/* 0x0078, */ 0x0000000000000000UL,
|
||||
/* 0x0080, */ 0x0000000000000000UL,
|
||||
/* 0x0088, */ 0x0000000000000000UL,
|
||||
/* 0x0090, */ 0x0000000000000000UL,
|
||||
/* 0x0098, */ 0x0000000000000000UL,
|
||||
/* 0x00a0, */ 0x0000000000000000UL,
|
||||
/* 0x00a8, */ 0x0000000000000000UL,
|
||||
/* 0x00b0, */ 0x0000000000000000UL,
|
||||
/* 0x00b8, */ 0x0000000000000000UL,
|
||||
/* 0x00c0, */ 0x0000000000000000UL,
|
||||
/* 0x00c8, */ 0x0000000000000000UL,
|
||||
/* 0x00d0, */ 0x0000000000000000UL,
|
||||
/* 0x00d8, */ 0x0000000000000000UL,
|
||||
/* 0x00e0, */ 0x0000000000000000UL,
|
||||
/* 0x00e8, */ 0x0000000000000000UL,
|
||||
/* 0x00f0, */ 0x0000000000000000UL,
|
||||
/* 0x00f8, */ 0x0000000000000000UL,
|
||||
/* 0x0100, */ 0x0000000000000000UL,
|
||||
/* 0x0108, */ 0x0000000000000000UL,
|
||||
/* 0x0110, */ 0x0000000000000000UL,
|
||||
/* 0x0118, */ 0x0000000000000000UL,
|
||||
/* 0x0120, */ 0x0000000000000000UL,
|
||||
/* 0x0128, */ 0x0000000000000000UL,
|
||||
/* 0x0130, */ 0x0000000000000000UL,
|
||||
/* 0x0138, */ 0x0000000000000000UL,
|
||||
/* 0x0140, */ 0x0000000000000000UL,
|
||||
/* 0x0148, */ 0x0000000000000000UL,
|
||||
/* 0x0150, */ 0x0000000000000000UL,
|
||||
/* 0x0158, */ 0x0000000000000000UL,
|
||||
/* 0x0160, */ 0x0000000000000000UL,
|
||||
/* 0x0168, */ 0x0000000000000000UL,
|
||||
/* 0x0170, */ 0x0000000000000000UL,
|
||||
/* 0x0178, */ 0x0000000000000000UL,
|
||||
/* 0x0180, */ 0x0000000000000000UL,
|
||||
/* 0x0188, */ 0x0000000000000000UL,
|
||||
/* 0x0190, */ 0x0000000000000000UL,
|
||||
/* 0x0198, */ 0x0000000000000000UL,
|
||||
/* 0x01a0, */ 0x0000000000000000UL,
|
||||
/* 0x01a8, */ 0x0000000000000000UL,
|
||||
/* 0x01b0, */ 0x0000000000000000UL,
|
||||
/* 0x01b8, */ 0x0000000000000000UL,
|
||||
/* 0x01c0, */ 0x002100600BDFFC01UL,
|
||||
/* 0x01c8, */ 0x002100600BDFFC01UL,
|
||||
/* 0x01d0, */ 0x002100600BDFFC01UL,
|
||||
/* 0x01d8, */ 0x002100600BDFFC01UL,
|
||||
/* 0x01e0, */ 0x0000000000000000UL,
|
||||
/* 0x01e8, */ 0x0000000000000000UL,
|
||||
/* 0x01f0, */ 0x002100100BDF2401UL,
|
||||
/* 0x01f8, */ 0x0000000000000000UL,
|
||||
/* 0x0200, */ 0x0000000000000000UL,
|
||||
/* 0x0208, */ 0x0000000000000000UL,
|
||||
/* 0x0210, */ 0x002100100BDF2401UL,
|
||||
/* 0x0218, */ 0x001100100BDF2401UL,
|
||||
/* 0x0220, */ 0x001100100BDF2401UL,
|
||||
/* 0x0228, */ 0x0000000000000000UL,
|
||||
/* 0x0230, */ 0x001100100BDF2401UL,
|
||||
/* 0x0238, */ 0x001100100BDF2401UL,
|
||||
/* 0x0240, */ 0x001200100BDF2401UL,
|
||||
/* 0x0248, */ 0x001100100BDF2401UL,
|
||||
/* 0x0250, */ 0x001200100BDF2401UL,
|
||||
/* 0x0258, */ 0x001100100BDF2401UL,
|
||||
/* 0x0260, */ 0x0000000000000000UL,
|
||||
/* 0x0268, */ 0x0000000000000000UL,
|
||||
/* 0x0270, */ 0x0000000000000000UL,
|
||||
/* 0x0278, */ 0x0000000000000000UL,
|
||||
/* 0x0280, */ 0x0000000000000000UL,
|
||||
/* 0x0288, */ 0x0000000000000000UL,
|
||||
/* 0x0290, */ 0x0000000000000000UL,
|
||||
/* 0x0298, */ 0x0000000000000000UL,
|
||||
/* 0x02a0, */ 0x0000000000000000UL,
|
||||
/* 0x02a8, */ 0x0000000000000000UL,
|
||||
/* 0x02b0, */ 0x0000000000000000UL,
|
||||
/* 0x02b8, */ 0x0000000000000000UL,
|
||||
/* 0x02c0, */ 0x0000000000000000UL,
|
||||
/* 0x02c8, */ 0x0000000000000000UL,
|
||||
/* 0x02d0, */ 0x0000000000000000UL,
|
||||
/* 0x02d8, */ 0x0000000000000000UL,
|
||||
/* 0x02e0, */ 0x0000000000000000UL,
|
||||
/* 0x02e8, */ 0x0000000000000000UL,
|
||||
/* 0x02f0, */ 0x001100600BDFFC01UL,
|
||||
/* 0x02f8, */ 0x001100600BDFFC01UL,
|
||||
/* 0x0300, */ 0x0000000000000000UL,
|
||||
/* 0x0308, */ 0x001100600BDFFC01UL,
|
||||
/* 0x0310, */ 0x001100600BDFFC01UL,
|
||||
/* 0x0318, */ 0x001200100BD03401UL,
|
||||
/* 0x0320, */ 0x001100600BDFFC01UL,
|
||||
/* 0x0328, */ 0x001100600BDFFC01UL,
|
||||
/* 0x0330, */ 0x001100600BDFFC01UL,
|
||||
/* 0x0338, */ 0x001100600BDFFC01UL,
|
||||
/* 0x0340, */ 0x0000000000000000UL,
|
||||
/* 0x0348, */ 0x0000000000000000UL,
|
||||
/* 0x0350, */ 0x0000000000000000UL,
|
||||
/* 0x0358, */ 0x0000000000000000UL,
|
||||
/* 0x0360, */ 0x0000000000000000UL,
|
||||
/* 0x0368, */ 0x001200100BD0FC01UL,
|
||||
};
|
231
drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30_mstat390.h
Normal file
231
drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30_mstat390.h
Normal file
|
@ -0,0 +1,231 @@
|
|||
/*
|
||||
* Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
static uint64_t mstat_fix[] = {
|
||||
/* 0x0000, */ 0x0000000000000000UL,
|
||||
/* 0x0008, */ 0x0000000000000000UL,
|
||||
/* 0x0010, */ 0x0000000000000000UL,
|
||||
/* 0x0018, */ 0x0000000000000000UL,
|
||||
/* 0x0020, */ 0x0000000000000000UL,
|
||||
/* 0x0028, */ 0x0000000000000000UL,
|
||||
/* 0x0030, */ 0x001008070000FFFFUL,
|
||||
/* 0x0038, */ 0x0010100D0000FFFFUL,
|
||||
/* 0x0040, */ 0x00141C0E0000FFFFUL,
|
||||
/* 0x0048, */ 0x0000000000000000UL,
|
||||
/* 0x0050, */ 0x001408010000FFFFUL,
|
||||
/* 0x0058, */ 0x00141C190000FFFFUL,
|
||||
/* 0x0060, */ 0x00141C190000FFFFUL,
|
||||
/* 0x0068, */ 0x0000000000000000UL,
|
||||
/* 0x0070, */ 0x001408010000FFFFUL,
|
||||
/* 0x0078, */ 0x0010100D0000FFFFUL,
|
||||
/* 0x0080, */ 0x0000000000000000UL,
|
||||
/* 0x0088, */ 0x00141C0E0000FFFFUL,
|
||||
/* 0x0090, */ 0x00141C190000FFFFUL,
|
||||
/* 0x0098, */ 0x0000000000000000UL,
|
||||
/* 0x00a0, */ 0x000C08040000FFFFUL,
|
||||
/* 0x00a8, */ 0x000C04020000FFFFUL,
|
||||
/* 0x00b0, */ 0x000C04020000FFFFUL,
|
||||
/* 0x00b8, */ 0x0000000000000000UL,
|
||||
/* 0x00c0, */ 0x000C08040000FFFFUL,
|
||||
/* 0x00c8, */ 0x000C04020000FFFFUL,
|
||||
/* 0x00d0, */ 0x000C04020000FFFFUL,
|
||||
/* 0x00d8, */ 0x001044110000FFFFUL,
|
||||
/* 0x00e0, */ 0x001014110000FFFFUL,
|
||||
/* 0x00e8, */ 0x0000000000000000UL,
|
||||
/* 0x00f0, */ 0x001044110000FFFFUL,
|
||||
/* 0x00f8, */ 0x000C10100000FFFFUL,
|
||||
/* 0x0100, */ 0x0000000000000000UL,
|
||||
/* 0x0108, */ 0x0000000000000000UL,
|
||||
/* 0x0110, */ 0x001014110000FFFFUL,
|
||||
/* 0x0118, */ 0x000C302F0000FFFFUL,
|
||||
/* 0x0120, */ 0x000C302F0000FFFFUL,
|
||||
/* 0x0128, */ 0x0000000000000000UL,
|
||||
/* 0x0130, */ 0x0000000000000000UL,
|
||||
/* 0x0138, */ 0x001018150000FFFFUL,
|
||||
/* 0x0140, */ 0x001018150000FFFFUL,
|
||||
/* 0x0148, */ 0x0000000000000000UL,
|
||||
/* 0x0150, */ 0x00101C190000FFFFUL,
|
||||
/* 0x0158, */ 0x00101C190000FFFFUL,
|
||||
/* 0x0160, */ 0x001018150000FFFFUL,
|
||||
/* 0x0168, */ 0x001018150000FFFFUL,
|
||||
/* 0x0170, */ 0x0000000000000000UL,
|
||||
/* 0x0178, */ 0x00100C0B0000FFFFUL,
|
||||
/* 0x0180, */ 0x00100C0B0000FFFFUL,
|
||||
/* 0x0188, */ 0x0000000000000000UL,
|
||||
/* 0x0190, */ 0x001058570000FFFFUL,
|
||||
/* 0x0198, */ 0x001058570000FFFFUL,
|
||||
/* 0x01a0, */ 0x001018150000FFFFUL,
|
||||
/* 0x01a8, */ 0x001018150000FFFFUL,
|
||||
/* 0x01b0, */ 0x0000000000000000UL,
|
||||
/* 0x01b8, */ 0x0000000000000000UL,
|
||||
/* 0x01c0, */ 0x000C04010000FFFFUL,
|
||||
/* 0x01c8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x01d0, */ 0x000C04010000FFFFUL,
|
||||
/* 0x01d8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x01e0, */ 0x0000000000000000UL,
|
||||
/* 0x01e8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x01f0, */ 0x000C04010000FFFFUL,
|
||||
/* 0x01f8, */ 0x0000000000000000UL,
|
||||
/* 0x0200, */ 0x0000000000000000UL,
|
||||
/* 0x0208, */ 0x000C04010000FFFFUL,
|
||||
/* 0x0210, */ 0x000C04010000FFFFUL,
|
||||
/* 0x0218, */ 0x0000000000000000UL,
|
||||
/* 0x0220, */ 0x0000000000000000UL,
|
||||
/* 0x0228, */ 0x0000000000000000UL,
|
||||
/* 0x0230, */ 0x0000000000000000UL,
|
||||
/* 0x0238, */ 0x0000000000000000UL,
|
||||
/* 0x0240, */ 0x0000000000000000UL,
|
||||
/* 0x0248, */ 0x0000000000000000UL,
|
||||
/* 0x0250, */ 0x0000000000000000UL,
|
||||
/* 0x0258, */ 0x0000000000000000UL,
|
||||
/* 0x0260, */ 0x000C0C030000FFFFUL,
|
||||
/* 0x0268, */ 0x001410010000FFFFUL,
|
||||
/* 0x0270, */ 0x001404010000FFFFUL,
|
||||
/* 0x0278, */ 0x000C08020000FFFFUL,
|
||||
/* 0x0280, */ 0x0000000000000000UL,
|
||||
/* 0x0288, */ 0x0000000000000000UL,
|
||||
/* 0x0290, */ 0x001410010000FFFFUL,
|
||||
/* 0x0298, */ 0x001404010000FFFFUL,
|
||||
/* 0x02a0, */ 0x000C04010000FFFFUL,
|
||||
/* 0x02a8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x02b0, */ 0x00140C010000FFFFUL,
|
||||
/* 0x02b8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x02c0, */ 0x0000000000000000UL,
|
||||
/* 0x02c8, */ 0x0000000000000000UL,
|
||||
/* 0x02d0, */ 0x000C04010000FFFFUL,
|
||||
/* 0x02d8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x02e0, */ 0x00140C010000FFFFUL,
|
||||
/* 0x02e8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x02f0, */ 0x0000000000000000UL,
|
||||
/* 0x02f8, */ 0x0000000000000000UL,
|
||||
/* 0x0300, */ 0x0000000000000000UL,
|
||||
/* 0x0308, */ 0x0000000000000000UL,
|
||||
/* 0x0310, */ 0x0000000000000000UL,
|
||||
/* 0x0318, */ 0x0000000000000000UL,
|
||||
/* 0x0320, */ 0x0000000000000000UL,
|
||||
/* 0x0328, */ 0x0000000000000000UL,
|
||||
/* 0x0330, */ 0x0000000000000000UL,
|
||||
/* 0x0338, */ 0x0000000000000000UL,
|
||||
/* 0x0340, */ 0x0000000000000000UL,
|
||||
/* 0x0348, */ 0x0000000000000000UL,
|
||||
/* 0x0350, */ 0x0000000000000000UL,
|
||||
/* 0x0358, */ 0x0000000000000000UL,
|
||||
/* 0x0360, */ 0x0000000000000000UL,
|
||||
/* 0x0368, */ 0x0000000000000000UL,
|
||||
};
|
||||
|
||||
static uint64_t mstat_be[] = {
|
||||
/* 0x0000, */ 0x0012006005EFFC01UL,
|
||||
/* 0x0008, */ 0x0012006005EFFC01UL,
|
||||
/* 0x0010, */ 0x0012006005EFFC01UL,
|
||||
/* 0x0018, */ 0x0012006005EFFC01UL,
|
||||
/* 0x0020, */ 0x0000000000000000UL,
|
||||
/* 0x0028, */ 0x0012001005E0FC01UL,
|
||||
/* 0x0030, */ 0x0000000000000000UL,
|
||||
/* 0x0038, */ 0x0000000000000000UL,
|
||||
/* 0x0040, */ 0x0000000000000000UL,
|
||||
/* 0x0048, */ 0x0000000000000000UL,
|
||||
/* 0x0050, */ 0x0000000000000000UL,
|
||||
/* 0x0058, */ 0x0000000000000000UL,
|
||||
/* 0x0060, */ 0x0000000000000000UL,
|
||||
/* 0x0068, */ 0x0000000000000000UL,
|
||||
/* 0x0070, */ 0x0000000000000000UL,
|
||||
/* 0x0078, */ 0x0000000000000000UL,
|
||||
/* 0x0080, */ 0x0000000000000000UL,
|
||||
/* 0x0088, */ 0x0000000000000000UL,
|
||||
/* 0x0090, */ 0x0000000000000000UL,
|
||||
/* 0x0098, */ 0x0000000000000000UL,
|
||||
/* 0x00a0, */ 0x0000000000000000UL,
|
||||
/* 0x00a8, */ 0x0000000000000000UL,
|
||||
/* 0x00b0, */ 0x0000000000000000UL,
|
||||
/* 0x00b8, */ 0x0000000000000000UL,
|
||||
/* 0x00c0, */ 0x0000000000000000UL,
|
||||
/* 0x00c8, */ 0x0000000000000000UL,
|
||||
/* 0x00d0, */ 0x0000000000000000UL,
|
||||
/* 0x00d8, */ 0x0000000000000000UL,
|
||||
/* 0x00e0, */ 0x0000000000000000UL,
|
||||
/* 0x00e8, */ 0x0000000000000000UL,
|
||||
/* 0x00f0, */ 0x0000000000000000UL,
|
||||
/* 0x00f8, */ 0x0000000000000000UL,
|
||||
/* 0x0100, */ 0x0000000000000000UL,
|
||||
/* 0x0108, */ 0x0000000000000000UL,
|
||||
/* 0x0110, */ 0x0000000000000000UL,
|
||||
/* 0x0118, */ 0x0000000000000000UL,
|
||||
/* 0x0120, */ 0x0000000000000000UL,
|
||||
/* 0x0128, */ 0x0000000000000000UL,
|
||||
/* 0x0130, */ 0x0000000000000000UL,
|
||||
/* 0x0138, */ 0x0000000000000000UL,
|
||||
/* 0x0140, */ 0x0000000000000000UL,
|
||||
/* 0x0148, */ 0x0000000000000000UL,
|
||||
/* 0x0150, */ 0x0000000000000000UL,
|
||||
/* 0x0158, */ 0x0000000000000000UL,
|
||||
/* 0x0160, */ 0x0000000000000000UL,
|
||||
/* 0x0168, */ 0x0000000000000000UL,
|
||||
/* 0x0170, */ 0x0000000000000000UL,
|
||||
/* 0x0178, */ 0x0000000000000000UL,
|
||||
/* 0x0180, */ 0x0000000000000000UL,
|
||||
/* 0x0188, */ 0x0000000000000000UL,
|
||||
/* 0x0190, */ 0x0000000000000000UL,
|
||||
/* 0x0198, */ 0x0000000000000000UL,
|
||||
/* 0x01a0, */ 0x0000000000000000UL,
|
||||
/* 0x01a8, */ 0x0000000000000000UL,
|
||||
/* 0x01b0, */ 0x0000000000000000UL,
|
||||
/* 0x01b8, */ 0x0000000000000000UL,
|
||||
/* 0x01c0, */ 0x0021006005EFFC01UL,
|
||||
/* 0x01c8, */ 0x0021006005EFFC01UL,
|
||||
/* 0x01d0, */ 0x0021006005EFFC01UL,
|
||||
/* 0x01d8, */ 0x0021006005EFFC01UL,
|
||||
/* 0x01e0, */ 0x0000000000000000UL,
|
||||
/* 0x01e8, */ 0x0000000000000000UL,
|
||||
/* 0x01f0, */ 0x0021001005E79401UL,
|
||||
/* 0x01f8, */ 0x0000000000000000UL,
|
||||
/* 0x0200, */ 0x0000000000000000UL,
|
||||
/* 0x0208, */ 0x0000000000000000UL,
|
||||
/* 0x0210, */ 0x0021001005E79401UL,
|
||||
/* 0x0218, */ 0x0011001005E79401UL,
|
||||
/* 0x0220, */ 0x0011001005E79401UL,
|
||||
/* 0x0228, */ 0x0000000000000000UL,
|
||||
/* 0x0230, */ 0x0011001005E79401UL,
|
||||
/* 0x0238, */ 0x0011001005E79401UL,
|
||||
/* 0x0240, */ 0x0012001005E79401UL,
|
||||
/* 0x0248, */ 0x0011001005E79401UL,
|
||||
/* 0x0250, */ 0x0012001005E79401UL,
|
||||
/* 0x0258, */ 0x0011001005E79401UL,
|
||||
/* 0x0260, */ 0x0000000000000000UL,
|
||||
/* 0x0268, */ 0x0000000000000000UL,
|
||||
/* 0x0270, */ 0x0000000000000000UL,
|
||||
/* 0x0278, */ 0x0000000000000000UL,
|
||||
/* 0x0280, */ 0x0000000000000000UL,
|
||||
/* 0x0288, */ 0x0000000000000000UL,
|
||||
/* 0x0290, */ 0x0000000000000000UL,
|
||||
/* 0x0298, */ 0x0000000000000000UL,
|
||||
/* 0x02a0, */ 0x0000000000000000UL,
|
||||
/* 0x02a8, */ 0x0000000000000000UL,
|
||||
/* 0x02b0, */ 0x0000000000000000UL,
|
||||
/* 0x02b8, */ 0x0000000000000000UL,
|
||||
/* 0x02c0, */ 0x0000000000000000UL,
|
||||
/* 0x02c8, */ 0x0000000000000000UL,
|
||||
/* 0x02d0, */ 0x0000000000000000UL,
|
||||
/* 0x02d8, */ 0x0000000000000000UL,
|
||||
/* 0x02e0, */ 0x0000000000000000UL,
|
||||
/* 0x02e8, */ 0x0000000000000000UL,
|
||||
/* 0x02f0, */ 0x0011006005EFFC01UL,
|
||||
/* 0x02f8, */ 0x0011006005EFFC01UL,
|
||||
/* 0x0300, */ 0x0000000000000000UL,
|
||||
/* 0x0308, */ 0x0011006005EFFC01UL,
|
||||
/* 0x0310, */ 0x0011006005EFFC01UL,
|
||||
/* 0x0318, */ 0x0012001005E03401UL,
|
||||
/* 0x0320, */ 0x0011006005EFFC01UL,
|
||||
/* 0x0328, */ 0x0011006005EFFC01UL,
|
||||
/* 0x0330, */ 0x0011006005EFFC01UL,
|
||||
/* 0x0338, */ 0x0011006005EFFC01UL,
|
||||
/* 0x0340, */ 0x0000000000000000UL,
|
||||
/* 0x0348, */ 0x0000000000000000UL,
|
||||
/* 0x0350, */ 0x0000000000000000UL,
|
||||
/* 0x0358, */ 0x0000000000000000UL,
|
||||
/* 0x0360, */ 0x0000000000000000UL,
|
||||
/* 0x0368, */ 0x0012001005E0FC01UL,
|
||||
};
|
231
drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30_qoswt195.h
Normal file
231
drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30_qoswt195.h
Normal file
|
@ -0,0 +1,231 @@
|
|||
/*
|
||||
* Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
static uint64_t qoswt_fix[] = {
|
||||
/* 0x0000, */ 0x0000000000000000UL,
|
||||
/* 0x0008, */ 0x0000000000000000UL,
|
||||
/* 0x0010, */ 0x0000000000000000UL,
|
||||
/* 0x0018, */ 0x0000000000000000UL,
|
||||
/* 0x0020, */ 0x0000000000000000UL,
|
||||
/* 0x0028, */ 0x0000000000000000UL,
|
||||
/* 0x0030, */ 0x001004040000C010UL,
|
||||
/* 0x0038, */ 0x001008070000C010UL,
|
||||
/* 0x0040, */ 0x001410070000FFF0UL,
|
||||
/* 0x0048, */ 0x0000000000000000UL,
|
||||
/* 0x0050, */ 0x0000000000000000UL,
|
||||
/* 0x0058, */ 0x0014100D0000C010UL,
|
||||
/* 0x0060, */ 0x0014100D0000C010UL,
|
||||
/* 0x0068, */ 0x0000000000000000UL,
|
||||
/* 0x0070, */ 0x0000000000000000UL,
|
||||
/* 0x0078, */ 0x001008070000C010UL,
|
||||
/* 0x0080, */ 0x0000000000000000UL,
|
||||
/* 0x0088, */ 0x001410070000FFF0UL,
|
||||
/* 0x0090, */ 0x0014100D0000C010UL,
|
||||
/* 0x0098, */ 0x0000000000000000UL,
|
||||
/* 0x00a0, */ 0x0000000000000000UL,
|
||||
/* 0x00a8, */ 0x0000000000000000UL,
|
||||
/* 0x00b0, */ 0x0000000000000000UL,
|
||||
/* 0x00b8, */ 0x0000000000000000UL,
|
||||
/* 0x00c0, */ 0x0000000000000000UL,
|
||||
/* 0x00c8, */ 0x0000000000000000UL,
|
||||
/* 0x00d0, */ 0x0000000000000000UL,
|
||||
/* 0x00d8, */ 0x0000000000000000UL,
|
||||
/* 0x00e0, */ 0x0000000000000000UL,
|
||||
/* 0x00e8, */ 0x0000000000000000UL,
|
||||
/* 0x00f0, */ 0x0000000000000000UL,
|
||||
/* 0x00f8, */ 0x0000000000000000UL,
|
||||
/* 0x0100, */ 0x0000000000000000UL,
|
||||
/* 0x0108, */ 0x0000000000000000UL,
|
||||
/* 0x0110, */ 0x0000000000000000UL,
|
||||
/* 0x0118, */ 0x0000000000000000UL,
|
||||
/* 0x0120, */ 0x0000000000000000UL,
|
||||
/* 0x0128, */ 0x0000000000000000UL,
|
||||
/* 0x0130, */ 0x0000000000000000UL,
|
||||
/* 0x0138, */ 0x0000000000000000UL,
|
||||
/* 0x0140, */ 0x0000000000000000UL,
|
||||
/* 0x0148, */ 0x0000000000000000UL,
|
||||
/* 0x0150, */ 0x0000000000000000UL,
|
||||
/* 0x0158, */ 0x0000000000000000UL,
|
||||
/* 0x0160, */ 0x0000000000000000UL,
|
||||
/* 0x0168, */ 0x0000000000000000UL,
|
||||
/* 0x0170, */ 0x0000000000000000UL,
|
||||
/* 0x0178, */ 0x0000000000000000UL,
|
||||
/* 0x0180, */ 0x0000000000000000UL,
|
||||
/* 0x0188, */ 0x0000000000000000UL,
|
||||
/* 0x0190, */ 0x0000000000000000UL,
|
||||
/* 0x0198, */ 0x0000000000000000UL,
|
||||
/* 0x01a0, */ 0x0000000000000000UL,
|
||||
/* 0x01a8, */ 0x0000000000000000UL,
|
||||
/* 0x01b0, */ 0x0000000000000000UL,
|
||||
/* 0x01b8, */ 0x0000000000000000UL,
|
||||
/* 0x01c0, */ 0x0000000000000000UL,
|
||||
/* 0x01c8, */ 0x0000000000000000UL,
|
||||
/* 0x01d0, */ 0x0000000000000000UL,
|
||||
/* 0x01d8, */ 0x0000000000000000UL,
|
||||
/* 0x01e0, */ 0x0000000000000000UL,
|
||||
/* 0x01e8, */ 0x0000000000000000UL,
|
||||
/* 0x01f0, */ 0x0000000000000000UL,
|
||||
/* 0x01f8, */ 0x0000000000000000UL,
|
||||
/* 0x0200, */ 0x0000000000000000UL,
|
||||
/* 0x0208, */ 0x0000000000000000UL,
|
||||
/* 0x0210, */ 0x0000000000000000UL,
|
||||
/* 0x0218, */ 0x0000000000000000UL,
|
||||
/* 0x0220, */ 0x0000000000000000UL,
|
||||
/* 0x0228, */ 0x0000000000000000UL,
|
||||
/* 0x0230, */ 0x0000000000000000UL,
|
||||
/* 0x0238, */ 0x0000000000000000UL,
|
||||
/* 0x0240, */ 0x0000000000000000UL,
|
||||
/* 0x0248, */ 0x0000000000000000UL,
|
||||
/* 0x0250, */ 0x0000000000000000UL,
|
||||
/* 0x0258, */ 0x0000000000000000UL,
|
||||
/* 0x0260, */ 0x000C08020000FFF0UL,
|
||||
/* 0x0268, */ 0x001408010000FFF0UL,
|
||||
/* 0x0270, */ 0x001404010000FFF0UL,
|
||||
/* 0x0278, */ 0x000C04010000FFF0UL,
|
||||
/* 0x0280, */ 0x0000000000000000UL,
|
||||
/* 0x0288, */ 0x0000000000000000UL,
|
||||
/* 0x0290, */ 0x001408010000FFF0UL,
|
||||
/* 0x0298, */ 0x001404010000FFF0UL,
|
||||
/* 0x02a0, */ 0x0000000000000000UL,
|
||||
/* 0x02a8, */ 0x0000000000000000UL,
|
||||
/* 0x02b0, */ 0x0000000000000000UL,
|
||||
/* 0x02b8, */ 0x0000000000000000UL,
|
||||
/* 0x02c0, */ 0x0000000000000000UL,
|
||||
/* 0x02c8, */ 0x0000000000000000UL,
|
||||
/* 0x02d0, */ 0x0000000000000000UL,
|
||||
/* 0x02d8, */ 0x0000000000000000UL,
|
||||
/* 0x02e0, */ 0x0000000000000000UL,
|
||||
/* 0x02e8, */ 0x0000000000000000UL,
|
||||
/* 0x02f0, */ 0x0000000000000000UL,
|
||||
/* 0x02f8, */ 0x0000000000000000UL,
|
||||
/* 0x0300, */ 0x0000000000000000UL,
|
||||
/* 0x0308, */ 0x0000000000000000UL,
|
||||
/* 0x0310, */ 0x0000000000000000UL,
|
||||
/* 0x0318, */ 0x0000000000000000UL,
|
||||
/* 0x0320, */ 0x0000000000000000UL,
|
||||
/* 0x0328, */ 0x0000000000000000UL,
|
||||
/* 0x0330, */ 0x0000000000000000UL,
|
||||
/* 0x0338, */ 0x0000000000000000UL,
|
||||
/* 0x0340, */ 0x0000000000000000UL,
|
||||
/* 0x0348, */ 0x0000000000000000UL,
|
||||
/* 0x0350, */ 0x0000000000000000UL,
|
||||
/* 0x0358, */ 0x0000000000000000UL,
|
||||
/* 0x0360, */ 0x0000000000000000UL,
|
||||
/* 0x0368, */ 0x0000000000000000UL,
|
||||
};
|
||||
|
||||
static uint64_t qoswt_be[] = {
|
||||
/* 0x0000, */ 0x0000000000000000UL,
|
||||
/* 0x0008, */ 0x0000000000000000UL,
|
||||
/* 0x0010, */ 0x0000000000000000UL,
|
||||
/* 0x0018, */ 0x0000000000000000UL,
|
||||
/* 0x0020, */ 0x0000000000000000UL,
|
||||
/* 0x0028, */ 0x0000000000000000UL,
|
||||
/* 0x0030, */ 0x0000000000000000UL,
|
||||
/* 0x0038, */ 0x0000000000000000UL,
|
||||
/* 0x0040, */ 0x0000000000000000UL,
|
||||
/* 0x0048, */ 0x0000000000000000UL,
|
||||
/* 0x0050, */ 0x0000000000000000UL,
|
||||
/* 0x0058, */ 0x0000000000000000UL,
|
||||
/* 0x0060, */ 0x0000000000000000UL,
|
||||
/* 0x0068, */ 0x0000000000000000UL,
|
||||
/* 0x0070, */ 0x0000000000000000UL,
|
||||
/* 0x0078, */ 0x0000000000000000UL,
|
||||
/* 0x0080, */ 0x0000000000000000UL,
|
||||
/* 0x0088, */ 0x0000000000000000UL,
|
||||
/* 0x0090, */ 0x0000000000000000UL,
|
||||
/* 0x0098, */ 0x0000000000000000UL,
|
||||
/* 0x00a0, */ 0x0000000000000000UL,
|
||||
/* 0x00a8, */ 0x0000000000000000UL,
|
||||
/* 0x00b0, */ 0x0000000000000000UL,
|
||||
/* 0x00b8, */ 0x0000000000000000UL,
|
||||
/* 0x00c0, */ 0x0000000000000000UL,
|
||||
/* 0x00c8, */ 0x0000000000000000UL,
|
||||
/* 0x00d0, */ 0x0000000000000000UL,
|
||||
/* 0x00d8, */ 0x0000000000000000UL,
|
||||
/* 0x00e0, */ 0x0000000000000000UL,
|
||||
/* 0x00e8, */ 0x0000000000000000UL,
|
||||
/* 0x00f0, */ 0x0000000000000000UL,
|
||||
/* 0x00f8, */ 0x0000000000000000UL,
|
||||
/* 0x0100, */ 0x0000000000000000UL,
|
||||
/* 0x0108, */ 0x0000000000000000UL,
|
||||
/* 0x0110, */ 0x0000000000000000UL,
|
||||
/* 0x0118, */ 0x0000000000000000UL,
|
||||
/* 0x0120, */ 0x0000000000000000UL,
|
||||
/* 0x0128, */ 0x0000000000000000UL,
|
||||
/* 0x0130, */ 0x0000000000000000UL,
|
||||
/* 0x0138, */ 0x0000000000000000UL,
|
||||
/* 0x0140, */ 0x0000000000000000UL,
|
||||
/* 0x0148, */ 0x0000000000000000UL,
|
||||
/* 0x0150, */ 0x0000000000000000UL,
|
||||
/* 0x0158, */ 0x0000000000000000UL,
|
||||
/* 0x0160, */ 0x0000000000000000UL,
|
||||
/* 0x0168, */ 0x0000000000000000UL,
|
||||
/* 0x0170, */ 0x0000000000000000UL,
|
||||
/* 0x0178, */ 0x0000000000000000UL,
|
||||
/* 0x0180, */ 0x0000000000000000UL,
|
||||
/* 0x0188, */ 0x0000000000000000UL,
|
||||
/* 0x0190, */ 0x0000000000000000UL,
|
||||
/* 0x0198, */ 0x0000000000000000UL,
|
||||
/* 0x01a0, */ 0x0000000000000000UL,
|
||||
/* 0x01a8, */ 0x0000000000000000UL,
|
||||
/* 0x01b0, */ 0x0000000000000000UL,
|
||||
/* 0x01b8, */ 0x0000000000000000UL,
|
||||
/* 0x01c0, */ 0x0000000000000000UL,
|
||||
/* 0x01c8, */ 0x0000000000000000UL,
|
||||
/* 0x01d0, */ 0x0000000000000000UL,
|
||||
/* 0x01d8, */ 0x0000000000000000UL,
|
||||
/* 0x01e0, */ 0x0000000000000000UL,
|
||||
/* 0x01e8, */ 0x0000000000000000UL,
|
||||
/* 0x01f0, */ 0x0000000000000000UL,
|
||||
/* 0x01f8, */ 0x0000000000000000UL,
|
||||
/* 0x0200, */ 0x0000000000000000UL,
|
||||
/* 0x0208, */ 0x0000000000000000UL,
|
||||
/* 0x0210, */ 0x0000000000000000UL,
|
||||
/* 0x0218, */ 0x0000000000000000UL,
|
||||
/* 0x0220, */ 0x0000000000000000UL,
|
||||
/* 0x0228, */ 0x0000000000000000UL,
|
||||
/* 0x0230, */ 0x0000000000000000UL,
|
||||
/* 0x0238, */ 0x0000000000000000UL,
|
||||
/* 0x0240, */ 0x0000000000000000UL,
|
||||
/* 0x0248, */ 0x0000000000000000UL,
|
||||
/* 0x0250, */ 0x0000000000000000UL,
|
||||
/* 0x0258, */ 0x0000000000000000UL,
|
||||
/* 0x0260, */ 0x0000000000000000UL,
|
||||
/* 0x0268, */ 0x0000000000000000UL,
|
||||
/* 0x0270, */ 0x0000000000000000UL,
|
||||
/* 0x0278, */ 0x0000000000000000UL,
|
||||
/* 0x0280, */ 0x0000000000000000UL,
|
||||
/* 0x0288, */ 0x0000000000000000UL,
|
||||
/* 0x0290, */ 0x0000000000000000UL,
|
||||
/* 0x0298, */ 0x0000000000000000UL,
|
||||
/* 0x02a0, */ 0x0000000000000000UL,
|
||||
/* 0x02a8, */ 0x0000000000000000UL,
|
||||
/* 0x02b0, */ 0x0000000000000000UL,
|
||||
/* 0x02b8, */ 0x0000000000000000UL,
|
||||
/* 0x02c0, */ 0x0000000000000000UL,
|
||||
/* 0x02c8, */ 0x0000000000000000UL,
|
||||
/* 0x02d0, */ 0x0000000000000000UL,
|
||||
/* 0x02d8, */ 0x0000000000000000UL,
|
||||
/* 0x02e0, */ 0x0000000000000000UL,
|
||||
/* 0x02e8, */ 0x0000000000000000UL,
|
||||
/* 0x02f0, */ 0x0000000000000000UL,
|
||||
/* 0x02f8, */ 0x0000000000000000UL,
|
||||
/* 0x0300, */ 0x0000000000000000UL,
|
||||
/* 0x0308, */ 0x0000000000000000UL,
|
||||
/* 0x0310, */ 0x0000000000000000UL,
|
||||
/* 0x0318, */ 0x0000000000000000UL,
|
||||
/* 0x0320, */ 0x0000000000000000UL,
|
||||
/* 0x0328, */ 0x0000000000000000UL,
|
||||
/* 0x0330, */ 0x0000000000000000UL,
|
||||
/* 0x0338, */ 0x0000000000000000UL,
|
||||
/* 0x0340, */ 0x0000000000000000UL,
|
||||
/* 0x0348, */ 0x0000000000000000UL,
|
||||
/* 0x0350, */ 0x0000000000000000UL,
|
||||
/* 0x0358, */ 0x0000000000000000UL,
|
||||
/* 0x0360, */ 0x0000000000000000UL,
|
||||
/* 0x0368, */ 0x0000000000000000UL,
|
||||
};
|
231
drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30_qoswt390.h
Normal file
231
drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30_qoswt390.h
Normal file
|
@ -0,0 +1,231 @@
|
|||
/*
|
||||
* Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
static uint64_t qoswt_fix[] = {
|
||||
/* 0x0000, */ 0x0000000000000000UL,
|
||||
/* 0x0008, */ 0x0000000000000000UL,
|
||||
/* 0x0010, */ 0x0000000000000000UL,
|
||||
/* 0x0018, */ 0x0000000000000000UL,
|
||||
/* 0x0020, */ 0x0000000000000000UL,
|
||||
/* 0x0028, */ 0x0000000000000000UL,
|
||||
/* 0x0030, */ 0x001008070000C010UL,
|
||||
/* 0x0038, */ 0x0010100D0000C010UL,
|
||||
/* 0x0040, */ 0x00141C0E0000FFF0UL,
|
||||
/* 0x0048, */ 0x0000000000000000UL,
|
||||
/* 0x0050, */ 0x0000000000000000UL,
|
||||
/* 0x0058, */ 0x00141C190000C010UL,
|
||||
/* 0x0060, */ 0x00141C190000C010UL,
|
||||
/* 0x0068, */ 0x0000000000000000UL,
|
||||
/* 0x0070, */ 0x0000000000000000UL,
|
||||
/* 0x0078, */ 0x0010100D0000C010UL,
|
||||
/* 0x0080, */ 0x0000000000000000UL,
|
||||
/* 0x0088, */ 0x00141C0E0000FFF0UL,
|
||||
/* 0x0090, */ 0x00141C190000C010UL,
|
||||
/* 0x0098, */ 0x0000000000000000UL,
|
||||
/* 0x00a0, */ 0x0000000000000000UL,
|
||||
/* 0x00a8, */ 0x0000000000000000UL,
|
||||
/* 0x00b0, */ 0x0000000000000000UL,
|
||||
/* 0x00b8, */ 0x0000000000000000UL,
|
||||
/* 0x00c0, */ 0x0000000000000000UL,
|
||||
/* 0x00c8, */ 0x0000000000000000UL,
|
||||
/* 0x00d0, */ 0x0000000000000000UL,
|
||||
/* 0x00d8, */ 0x0000000000000000UL,
|
||||
/* 0x00e0, */ 0x0000000000000000UL,
|
||||
/* 0x00e8, */ 0x0000000000000000UL,
|
||||
/* 0x00f0, */ 0x0000000000000000UL,
|
||||
/* 0x00f8, */ 0x0000000000000000UL,
|
||||
/* 0x0100, */ 0x0000000000000000UL,
|
||||
/* 0x0108, */ 0x0000000000000000UL,
|
||||
/* 0x0110, */ 0x0000000000000000UL,
|
||||
/* 0x0118, */ 0x0000000000000000UL,
|
||||
/* 0x0120, */ 0x0000000000000000UL,
|
||||
/* 0x0128, */ 0x0000000000000000UL,
|
||||
/* 0x0130, */ 0x0000000000000000UL,
|
||||
/* 0x0138, */ 0x0000000000000000UL,
|
||||
/* 0x0140, */ 0x0000000000000000UL,
|
||||
/* 0x0148, */ 0x0000000000000000UL,
|
||||
/* 0x0150, */ 0x0000000000000000UL,
|
||||
/* 0x0158, */ 0x0000000000000000UL,
|
||||
/* 0x0160, */ 0x0000000000000000UL,
|
||||
/* 0x0168, */ 0x0000000000000000UL,
|
||||
/* 0x0170, */ 0x0000000000000000UL,
|
||||
/* 0x0178, */ 0x0000000000000000UL,
|
||||
/* 0x0180, */ 0x0000000000000000UL,
|
||||
/* 0x0188, */ 0x0000000000000000UL,
|
||||
/* 0x0190, */ 0x0000000000000000UL,
|
||||
/* 0x0198, */ 0x0000000000000000UL,
|
||||
/* 0x01a0, */ 0x0000000000000000UL,
|
||||
/* 0x01a8, */ 0x0000000000000000UL,
|
||||
/* 0x01b0, */ 0x0000000000000000UL,
|
||||
/* 0x01b8, */ 0x0000000000000000UL,
|
||||
/* 0x01c0, */ 0x0000000000000000UL,
|
||||
/* 0x01c8, */ 0x0000000000000000UL,
|
||||
/* 0x01d0, */ 0x0000000000000000UL,
|
||||
/* 0x01d8, */ 0x0000000000000000UL,
|
||||
/* 0x01e0, */ 0x0000000000000000UL,
|
||||
/* 0x01e8, */ 0x0000000000000000UL,
|
||||
/* 0x01f0, */ 0x0000000000000000UL,
|
||||
/* 0x01f8, */ 0x0000000000000000UL,
|
||||
/* 0x0200, */ 0x0000000000000000UL,
|
||||
/* 0x0208, */ 0x0000000000000000UL,
|
||||
/* 0x0210, */ 0x0000000000000000UL,
|
||||
/* 0x0218, */ 0x0000000000000000UL,
|
||||
/* 0x0220, */ 0x0000000000000000UL,
|
||||
/* 0x0228, */ 0x0000000000000000UL,
|
||||
/* 0x0230, */ 0x0000000000000000UL,
|
||||
/* 0x0238, */ 0x0000000000000000UL,
|
||||
/* 0x0240, */ 0x0000000000000000UL,
|
||||
/* 0x0248, */ 0x0000000000000000UL,
|
||||
/* 0x0250, */ 0x0000000000000000UL,
|
||||
/* 0x0258, */ 0x0000000000000000UL,
|
||||
/* 0x0260, */ 0x000C0C030000FFF0UL,
|
||||
/* 0x0268, */ 0x001410010000FFF0UL,
|
||||
/* 0x0270, */ 0x001404010000FFF0UL,
|
||||
/* 0x0278, */ 0x000C08020000FFF0UL,
|
||||
/* 0x0280, */ 0x0000000000000000UL,
|
||||
/* 0x0288, */ 0x0000000000000000UL,
|
||||
/* 0x0290, */ 0x001410010000FFF0UL,
|
||||
/* 0x0298, */ 0x001404010000FFF0UL,
|
||||
/* 0x02a0, */ 0x0000000000000000UL,
|
||||
/* 0x02a8, */ 0x0000000000000000UL,
|
||||
/* 0x02b0, */ 0x0000000000000000UL,
|
||||
/* 0x02b8, */ 0x0000000000000000UL,
|
||||
/* 0x02c0, */ 0x0000000000000000UL,
|
||||
/* 0x02c8, */ 0x0000000000000000UL,
|
||||
/* 0x02d0, */ 0x0000000000000000UL,
|
||||
/* 0x02d8, */ 0x0000000000000000UL,
|
||||
/* 0x02e0, */ 0x0000000000000000UL,
|
||||
/* 0x02e8, */ 0x0000000000000000UL,
|
||||
/* 0x02f0, */ 0x0000000000000000UL,
|
||||
/* 0x02f8, */ 0x0000000000000000UL,
|
||||
/* 0x0300, */ 0x0000000000000000UL,
|
||||
/* 0x0308, */ 0x0000000000000000UL,
|
||||
/* 0x0310, */ 0x0000000000000000UL,
|
||||
/* 0x0318, */ 0x0000000000000000UL,
|
||||
/* 0x0320, */ 0x0000000000000000UL,
|
||||
/* 0x0328, */ 0x0000000000000000UL,
|
||||
/* 0x0330, */ 0x0000000000000000UL,
|
||||
/* 0x0338, */ 0x0000000000000000UL,
|
||||
/* 0x0340, */ 0x0000000000000000UL,
|
||||
/* 0x0348, */ 0x0000000000000000UL,
|
||||
/* 0x0350, */ 0x0000000000000000UL,
|
||||
/* 0x0358, */ 0x0000000000000000UL,
|
||||
/* 0x0360, */ 0x0000000000000000UL,
|
||||
/* 0x0368, */ 0x0000000000000000UL,
|
||||
};
|
||||
|
||||
static uint64_t qoswt_be[] = {
|
||||
/* 0x0000, */ 0x0000000000000000UL,
|
||||
/* 0x0008, */ 0x0000000000000000UL,
|
||||
/* 0x0010, */ 0x0000000000000000UL,
|
||||
/* 0x0018, */ 0x0000000000000000UL,
|
||||
/* 0x0020, */ 0x0000000000000000UL,
|
||||
/* 0x0028, */ 0x0000000000000000UL,
|
||||
/* 0x0030, */ 0x0000000000000000UL,
|
||||
/* 0x0038, */ 0x0000000000000000UL,
|
||||
/* 0x0040, */ 0x0000000000000000UL,
|
||||
/* 0x0048, */ 0x0000000000000000UL,
|
||||
/* 0x0050, */ 0x0000000000000000UL,
|
||||
/* 0x0058, */ 0x0000000000000000UL,
|
||||
/* 0x0060, */ 0x0000000000000000UL,
|
||||
/* 0x0068, */ 0x0000000000000000UL,
|
||||
/* 0x0070, */ 0x0000000000000000UL,
|
||||
/* 0x0078, */ 0x0000000000000000UL,
|
||||
/* 0x0080, */ 0x0000000000000000UL,
|
||||
/* 0x0088, */ 0x0000000000000000UL,
|
||||
/* 0x0090, */ 0x0000000000000000UL,
|
||||
/* 0x0098, */ 0x0000000000000000UL,
|
||||
/* 0x00a0, */ 0x0000000000000000UL,
|
||||
/* 0x00a8, */ 0x0000000000000000UL,
|
||||
/* 0x00b0, */ 0x0000000000000000UL,
|
||||
/* 0x00b8, */ 0x0000000000000000UL,
|
||||
/* 0x00c0, */ 0x0000000000000000UL,
|
||||
/* 0x00c8, */ 0x0000000000000000UL,
|
||||
/* 0x00d0, */ 0x0000000000000000UL,
|
||||
/* 0x00d8, */ 0x0000000000000000UL,
|
||||
/* 0x00e0, */ 0x0000000000000000UL,
|
||||
/* 0x00e8, */ 0x0000000000000000UL,
|
||||
/* 0x00f0, */ 0x0000000000000000UL,
|
||||
/* 0x00f8, */ 0x0000000000000000UL,
|
||||
/* 0x0100, */ 0x0000000000000000UL,
|
||||
/* 0x0108, */ 0x0000000000000000UL,
|
||||
/* 0x0110, */ 0x0000000000000000UL,
|
||||
/* 0x0118, */ 0x0000000000000000UL,
|
||||
/* 0x0120, */ 0x0000000000000000UL,
|
||||
/* 0x0128, */ 0x0000000000000000UL,
|
||||
/* 0x0130, */ 0x0000000000000000UL,
|
||||
/* 0x0138, */ 0x0000000000000000UL,
|
||||
/* 0x0140, */ 0x0000000000000000UL,
|
||||
/* 0x0148, */ 0x0000000000000000UL,
|
||||
/* 0x0150, */ 0x0000000000000000UL,
|
||||
/* 0x0158, */ 0x0000000000000000UL,
|
||||
/* 0x0160, */ 0x0000000000000000UL,
|
||||
/* 0x0168, */ 0x0000000000000000UL,
|
||||
/* 0x0170, */ 0x0000000000000000UL,
|
||||
/* 0x0178, */ 0x0000000000000000UL,
|
||||
/* 0x0180, */ 0x0000000000000000UL,
|
||||
/* 0x0188, */ 0x0000000000000000UL,
|
||||
/* 0x0190, */ 0x0000000000000000UL,
|
||||
/* 0x0198, */ 0x0000000000000000UL,
|
||||
/* 0x01a0, */ 0x0000000000000000UL,
|
||||
/* 0x01a8, */ 0x0000000000000000UL,
|
||||
/* 0x01b0, */ 0x0000000000000000UL,
|
||||
/* 0x01b8, */ 0x0000000000000000UL,
|
||||
/* 0x01c0, */ 0x0000000000000000UL,
|
||||
/* 0x01c8, */ 0x0000000000000000UL,
|
||||
/* 0x01d0, */ 0x0000000000000000UL,
|
||||
/* 0x01d8, */ 0x0000000000000000UL,
|
||||
/* 0x01e0, */ 0x0000000000000000UL,
|
||||
/* 0x01e8, */ 0x0000000000000000UL,
|
||||
/* 0x01f0, */ 0x0000000000000000UL,
|
||||
/* 0x01f8, */ 0x0000000000000000UL,
|
||||
/* 0x0200, */ 0x0000000000000000UL,
|
||||
/* 0x0208, */ 0x0000000000000000UL,
|
||||
/* 0x0210, */ 0x0000000000000000UL,
|
||||
/* 0x0218, */ 0x0000000000000000UL,
|
||||
/* 0x0220, */ 0x0000000000000000UL,
|
||||
/* 0x0228, */ 0x0000000000000000UL,
|
||||
/* 0x0230, */ 0x0000000000000000UL,
|
||||
/* 0x0238, */ 0x0000000000000000UL,
|
||||
/* 0x0240, */ 0x0000000000000000UL,
|
||||
/* 0x0248, */ 0x0000000000000000UL,
|
||||
/* 0x0250, */ 0x0000000000000000UL,
|
||||
/* 0x0258, */ 0x0000000000000000UL,
|
||||
/* 0x0260, */ 0x0000000000000000UL,
|
||||
/* 0x0268, */ 0x0000000000000000UL,
|
||||
/* 0x0270, */ 0x0000000000000000UL,
|
||||
/* 0x0278, */ 0x0000000000000000UL,
|
||||
/* 0x0280, */ 0x0000000000000000UL,
|
||||
/* 0x0288, */ 0x0000000000000000UL,
|
||||
/* 0x0290, */ 0x0000000000000000UL,
|
||||
/* 0x0298, */ 0x0000000000000000UL,
|
||||
/* 0x02a0, */ 0x0000000000000000UL,
|
||||
/* 0x02a8, */ 0x0000000000000000UL,
|
||||
/* 0x02b0, */ 0x0000000000000000UL,
|
||||
/* 0x02b8, */ 0x0000000000000000UL,
|
||||
/* 0x02c0, */ 0x0000000000000000UL,
|
||||
/* 0x02c8, */ 0x0000000000000000UL,
|
||||
/* 0x02d0, */ 0x0000000000000000UL,
|
||||
/* 0x02d8, */ 0x0000000000000000UL,
|
||||
/* 0x02e0, */ 0x0000000000000000UL,
|
||||
/* 0x02e8, */ 0x0000000000000000UL,
|
||||
/* 0x02f0, */ 0x0000000000000000UL,
|
||||
/* 0x02f8, */ 0x0000000000000000UL,
|
||||
/* 0x0300, */ 0x0000000000000000UL,
|
||||
/* 0x0308, */ 0x0000000000000000UL,
|
||||
/* 0x0310, */ 0x0000000000000000UL,
|
||||
/* 0x0318, */ 0x0000000000000000UL,
|
||||
/* 0x0320, */ 0x0000000000000000UL,
|
||||
/* 0x0328, */ 0x0000000000000000UL,
|
||||
/* 0x0330, */ 0x0000000000000000UL,
|
||||
/* 0x0338, */ 0x0000000000000000UL,
|
||||
/* 0x0340, */ 0x0000000000000000UL,
|
||||
/* 0x0348, */ 0x0000000000000000UL,
|
||||
/* 0x0350, */ 0x0000000000000000UL,
|
||||
/* 0x0358, */ 0x0000000000000000UL,
|
||||
/* 0x0360, */ 0x0000000000000000UL,
|
||||
/* 0x0368, */ 0x0000000000000000UL,
|
||||
};
|
261
drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30.c
Normal file
261
drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30.c
Normal file
|
@ -0,0 +1,261 @@
|
|||
/*
|
||||
* Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <debug.h>
|
||||
#include "../qos_common.h"
|
||||
#include "../qos_reg.h"
|
||||
#include "qos_init_h3n_v30.h"
|
||||
|
||||
#define RCAR_QOS_VERSION "rev.0.03"
|
||||
|
||||
#define QOSCTRL_FSS (QOS_BASE1 + 0x0048U)
|
||||
|
||||
#define QOSWT_TIME_BANK0 (20000000U) /* unit:ns */
|
||||
|
||||
#define QOSWT_WTEN_ENABLE (0x1U)
|
||||
|
||||
#define QOSCTRL_REF_ARS_ARBSTOPCYCLE_H3N (SL_INIT_SSLOTCLK_H3N - 0x5U)
|
||||
|
||||
#define OSWT_WTREF_SLOT0_EN_REQ1_SLOT (3U)
|
||||
#define OSWT_WTREF_SLOT0_EN_REQ2_SLOT (9U)
|
||||
#define QOSWT_WTREF_SLOT0_EN ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
|
||||
#define QOSWT_WTREF_SLOT1_EN ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
|
||||
|
||||
#define QOSWT_WTSET0_REQ_SSLOT0 (5U)
|
||||
#define WT_BASE_SUB_SLOT_NUM0 (12U)
|
||||
#define QOSWT_WTSET0_PERIOD0_H3N ((QOSWT_TIME_BANK0/QOSWT_WTSET0_CYCLE_H3N)-1U)
|
||||
#define QOSWT_WTSET0_SSLOT0 (QOSWT_WTSET0_REQ_SSLOT0 -1U)
|
||||
#define QOSWT_WTSET0_SLOTSLOT0 (WT_BASE_SUB_SLOT_NUM0 -1U)
|
||||
|
||||
#define QOSWT_WTSET1_PERIOD1_H3N (QOSWT_WTSET0_PERIOD0_H3N)
|
||||
#define QOSWT_WTSET1_SSLOT1 (QOSWT_WTSET0_SSLOT0)
|
||||
#define QOSWT_WTSET1_SLOTSLOT1 (QOSWT_WTSET0_SLOTSLOT0)
|
||||
|
||||
#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
|
||||
|
||||
#if RCAR_REF_INT == RCAR_REF_DEFAULT
|
||||
#include "qos_init_h3n_v30_mstat195.h"
|
||||
#else
|
||||
#include "qos_init_h3n_v30_mstat390.h"
|
||||
#endif
|
||||
|
||||
#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
|
||||
|
||||
#if RCAR_REF_INT == RCAR_REF_DEFAULT
|
||||
#include "qos_init_h3n_v30_qoswt195.h"
|
||||
#else
|
||||
#include "qos_init_h3n_v30_qoswt390.h"
|
||||
#endif
|
||||
|
||||
#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
|
||||
|
||||
#endif
|
||||
|
||||
static void dbsc_setting(void)
|
||||
{
|
||||
uint32_t md = 0;
|
||||
|
||||
/* Register write enable */
|
||||
io_write_32(DBSC_DBSYSCNT0, 0x00001234U);
|
||||
|
||||
/* BUFCAM settings */
|
||||
io_write_32(DBSC_DBCAM0CNF1, 0x00043218U); /* dbcam0cnf1 */
|
||||
io_write_32(DBSC_DBCAM0CNF2, 0x000000F4U); /* dbcam0cnf2 */
|
||||
io_write_32(DBSC_DBCAM0CNF3, 0x00000000U); /* dbcam0cnf3 */
|
||||
io_write_32(DBSC_DBSCHCNT0, 0x000F0037U); /* dbschcnt0 */
|
||||
io_write_32(DBSC_DBSCHSZ0, 0x00000001U); /* dbschsz0 */
|
||||
io_write_32(DBSC_DBSCHRW0, 0x22421111U); /* dbschrw0 */
|
||||
|
||||
md = (*((volatile uint32_t *)RST_MODEMR) & 0x000A0000) >> 17;
|
||||
|
||||
switch (md) {
|
||||
case 0x0:
|
||||
/* DDR3200 */
|
||||
io_write_32(DBSC_SCFCTST2, 0x012F1123U);
|
||||
break;
|
||||
case 0x1: /* MD19=0,MD17=1 : LPDDR4-3000, 4GByte(1GByte x4) */
|
||||
/* DDR2800 */
|
||||
io_write_32(DBSC_SCFCTST2, 0x012F1123U);
|
||||
break;
|
||||
case 0x4: /* MD19=1,MD17=0 : LPDDR4-2400, 4GByte(1GByte x4) */
|
||||
/* DDR2400 */
|
||||
io_write_32(DBSC_SCFCTST2, 0x012F1123U);
|
||||
break;
|
||||
default: /* MD19=1,MD17=1 : LPDDR4-1600, 4GByte(1GByte x4) */
|
||||
/* DDR1600 */
|
||||
io_write_32(DBSC_SCFCTST2, 0x012F1123U);
|
||||
break;
|
||||
}
|
||||
|
||||
/* QoS Settings */
|
||||
io_write_32(DBSC_DBSCHQOS00, 0x00000F00U);
|
||||
io_write_32(DBSC_DBSCHQOS01, 0x00000B00U);
|
||||
io_write_32(DBSC_DBSCHQOS02, 0x00000000U);
|
||||
io_write_32(DBSC_DBSCHQOS03, 0x00000000U);
|
||||
io_write_32(DBSC_DBSCHQOS40, 0x00000300U);
|
||||
io_write_32(DBSC_DBSCHQOS41, 0x000002F0U);
|
||||
io_write_32(DBSC_DBSCHQOS42, 0x00000200U);
|
||||
io_write_32(DBSC_DBSCHQOS43, 0x00000100U);
|
||||
io_write_32(DBSC_DBSCHQOS90, 0x00000100U);
|
||||
io_write_32(DBSC_DBSCHQOS91, 0x000000F0U);
|
||||
io_write_32(DBSC_DBSCHQOS92, 0x000000A0U);
|
||||
io_write_32(DBSC_DBSCHQOS93, 0x00000040U);
|
||||
io_write_32(DBSC_DBSCHQOS120, 0x00000040U);
|
||||
io_write_32(DBSC_DBSCHQOS121, 0x00000030U);
|
||||
io_write_32(DBSC_DBSCHQOS122, 0x00000020U);
|
||||
io_write_32(DBSC_DBSCHQOS123, 0x00000010U);
|
||||
io_write_32(DBSC_DBSCHQOS130, 0x00000100U);
|
||||
io_write_32(DBSC_DBSCHQOS131, 0x000000F0U);
|
||||
io_write_32(DBSC_DBSCHQOS132, 0x000000A0U);
|
||||
io_write_32(DBSC_DBSCHQOS133, 0x00000040U);
|
||||
io_write_32(DBSC_DBSCHQOS140, 0x000000C0U);
|
||||
io_write_32(DBSC_DBSCHQOS141, 0x000000B0U);
|
||||
io_write_32(DBSC_DBSCHQOS142, 0x00000080U);
|
||||
io_write_32(DBSC_DBSCHQOS143, 0x00000040U);
|
||||
io_write_32(DBSC_DBSCHQOS150, 0x00000040U);
|
||||
io_write_32(DBSC_DBSCHQOS151, 0x00000030U);
|
||||
io_write_32(DBSC_DBSCHQOS152, 0x00000020U);
|
||||
io_write_32(DBSC_DBSCHQOS153, 0x00000010U);
|
||||
|
||||
/* Register write protect */
|
||||
io_write_32(DBSC_DBSYSCNT0, 0x00000000U);
|
||||
}
|
||||
|
||||
void qos_init_h3n_v30(void)
|
||||
{
|
||||
unsigned int split_area;
|
||||
dbsc_setting();
|
||||
|
||||
/* use 1(2GB) for RCAR_DRAM_LPDDR4_MEMCONF for H3N */
|
||||
split_area = 0x1CU;
|
||||
|
||||
/* DRAM Split Address mapping */
|
||||
#if (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH)
|
||||
#if RCAR_LSI == RCAR_H3N
|
||||
#error "Don't set DRAM Split 4ch(H3N)"
|
||||
#else
|
||||
ERROR("DRAM Split 4ch not supported.(H3N)");
|
||||
panic();
|
||||
#endif
|
||||
#elif (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH) || \
|
||||
(RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO)
|
||||
NOTICE("BL2: DRAM Split is 2ch(DDR %x)\n", (int)qos_init_ddr_phyvalid);
|
||||
|
||||
io_write_32(AXI_ADSPLCR0, ADSPLCR0_AREA(split_area));
|
||||
io_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT
|
||||
| ADSPLCR0_SPLITSEL(0xFFU)
|
||||
| ADSPLCR0_AREA(split_area)
|
||||
| ADSPLCR0_SWP);
|
||||
io_write_32(AXI_ADSPLCR2, 0x00001004U);
|
||||
io_write_32(AXI_ADSPLCR3, 0x00000000U);
|
||||
#else
|
||||
io_write_32(AXI_ADSPLCR0, ADSPLCR0_AREA(split_area));
|
||||
NOTICE("BL2: DRAM Split is OFF(DDR %x)\n", (int)qos_init_ddr_phyvalid);
|
||||
#endif
|
||||
|
||||
#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
|
||||
#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
|
||||
NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
|
||||
#endif
|
||||
|
||||
#if RCAR_REF_INT == RCAR_REF_DEFAULT
|
||||
NOTICE("BL2: DRAM refresh interval 1.95 usec\n");
|
||||
#else
|
||||
NOTICE("BL2: DRAM refresh interval 3.9 usec\n");
|
||||
#endif
|
||||
|
||||
#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
|
||||
NOTICE("BL2: Periodic Write DQ Training\n");
|
||||
#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
|
||||
|
||||
io_write_32(QOSCTRL_RAS, 0x00000044U);
|
||||
io_write_64(QOSCTRL_DANN, 0x0404020002020201UL);
|
||||
io_write_32(QOSCTRL_DANT, 0x0020100AU);
|
||||
io_write_32(QOSCTRL_FSS, 0x0000000AU);
|
||||
io_write_32(QOSCTRL_INSFC, 0x06330001U);
|
||||
io_write_32(QOSCTRL_RACNT0, 0x00010003U);
|
||||
|
||||
/* GPU Boost Mode */
|
||||
io_write_32(QOSCTRL_STATGEN0, 0x00000001U);
|
||||
|
||||
io_write_32(QOSCTRL_SL_INIT,
|
||||
SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT |
|
||||
SL_INIT_SSLOTCLK_H3N);
|
||||
io_write_32(QOSCTRL_REF_ARS,
|
||||
((QOSCTRL_REF_ARS_ARBSTOPCYCLE_H3N << 16)));
|
||||
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
|
||||
io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
|
||||
io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
|
||||
}
|
||||
for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
|
||||
io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
|
||||
io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
|
||||
}
|
||||
#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
|
||||
for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) {
|
||||
io_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8,
|
||||
qoswt_fix[i]);
|
||||
io_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8,
|
||||
qoswt_fix[i]);
|
||||
}
|
||||
for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) {
|
||||
io_write_64(QOSWT_BE_WTQOS_BANK0 + i * 8, qoswt_be[i]);
|
||||
io_write_64(QOSWT_BE_WTQOS_BANK1 + i * 8, qoswt_be[i]);
|
||||
}
|
||||
#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
|
||||
}
|
||||
|
||||
/* AXI setting */
|
||||
io_write_32(AXI_MMCR, 0x00010008U);
|
||||
io_write_32(AXI_TR3CR, 0x00010000U);
|
||||
io_write_32(AXI_TR4CR, 0x00010000U);
|
||||
|
||||
/* 3DG bus Leaf setting */
|
||||
io_write_32(GPU_ACT_GRD, 0x00001234U);
|
||||
io_write_32(GPU_ACT0, 0x00000000U);
|
||||
io_write_32(GPU_ACT1, 0x00000000U);
|
||||
io_write_32(GPU_ACT2, 0x00000000U);
|
||||
io_write_32(GPU_ACT3, 0x00000000U);
|
||||
io_write_32(GPU_ACT_GRD, 0x00000000U);
|
||||
|
||||
/* RT bus Leaf setting */
|
||||
io_write_32(RT_ACT0, 0x00000000U);
|
||||
io_write_32(RT_ACT1, 0x00000000U);
|
||||
|
||||
/* CCI bus Leaf setting */
|
||||
io_write_32(CPU_ACT0, 0x00000003U);
|
||||
io_write_32(CPU_ACT1, 0x00000003U);
|
||||
io_write_32(CPU_ACT2, 0x00000003U);
|
||||
io_write_32(CPU_ACT3, 0x00000003U);
|
||||
|
||||
io_write_32(QOSCTRL_RAEN, 0x00000001U);
|
||||
|
||||
#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
|
||||
/* re-write training setting */
|
||||
io_write_32(QOSWT_WTREF,
|
||||
((QOSWT_WTREF_SLOT1_EN << 16) | QOSWT_WTREF_SLOT0_EN));
|
||||
io_write_32(QOSWT_WTSET0,
|
||||
((QOSWT_WTSET0_PERIOD0_H3N << 16) |
|
||||
(QOSWT_WTSET0_SSLOT0 << 8) | QOSWT_WTSET0_SLOTSLOT0));
|
||||
io_write_32(QOSWT_WTSET1,
|
||||
((QOSWT_WTSET1_PERIOD1_H3N << 16) |
|
||||
(QOSWT_WTSET1_SSLOT1 << 8) | QOSWT_WTSET1_SLOTSLOT1));
|
||||
|
||||
io_write_32(QOSWT_WTEN, QOSWT_WTEN_ENABLE);
|
||||
#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
|
||||
|
||||
io_write_32(QOSCTRL_STATQC, 0x00000001U);
|
||||
#else
|
||||
NOTICE("BL2: QoS is None\n");
|
||||
|
||||
io_write_32(QOSCTRL_RAEN, 0x00000001U);
|
||||
#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
|
||||
}
|
12
drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30.h
Normal file
12
drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30.h
Normal file
|
@ -0,0 +1,12 @@
|
|||
/*
|
||||
* Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef QOS_INIT_H_H3N_V30__
|
||||
#define QOS_INIT_H_H3N_V30__
|
||||
|
||||
void qos_init_h3n_v30(void);
|
||||
|
||||
#endif /* QOS_INIT_H_H3N_V30__ */
|
231
drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30_mstat195.h
Normal file
231
drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30_mstat195.h
Normal file
|
@ -0,0 +1,231 @@
|
|||
/*
|
||||
* Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
static uint64_t mstat_fix[] = {
|
||||
/* 0x0000, */ 0x0000000000000000UL,
|
||||
/* 0x0008, */ 0x0000000000000000UL,
|
||||
/* 0x0010, */ 0x0000000000000000UL,
|
||||
/* 0x0018, */ 0x0000000000000000UL,
|
||||
/* 0x0020, */ 0x0000000000000000UL,
|
||||
/* 0x0028, */ 0x0000000000000000UL,
|
||||
/* 0x0030, */ 0x001004040000FFFFUL,
|
||||
/* 0x0038, */ 0x001008070000FFFFUL,
|
||||
/* 0x0040, */ 0x001410070000FFFFUL,
|
||||
/* 0x0048, */ 0x0000000000000000UL,
|
||||
/* 0x0050, */ 0x001404010000FFFFUL,
|
||||
/* 0x0058, */ 0x0014100D0000FFFFUL,
|
||||
/* 0x0060, */ 0x0014100D0000FFFFUL,
|
||||
/* 0x0068, */ 0x0000000000000000UL,
|
||||
/* 0x0070, */ 0x001404010000FFFFUL,
|
||||
/* 0x0078, */ 0x0000000000000000UL,
|
||||
/* 0x0080, */ 0x0000000000000000UL,
|
||||
/* 0x0088, */ 0x001410070000FFFFUL,
|
||||
/* 0x0090, */ 0x0000000000000000UL,
|
||||
/* 0x0098, */ 0x0000000000000000UL,
|
||||
/* 0x00a0, */ 0x000C04020000FFFFUL,
|
||||
/* 0x00a8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x00b0, */ 0x000C04010000FFFFUL,
|
||||
/* 0x00b8, */ 0x0000000000000000UL,
|
||||
/* 0x00c0, */ 0x000C04020000FFFFUL,
|
||||
/* 0x00c8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x00d0, */ 0x000C04010000FFFFUL,
|
||||
/* 0x00d8, */ 0x001024090000FFFFUL,
|
||||
/* 0x00e0, */ 0x00100C090000FFFFUL,
|
||||
/* 0x00e8, */ 0x0000000000000000UL,
|
||||
/* 0x00f0, */ 0x001024090000FFFFUL,
|
||||
/* 0x00f8, */ 0x000C08080000FFFFUL,
|
||||
/* 0x0100, */ 0x0000000000000000UL,
|
||||
/* 0x0108, */ 0x0000000000000000UL,
|
||||
/* 0x0110, */ 0x00100C090000FFFFUL,
|
||||
/* 0x0118, */ 0x000C18180000FFFFUL,
|
||||
/* 0x0120, */ 0x000C18180000FFFFUL,
|
||||
/* 0x0128, */ 0x0000000000000000UL,
|
||||
/* 0x0130, */ 0x0000000000000000UL,
|
||||
/* 0x0138, */ 0x00100C0B0000FFFFUL,
|
||||
/* 0x0140, */ 0x00100C0B0000FFFFUL,
|
||||
/* 0x0148, */ 0x0000000000000000UL,
|
||||
/* 0x0150, */ 0x0010100D0000FFFFUL,
|
||||
/* 0x0158, */ 0x0010100D0000FFFFUL,
|
||||
/* 0x0160, */ 0x00100C0B0000FFFFUL,
|
||||
/* 0x0168, */ 0x00100C0B0000FFFFUL,
|
||||
/* 0x0170, */ 0x0000000000000000UL,
|
||||
/* 0x0178, */ 0x001008060000FFFFUL,
|
||||
/* 0x0180, */ 0x001008060000FFFFUL,
|
||||
/* 0x0188, */ 0x0000000000000000UL,
|
||||
/* 0x0190, */ 0x00102C2C0000FFFFUL,
|
||||
/* 0x0198, */ 0x00102C2C0000FFFFUL,
|
||||
/* 0x01a0, */ 0x00100C0B0000FFFFUL,
|
||||
/* 0x01a8, */ 0x00100C0B0000FFFFUL,
|
||||
/* 0x01b0, */ 0x0000000000000000UL,
|
||||
/* 0x01b8, */ 0x0000000000000000UL,
|
||||
/* 0x01c0, */ 0x000C04010000FFFFUL,
|
||||
/* 0x01c8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x01d0, */ 0x000C04010000FFFFUL,
|
||||
/* 0x01d8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x01e0, */ 0x0000000000000000UL,
|
||||
/* 0x01e8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x01f0, */ 0x000C04010000FFFFUL,
|
||||
/* 0x01f8, */ 0x0000000000000000UL,
|
||||
/* 0x0200, */ 0x0000000000000000UL,
|
||||
/* 0x0208, */ 0x000C04010000FFFFUL,
|
||||
/* 0x0210, */ 0x000C04010000FFFFUL,
|
||||
/* 0x0218, */ 0x0000000000000000UL,
|
||||
/* 0x0220, */ 0x0000000000000000UL,
|
||||
/* 0x0228, */ 0x0000000000000000UL,
|
||||
/* 0x0230, */ 0x0000000000000000UL,
|
||||
/* 0x0238, */ 0x0000000000000000UL,
|
||||
/* 0x0240, */ 0x0000000000000000UL,
|
||||
/* 0x0248, */ 0x0000000000000000UL,
|
||||
/* 0x0250, */ 0x0000000000000000UL,
|
||||
/* 0x0258, */ 0x0000000000000000UL,
|
||||
/* 0x0260, */ 0x000C08020000FFFFUL,
|
||||
/* 0x0268, */ 0x001408010000FFFFUL,
|
||||
/* 0x0270, */ 0x001404010000FFFFUL,
|
||||
/* 0x0278, */ 0x000C04010000FFFFUL,
|
||||
/* 0x0280, */ 0x0000000000000000UL,
|
||||
/* 0x0288, */ 0x0000000000000000UL,
|
||||
/* 0x0290, */ 0x001408010000FFFFUL,
|
||||
/* 0x0298, */ 0x001404010000FFFFUL,
|
||||
/* 0x02a0, */ 0x000C04010000FFFFUL,
|
||||
/* 0x02a8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x02b0, */ 0x001408010000FFFFUL,
|
||||
/* 0x02b8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x02c0, */ 0x0000000000000000UL,
|
||||
/* 0x02c8, */ 0x0000000000000000UL,
|
||||
/* 0x02d0, */ 0x000C04010000FFFFUL,
|
||||
/* 0x02d8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x02e0, */ 0x001408010000FFFFUL,
|
||||
/* 0x02e8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x02f0, */ 0x0000000000000000UL,
|
||||
/* 0x02f8, */ 0x0000000000000000UL,
|
||||
/* 0x0300, */ 0x0000000000000000UL,
|
||||
/* 0x0308, */ 0x0000000000000000UL,
|
||||
/* 0x0310, */ 0x0000000000000000UL,
|
||||
/* 0x0318, */ 0x0000000000000000UL,
|
||||
/* 0x0320, */ 0x0000000000000000UL,
|
||||
/* 0x0328, */ 0x0000000000000000UL,
|
||||
/* 0x0330, */ 0x0000000000000000UL,
|
||||
/* 0x0338, */ 0x0000000000000000UL,
|
||||
/* 0x0340, */ 0x0000000000000000UL,
|
||||
/* 0x0348, */ 0x0000000000000000UL,
|
||||
/* 0x0350, */ 0x0000000000000000UL,
|
||||
/* 0x0358, */ 0x0000000000000000UL,
|
||||
/* 0x0360, */ 0x0000000000000000UL,
|
||||
/* 0x0368, */ 0x0000000000000000UL,
|
||||
};
|
||||
|
||||
static uint64_t mstat_be[] = {
|
||||
/* 0x0000, */ 0x001200600BDFFC01UL,
|
||||
/* 0x0008, */ 0x001200600BDFFC01UL,
|
||||
/* 0x0010, */ 0x001200600BDFFC01UL,
|
||||
/* 0x0018, */ 0x001200600BDFFC01UL,
|
||||
/* 0x0020, */ 0x0000000000000000UL,
|
||||
/* 0x0028, */ 0x001200100BD0FC01UL,
|
||||
/* 0x0030, */ 0x0000000000000000UL,
|
||||
/* 0x0038, */ 0x0000000000000000UL,
|
||||
/* 0x0040, */ 0x0000000000000000UL,
|
||||
/* 0x0048, */ 0x0000000000000000UL,
|
||||
/* 0x0050, */ 0x0000000000000000UL,
|
||||
/* 0x0058, */ 0x0000000000000000UL,
|
||||
/* 0x0060, */ 0x0000000000000000UL,
|
||||
/* 0x0068, */ 0x0000000000000000UL,
|
||||
/* 0x0070, */ 0x0000000000000000UL,
|
||||
/* 0x0078, */ 0x0000000000000000UL,
|
||||
/* 0x0080, */ 0x0000000000000000UL,
|
||||
/* 0x0088, */ 0x0000000000000000UL,
|
||||
/* 0x0090, */ 0x0000000000000000UL,
|
||||
/* 0x0098, */ 0x0000000000000000UL,
|
||||
/* 0x00a0, */ 0x0000000000000000UL,
|
||||
/* 0x00a8, */ 0x0000000000000000UL,
|
||||
/* 0x00b0, */ 0x0000000000000000UL,
|
||||
/* 0x00b8, */ 0x0000000000000000UL,
|
||||
/* 0x00c0, */ 0x0000000000000000UL,
|
||||
/* 0x00c8, */ 0x0000000000000000UL,
|
||||
/* 0x00d0, */ 0x0000000000000000UL,
|
||||
/* 0x00d8, */ 0x0000000000000000UL,
|
||||
/* 0x00e0, */ 0x0000000000000000UL,
|
||||
/* 0x00e8, */ 0x0000000000000000UL,
|
||||
/* 0x00f0, */ 0x0000000000000000UL,
|
||||
/* 0x00f8, */ 0x0000000000000000UL,
|
||||
/* 0x0100, */ 0x0000000000000000UL,
|
||||
/* 0x0108, */ 0x0000000000000000UL,
|
||||
/* 0x0110, */ 0x0000000000000000UL,
|
||||
/* 0x0118, */ 0x0000000000000000UL,
|
||||
/* 0x0120, */ 0x0000000000000000UL,
|
||||
/* 0x0128, */ 0x0000000000000000UL,
|
||||
/* 0x0130, */ 0x0000000000000000UL,
|
||||
/* 0x0138, */ 0x0000000000000000UL,
|
||||
/* 0x0140, */ 0x0000000000000000UL,
|
||||
/* 0x0148, */ 0x0000000000000000UL,
|
||||
/* 0x0150, */ 0x0000000000000000UL,
|
||||
/* 0x0158, */ 0x0000000000000000UL,
|
||||
/* 0x0160, */ 0x0000000000000000UL,
|
||||
/* 0x0168, */ 0x0000000000000000UL,
|
||||
/* 0x0170, */ 0x0000000000000000UL,
|
||||
/* 0x0178, */ 0x0000000000000000UL,
|
||||
/* 0x0180, */ 0x0000000000000000UL,
|
||||
/* 0x0188, */ 0x0000000000000000UL,
|
||||
/* 0x0190, */ 0x0000000000000000UL,
|
||||
/* 0x0198, */ 0x0000000000000000UL,
|
||||
/* 0x01a0, */ 0x0000000000000000UL,
|
||||
/* 0x01a8, */ 0x0000000000000000UL,
|
||||
/* 0x01b0, */ 0x0000000000000000UL,
|
||||
/* 0x01b8, */ 0x0000000000000000UL,
|
||||
/* 0x01c0, */ 0x002100600BDFFC01UL,
|
||||
/* 0x01c8, */ 0x002100600BDFFC01UL,
|
||||
/* 0x01d0, */ 0x002100600BDFFC01UL,
|
||||
/* 0x01d8, */ 0x002100600BDFFC01UL,
|
||||
/* 0x01e0, */ 0x0000000000000000UL,
|
||||
/* 0x01e8, */ 0x0000000000000000UL,
|
||||
/* 0x01f0, */ 0x002100100BDF2401UL,
|
||||
/* 0x01f8, */ 0x0000000000000000UL,
|
||||
/* 0x0200, */ 0x0000000000000000UL,
|
||||
/* 0x0208, */ 0x0000000000000000UL,
|
||||
/* 0x0210, */ 0x002100100BDF2401UL,
|
||||
/* 0x0218, */ 0x001100100BDF2401UL,
|
||||
/* 0x0220, */ 0x001100100BDF2401UL,
|
||||
/* 0x0228, */ 0x0000000000000000UL,
|
||||
/* 0x0230, */ 0x001100100BDF2401UL,
|
||||
/* 0x0238, */ 0x001100100BDF2401UL,
|
||||
/* 0x0240, */ 0x001200100BDF2401UL,
|
||||
/* 0x0248, */ 0x001100100BDF2401UL,
|
||||
/* 0x0250, */ 0x001200100BDF2401UL,
|
||||
/* 0x0258, */ 0x001100100BDF2401UL,
|
||||
/* 0x0260, */ 0x0000000000000000UL,
|
||||
/* 0x0268, */ 0x0000000000000000UL,
|
||||
/* 0x0270, */ 0x0000000000000000UL,
|
||||
/* 0x0278, */ 0x0000000000000000UL,
|
||||
/* 0x0280, */ 0x0000000000000000UL,
|
||||
/* 0x0288, */ 0x0000000000000000UL,
|
||||
/* 0x0290, */ 0x0000000000000000UL,
|
||||
/* 0x0298, */ 0x0000000000000000UL,
|
||||
/* 0x02a0, */ 0x0000000000000000UL,
|
||||
/* 0x02a8, */ 0x0000000000000000UL,
|
||||
/* 0x02b0, */ 0x0000000000000000UL,
|
||||
/* 0x02b8, */ 0x0000000000000000UL,
|
||||
/* 0x02c0, */ 0x0000000000000000UL,
|
||||
/* 0x02c8, */ 0x0000000000000000UL,
|
||||
/* 0x02d0, */ 0x0000000000000000UL,
|
||||
/* 0x02d8, */ 0x0000000000000000UL,
|
||||
/* 0x02e0, */ 0x0000000000000000UL,
|
||||
/* 0x02e8, */ 0x0000000000000000UL,
|
||||
/* 0x02f0, */ 0x001100600BDFFC01UL,
|
||||
/* 0x02f8, */ 0x001100600BDFFC01UL,
|
||||
/* 0x0300, */ 0x0000000000000000UL,
|
||||
/* 0x0308, */ 0x001100600BDFFC01UL,
|
||||
/* 0x0310, */ 0x001100600BDFFC01UL,
|
||||
/* 0x0318, */ 0x001200100BD03401UL,
|
||||
/* 0x0320, */ 0x001100600BDFFC01UL,
|
||||
/* 0x0328, */ 0x001100600BDFFC01UL,
|
||||
/* 0x0330, */ 0x001100600BDFFC01UL,
|
||||
/* 0x0338, */ 0x001100600BDFFC01UL,
|
||||
/* 0x0340, */ 0x0000000000000000UL,
|
||||
/* 0x0348, */ 0x0000000000000000UL,
|
||||
/* 0x0350, */ 0x0000000000000000UL,
|
||||
/* 0x0358, */ 0x0000000000000000UL,
|
||||
/* 0x0360, */ 0x0000000000000000UL,
|
||||
/* 0x0368, */ 0x001200100BD0FC01UL,
|
||||
};
|
231
drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30_mstat390.h
Normal file
231
drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30_mstat390.h
Normal file
|
@ -0,0 +1,231 @@
|
|||
/*
|
||||
* Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
static uint64_t mstat_fix[] = {
|
||||
/* 0x0000, */ 0x0000000000000000UL,
|
||||
/* 0x0008, */ 0x0000000000000000UL,
|
||||
/* 0x0010, */ 0x0000000000000000UL,
|
||||
/* 0x0018, */ 0x0000000000000000UL,
|
||||
/* 0x0020, */ 0x0000000000000000UL,
|
||||
/* 0x0028, */ 0x0000000000000000UL,
|
||||
/* 0x0030, */ 0x001008070000FFFFUL,
|
||||
/* 0x0038, */ 0x0010100D0000FFFFUL,
|
||||
/* 0x0040, */ 0x00141C0E0000FFFFUL,
|
||||
/* 0x0048, */ 0x0000000000000000UL,
|
||||
/* 0x0050, */ 0x001408010000FFFFUL,
|
||||
/* 0x0058, */ 0x00141C190000FFFFUL,
|
||||
/* 0x0060, */ 0x00141C190000FFFFUL,
|
||||
/* 0x0068, */ 0x0000000000000000UL,
|
||||
/* 0x0070, */ 0x001408010000FFFFUL,
|
||||
/* 0x0078, */ 0x0000000000000000UL,
|
||||
/* 0x0080, */ 0x0000000000000000UL,
|
||||
/* 0x0088, */ 0x00141C0E0000FFFFUL,
|
||||
/* 0x0090, */ 0x0000000000000000UL,
|
||||
/* 0x0098, */ 0x0000000000000000UL,
|
||||
/* 0x00a0, */ 0x000C08040000FFFFUL,
|
||||
/* 0x00a8, */ 0x000C04020000FFFFUL,
|
||||
/* 0x00b0, */ 0x000C04020000FFFFUL,
|
||||
/* 0x00b8, */ 0x0000000000000000UL,
|
||||
/* 0x00c0, */ 0x000C08040000FFFFUL,
|
||||
/* 0x00c8, */ 0x000C04020000FFFFUL,
|
||||
/* 0x00d0, */ 0x000C04020000FFFFUL,
|
||||
/* 0x00d8, */ 0x001044110000FFFFUL,
|
||||
/* 0x00e0, */ 0x001014110000FFFFUL,
|
||||
/* 0x00e8, */ 0x0000000000000000UL,
|
||||
/* 0x00f0, */ 0x001044110000FFFFUL,
|
||||
/* 0x00f8, */ 0x000C10100000FFFFUL,
|
||||
/* 0x0100, */ 0x0000000000000000UL,
|
||||
/* 0x0108, */ 0x0000000000000000UL,
|
||||
/* 0x0110, */ 0x001014110000FFFFUL,
|
||||
/* 0x0118, */ 0x000C302F0000FFFFUL,
|
||||
/* 0x0120, */ 0x000C302F0000FFFFUL,
|
||||
/* 0x0128, */ 0x0000000000000000UL,
|
||||
/* 0x0130, */ 0x0000000000000000UL,
|
||||
/* 0x0138, */ 0x001018150000FFFFUL,
|
||||
/* 0x0140, */ 0x001018150000FFFFUL,
|
||||
/* 0x0148, */ 0x0000000000000000UL,
|
||||
/* 0x0150, */ 0x00101C190000FFFFUL,
|
||||
/* 0x0158, */ 0x00101C190000FFFFUL,
|
||||
/* 0x0160, */ 0x001018150000FFFFUL,
|
||||
/* 0x0168, */ 0x001018150000FFFFUL,
|
||||
/* 0x0170, */ 0x0000000000000000UL,
|
||||
/* 0x0178, */ 0x00100C0B0000FFFFUL,
|
||||
/* 0x0180, */ 0x00100C0B0000FFFFUL,
|
||||
/* 0x0188, */ 0x0000000000000000UL,
|
||||
/* 0x0190, */ 0x001058570000FFFFUL,
|
||||
/* 0x0198, */ 0x001058570000FFFFUL,
|
||||
/* 0x01a0, */ 0x001018150000FFFFUL,
|
||||
/* 0x01a8, */ 0x001018150000FFFFUL,
|
||||
/* 0x01b0, */ 0x0000000000000000UL,
|
||||
/* 0x01b8, */ 0x0000000000000000UL,
|
||||
/* 0x01c0, */ 0x000C04010000FFFFUL,
|
||||
/* 0x01c8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x01d0, */ 0x000C04010000FFFFUL,
|
||||
/* 0x01d8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x01e0, */ 0x0000000000000000UL,
|
||||
/* 0x01e8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x01f0, */ 0x000C04010000FFFFUL,
|
||||
/* 0x01f8, */ 0x0000000000000000UL,
|
||||
/* 0x0200, */ 0x0000000000000000UL,
|
||||
/* 0x0208, */ 0x000C04010000FFFFUL,
|
||||
/* 0x0210, */ 0x000C04010000FFFFUL,
|
||||
/* 0x0218, */ 0x0000000000000000UL,
|
||||
/* 0x0220, */ 0x0000000000000000UL,
|
||||
/* 0x0228, */ 0x0000000000000000UL,
|
||||
/* 0x0230, */ 0x0000000000000000UL,
|
||||
/* 0x0238, */ 0x0000000000000000UL,
|
||||
/* 0x0240, */ 0x0000000000000000UL,
|
||||
/* 0x0248, */ 0x0000000000000000UL,
|
||||
/* 0x0250, */ 0x0000000000000000UL,
|
||||
/* 0x0258, */ 0x0000000000000000UL,
|
||||
/* 0x0260, */ 0x000C0C030000FFFFUL,
|
||||
/* 0x0268, */ 0x001410010000FFFFUL,
|
||||
/* 0x0270, */ 0x001404010000FFFFUL,
|
||||
/* 0x0278, */ 0x000C08020000FFFFUL,
|
||||
/* 0x0280, */ 0x0000000000000000UL,
|
||||
/* 0x0288, */ 0x0000000000000000UL,
|
||||
/* 0x0290, */ 0x001410010000FFFFUL,
|
||||
/* 0x0298, */ 0x001404010000FFFFUL,
|
||||
/* 0x02a0, */ 0x000C04010000FFFFUL,
|
||||
/* 0x02a8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x02b0, */ 0x00140C010000FFFFUL,
|
||||
/* 0x02b8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x02c0, */ 0x0000000000000000UL,
|
||||
/* 0x02c8, */ 0x0000000000000000UL,
|
||||
/* 0x02d0, */ 0x000C04010000FFFFUL,
|
||||
/* 0x02d8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x02e0, */ 0x00140C010000FFFFUL,
|
||||
/* 0x02e8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x02f0, */ 0x0000000000000000UL,
|
||||
/* 0x02f8, */ 0x0000000000000000UL,
|
||||
/* 0x0300, */ 0x0000000000000000UL,
|
||||
/* 0x0308, */ 0x0000000000000000UL,
|
||||
/* 0x0310, */ 0x0000000000000000UL,
|
||||
/* 0x0318, */ 0x0000000000000000UL,
|
||||
/* 0x0320, */ 0x0000000000000000UL,
|
||||
/* 0x0328, */ 0x0000000000000000UL,
|
||||
/* 0x0330, */ 0x0000000000000000UL,
|
||||
/* 0x0338, */ 0x0000000000000000UL,
|
||||
/* 0x0340, */ 0x0000000000000000UL,
|
||||
/* 0x0348, */ 0x0000000000000000UL,
|
||||
/* 0x0350, */ 0x0000000000000000UL,
|
||||
/* 0x0358, */ 0x0000000000000000UL,
|
||||
/* 0x0360, */ 0x0000000000000000UL,
|
||||
/* 0x0368, */ 0x0000000000000000UL,
|
||||
};
|
||||
|
||||
static uint64_t mstat_be[] = {
|
||||
/* 0x0000, */ 0x0012006005EFFC01UL,
|
||||
/* 0x0008, */ 0x0012006005EFFC01UL,
|
||||
/* 0x0010, */ 0x0012006005EFFC01UL,
|
||||
/* 0x0018, */ 0x0012006005EFFC01UL,
|
||||
/* 0x0020, */ 0x0000000000000000UL,
|
||||
/* 0x0028, */ 0x0012001005E0FC01UL,
|
||||
/* 0x0030, */ 0x0000000000000000UL,
|
||||
/* 0x0038, */ 0x0000000000000000UL,
|
||||
/* 0x0040, */ 0x0000000000000000UL,
|
||||
/* 0x0048, */ 0x0000000000000000UL,
|
||||
/* 0x0050, */ 0x0000000000000000UL,
|
||||
/* 0x0058, */ 0x0000000000000000UL,
|
||||
/* 0x0060, */ 0x0000000000000000UL,
|
||||
/* 0x0068, */ 0x0000000000000000UL,
|
||||
/* 0x0070, */ 0x0000000000000000UL,
|
||||
/* 0x0078, */ 0x0000000000000000UL,
|
||||
/* 0x0080, */ 0x0000000000000000UL,
|
||||
/* 0x0088, */ 0x0000000000000000UL,
|
||||
/* 0x0090, */ 0x0000000000000000UL,
|
||||
/* 0x0098, */ 0x0000000000000000UL,
|
||||
/* 0x00a0, */ 0x0000000000000000UL,
|
||||
/* 0x00a8, */ 0x0000000000000000UL,
|
||||
/* 0x00b0, */ 0x0000000000000000UL,
|
||||
/* 0x00b8, */ 0x0000000000000000UL,
|
||||
/* 0x00c0, */ 0x0000000000000000UL,
|
||||
/* 0x00c8, */ 0x0000000000000000UL,
|
||||
/* 0x00d0, */ 0x0000000000000000UL,
|
||||
/* 0x00d8, */ 0x0000000000000000UL,
|
||||
/* 0x00e0, */ 0x0000000000000000UL,
|
||||
/* 0x00e8, */ 0x0000000000000000UL,
|
||||
/* 0x00f0, */ 0x0000000000000000UL,
|
||||
/* 0x00f8, */ 0x0000000000000000UL,
|
||||
/* 0x0100, */ 0x0000000000000000UL,
|
||||
/* 0x0108, */ 0x0000000000000000UL,
|
||||
/* 0x0110, */ 0x0000000000000000UL,
|
||||
/* 0x0118, */ 0x0000000000000000UL,
|
||||
/* 0x0120, */ 0x0000000000000000UL,
|
||||
/* 0x0128, */ 0x0000000000000000UL,
|
||||
/* 0x0130, */ 0x0000000000000000UL,
|
||||
/* 0x0138, */ 0x0000000000000000UL,
|
||||
/* 0x0140, */ 0x0000000000000000UL,
|
||||
/* 0x0148, */ 0x0000000000000000UL,
|
||||
/* 0x0150, */ 0x0000000000000000UL,
|
||||
/* 0x0158, */ 0x0000000000000000UL,
|
||||
/* 0x0160, */ 0x0000000000000000UL,
|
||||
/* 0x0168, */ 0x0000000000000000UL,
|
||||
/* 0x0170, */ 0x0000000000000000UL,
|
||||
/* 0x0178, */ 0x0000000000000000UL,
|
||||
/* 0x0180, */ 0x0000000000000000UL,
|
||||
/* 0x0188, */ 0x0000000000000000UL,
|
||||
/* 0x0190, */ 0x0000000000000000UL,
|
||||
/* 0x0198, */ 0x0000000000000000UL,
|
||||
/* 0x01a0, */ 0x0000000000000000UL,
|
||||
/* 0x01a8, */ 0x0000000000000000UL,
|
||||
/* 0x01b0, */ 0x0000000000000000UL,
|
||||
/* 0x01b8, */ 0x0000000000000000UL,
|
||||
/* 0x01c0, */ 0x0021006005EFFC01UL,
|
||||
/* 0x01c8, */ 0x0021006005EFFC01UL,
|
||||
/* 0x01d0, */ 0x0021006005EFFC01UL,
|
||||
/* 0x01d8, */ 0x0021006005EFFC01UL,
|
||||
/* 0x01e0, */ 0x0000000000000000UL,
|
||||
/* 0x01e8, */ 0x0000000000000000UL,
|
||||
/* 0x01f0, */ 0x0021001005E79401UL,
|
||||
/* 0x01f8, */ 0x0000000000000000UL,
|
||||
/* 0x0200, */ 0x0000000000000000UL,
|
||||
/* 0x0208, */ 0x0000000000000000UL,
|
||||
/* 0x0210, */ 0x0021001005E79401UL,
|
||||
/* 0x0218, */ 0x0011001005E79401UL,
|
||||
/* 0x0220, */ 0x0011001005E79401UL,
|
||||
/* 0x0228, */ 0x0000000000000000UL,
|
||||
/* 0x0230, */ 0x0011001005E79401UL,
|
||||
/* 0x0238, */ 0x0011001005E79401UL,
|
||||
/* 0x0240, */ 0x0012001005E79401UL,
|
||||
/* 0x0248, */ 0x0011001005E79401UL,
|
||||
/* 0x0250, */ 0x0012001005E79401UL,
|
||||
/* 0x0258, */ 0x0011001005E79401UL,
|
||||
/* 0x0260, */ 0x0000000000000000UL,
|
||||
/* 0x0268, */ 0x0000000000000000UL,
|
||||
/* 0x0270, */ 0x0000000000000000UL,
|
||||
/* 0x0278, */ 0x0000000000000000UL,
|
||||
/* 0x0280, */ 0x0000000000000000UL,
|
||||
/* 0x0288, */ 0x0000000000000000UL,
|
||||
/* 0x0290, */ 0x0000000000000000UL,
|
||||
/* 0x0298, */ 0x0000000000000000UL,
|
||||
/* 0x02a0, */ 0x0000000000000000UL,
|
||||
/* 0x02a8, */ 0x0000000000000000UL,
|
||||
/* 0x02b0, */ 0x0000000000000000UL,
|
||||
/* 0x02b8, */ 0x0000000000000000UL,
|
||||
/* 0x02c0, */ 0x0000000000000000UL,
|
||||
/* 0x02c8, */ 0x0000000000000000UL,
|
||||
/* 0x02d0, */ 0x0000000000000000UL,
|
||||
/* 0x02d8, */ 0x0000000000000000UL,
|
||||
/* 0x02e0, */ 0x0000000000000000UL,
|
||||
/* 0x02e8, */ 0x0000000000000000UL,
|
||||
/* 0x02f0, */ 0x0011006005EFFC01UL,
|
||||
/* 0x02f8, */ 0x0011006005EFFC01UL,
|
||||
/* 0x0300, */ 0x0000000000000000UL,
|
||||
/* 0x0308, */ 0x0011006005EFFC01UL,
|
||||
/* 0x0310, */ 0x0011006005EFFC01UL,
|
||||
/* 0x0318, */ 0x0012001005E03401UL,
|
||||
/* 0x0320, */ 0x0011006005EFFC01UL,
|
||||
/* 0x0328, */ 0x0011006005EFFC01UL,
|
||||
/* 0x0330, */ 0x0011006005EFFC01UL,
|
||||
/* 0x0338, */ 0x0011006005EFFC01UL,
|
||||
/* 0x0340, */ 0x0000000000000000UL,
|
||||
/* 0x0348, */ 0x0000000000000000UL,
|
||||
/* 0x0350, */ 0x0000000000000000UL,
|
||||
/* 0x0358, */ 0x0000000000000000UL,
|
||||
/* 0x0360, */ 0x0000000000000000UL,
|
||||
/* 0x0368, */ 0x0012001005E0FC01UL,
|
||||
};
|
231
drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30_qoswt195.h
Normal file
231
drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30_qoswt195.h
Normal file
|
@ -0,0 +1,231 @@
|
|||
/*
|
||||
* Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
static uint64_t qoswt_fix[] = {
|
||||
/* 0x0000, */ 0x0000000000000000UL,
|
||||
/* 0x0008, */ 0x0000000000000000UL,
|
||||
/* 0x0010, */ 0x0000000000000000UL,
|
||||
/* 0x0018, */ 0x0000000000000000UL,
|
||||
/* 0x0020, */ 0x0000000000000000UL,
|
||||
/* 0x0028, */ 0x0000000000000000UL,
|
||||
/* 0x0030, */ 0x001004040000C010UL,
|
||||
/* 0x0038, */ 0x001008070000C010UL,
|
||||
/* 0x0040, */ 0x001410070000FFF0UL,
|
||||
/* 0x0048, */ 0x0000000000000000UL,
|
||||
/* 0x0050, */ 0x0000000000000000UL,
|
||||
/* 0x0058, */ 0x0014100D0000C010UL,
|
||||
/* 0x0060, */ 0x0014100D0000C010UL,
|
||||
/* 0x0068, */ 0x0000000000000000UL,
|
||||
/* 0x0070, */ 0x0000000000000000UL,
|
||||
/* 0x0078, */ 0x0000000000000000UL,
|
||||
/* 0x0080, */ 0x0000000000000000UL,
|
||||
/* 0x0088, */ 0x001410070000FFF0UL,
|
||||
/* 0x0090, */ 0x0000000000000000UL,
|
||||
/* 0x0098, */ 0x0000000000000000UL,
|
||||
/* 0x00a0, */ 0x0000000000000000UL,
|
||||
/* 0x00a8, */ 0x0000000000000000UL,
|
||||
/* 0x00b0, */ 0x0000000000000000UL,
|
||||
/* 0x00b8, */ 0x0000000000000000UL,
|
||||
/* 0x00c0, */ 0x0000000000000000UL,
|
||||
/* 0x00c8, */ 0x0000000000000000UL,
|
||||
/* 0x00d0, */ 0x0000000000000000UL,
|
||||
/* 0x00d8, */ 0x0000000000000000UL,
|
||||
/* 0x00e0, */ 0x0000000000000000UL,
|
||||
/* 0x00e8, */ 0x0000000000000000UL,
|
||||
/* 0x00f0, */ 0x0000000000000000UL,
|
||||
/* 0x00f8, */ 0x0000000000000000UL,
|
||||
/* 0x0100, */ 0x0000000000000000UL,
|
||||
/* 0x0108, */ 0x0000000000000000UL,
|
||||
/* 0x0110, */ 0x0000000000000000UL,
|
||||
/* 0x0118, */ 0x0000000000000000UL,
|
||||
/* 0x0120, */ 0x0000000000000000UL,
|
||||
/* 0x0128, */ 0x0000000000000000UL,
|
||||
/* 0x0130, */ 0x0000000000000000UL,
|
||||
/* 0x0138, */ 0x0000000000000000UL,
|
||||
/* 0x0140, */ 0x0000000000000000UL,
|
||||
/* 0x0148, */ 0x0000000000000000UL,
|
||||
/* 0x0150, */ 0x0000000000000000UL,
|
||||
/* 0x0158, */ 0x0000000000000000UL,
|
||||
/* 0x0160, */ 0x0000000000000000UL,
|
||||
/* 0x0168, */ 0x0000000000000000UL,
|
||||
/* 0x0170, */ 0x0000000000000000UL,
|
||||
/* 0x0178, */ 0x0000000000000000UL,
|
||||
/* 0x0180, */ 0x0000000000000000UL,
|
||||
/* 0x0188, */ 0x0000000000000000UL,
|
||||
/* 0x0190, */ 0x0000000000000000UL,
|
||||
/* 0x0198, */ 0x0000000000000000UL,
|
||||
/* 0x01a0, */ 0x0000000000000000UL,
|
||||
/* 0x01a8, */ 0x0000000000000000UL,
|
||||
/* 0x01b0, */ 0x0000000000000000UL,
|
||||
/* 0x01b8, */ 0x0000000000000000UL,
|
||||
/* 0x01c0, */ 0x0000000000000000UL,
|
||||
/* 0x01c8, */ 0x0000000000000000UL,
|
||||
/* 0x01d0, */ 0x0000000000000000UL,
|
||||
/* 0x01d8, */ 0x0000000000000000UL,
|
||||
/* 0x01e0, */ 0x0000000000000000UL,
|
||||
/* 0x01e8, */ 0x0000000000000000UL,
|
||||
/* 0x01f0, */ 0x0000000000000000UL,
|
||||
/* 0x01f8, */ 0x0000000000000000UL,
|
||||
/* 0x0200, */ 0x0000000000000000UL,
|
||||
/* 0x0208, */ 0x0000000000000000UL,
|
||||
/* 0x0210, */ 0x0000000000000000UL,
|
||||
/* 0x0218, */ 0x0000000000000000UL,
|
||||
/* 0x0220, */ 0x0000000000000000UL,
|
||||
/* 0x0228, */ 0x0000000000000000UL,
|
||||
/* 0x0230, */ 0x0000000000000000UL,
|
||||
/* 0x0238, */ 0x0000000000000000UL,
|
||||
/* 0x0240, */ 0x0000000000000000UL,
|
||||
/* 0x0248, */ 0x0000000000000000UL,
|
||||
/* 0x0250, */ 0x0000000000000000UL,
|
||||
/* 0x0258, */ 0x0000000000000000UL,
|
||||
/* 0x0260, */ 0x000C08020000FFF0UL,
|
||||
/* 0x0268, */ 0x001408010000FFF0UL,
|
||||
/* 0x0270, */ 0x001404010000FFF0UL,
|
||||
/* 0x0278, */ 0x000C04010000FFF0UL,
|
||||
/* 0x0280, */ 0x0000000000000000UL,
|
||||
/* 0x0288, */ 0x0000000000000000UL,
|
||||
/* 0x0290, */ 0x001408010000FFF0UL,
|
||||
/* 0x0298, */ 0x001404010000FFF0UL,
|
||||
/* 0x02a0, */ 0x0000000000000000UL,
|
||||
/* 0x02a8, */ 0x0000000000000000UL,
|
||||
/* 0x02b0, */ 0x0000000000000000UL,
|
||||
/* 0x02b8, */ 0x0000000000000000UL,
|
||||
/* 0x02c0, */ 0x0000000000000000UL,
|
||||
/* 0x02c8, */ 0x0000000000000000UL,
|
||||
/* 0x02d0, */ 0x0000000000000000UL,
|
||||
/* 0x02d8, */ 0x0000000000000000UL,
|
||||
/* 0x02e0, */ 0x0000000000000000UL,
|
||||
/* 0x02e8, */ 0x0000000000000000UL,
|
||||
/* 0x02f0, */ 0x0000000000000000UL,
|
||||
/* 0x02f8, */ 0x0000000000000000UL,
|
||||
/* 0x0300, */ 0x0000000000000000UL,
|
||||
/* 0x0308, */ 0x0000000000000000UL,
|
||||
/* 0x0310, */ 0x0000000000000000UL,
|
||||
/* 0x0318, */ 0x0000000000000000UL,
|
||||
/* 0x0320, */ 0x0000000000000000UL,
|
||||
/* 0x0328, */ 0x0000000000000000UL,
|
||||
/* 0x0330, */ 0x0000000000000000UL,
|
||||
/* 0x0338, */ 0x0000000000000000UL,
|
||||
/* 0x0340, */ 0x0000000000000000UL,
|
||||
/* 0x0348, */ 0x0000000000000000UL,
|
||||
/* 0x0350, */ 0x0000000000000000UL,
|
||||
/* 0x0358, */ 0x0000000000000000UL,
|
||||
/* 0x0360, */ 0x0000000000000000UL,
|
||||
/* 0x0368, */ 0x0000000000000000UL,
|
||||
};
|
||||
|
||||
static uint64_t qoswt_be[] = {
|
||||
/* 0x0000, */ 0x0000000000000000UL,
|
||||
/* 0x0008, */ 0x0000000000000000UL,
|
||||
/* 0x0010, */ 0x0000000000000000UL,
|
||||
/* 0x0018, */ 0x0000000000000000UL,
|
||||
/* 0x0020, */ 0x0000000000000000UL,
|
||||
/* 0x0028, */ 0x0000000000000000UL,
|
||||
/* 0x0030, */ 0x0000000000000000UL,
|
||||
/* 0x0038, */ 0x0000000000000000UL,
|
||||
/* 0x0040, */ 0x0000000000000000UL,
|
||||
/* 0x0048, */ 0x0000000000000000UL,
|
||||
/* 0x0050, */ 0x0000000000000000UL,
|
||||
/* 0x0058, */ 0x0000000000000000UL,
|
||||
/* 0x0060, */ 0x0000000000000000UL,
|
||||
/* 0x0068, */ 0x0000000000000000UL,
|
||||
/* 0x0070, */ 0x0000000000000000UL,
|
||||
/* 0x0078, */ 0x0000000000000000UL,
|
||||
/* 0x0080, */ 0x0000000000000000UL,
|
||||
/* 0x0088, */ 0x0000000000000000UL,
|
||||
/* 0x0090, */ 0x0000000000000000UL,
|
||||
/* 0x0098, */ 0x0000000000000000UL,
|
||||
/* 0x00a0, */ 0x0000000000000000UL,
|
||||
/* 0x00a8, */ 0x0000000000000000UL,
|
||||
/* 0x00b0, */ 0x0000000000000000UL,
|
||||
/* 0x00b8, */ 0x0000000000000000UL,
|
||||
/* 0x00c0, */ 0x0000000000000000UL,
|
||||
/* 0x00c8, */ 0x0000000000000000UL,
|
||||
/* 0x00d0, */ 0x0000000000000000UL,
|
||||
/* 0x00d8, */ 0x0000000000000000UL,
|
||||
/* 0x00e0, */ 0x0000000000000000UL,
|
||||
/* 0x00e8, */ 0x0000000000000000UL,
|
||||
/* 0x00f0, */ 0x0000000000000000UL,
|
||||
/* 0x00f8, */ 0x0000000000000000UL,
|
||||
/* 0x0100, */ 0x0000000000000000UL,
|
||||
/* 0x0108, */ 0x0000000000000000UL,
|
||||
/* 0x0110, */ 0x0000000000000000UL,
|
||||
/* 0x0118, */ 0x0000000000000000UL,
|
||||
/* 0x0120, */ 0x0000000000000000UL,
|
||||
/* 0x0128, */ 0x0000000000000000UL,
|
||||
/* 0x0130, */ 0x0000000000000000UL,
|
||||
/* 0x0138, */ 0x0000000000000000UL,
|
||||
/* 0x0140, */ 0x0000000000000000UL,
|
||||
/* 0x0148, */ 0x0000000000000000UL,
|
||||
/* 0x0150, */ 0x0000000000000000UL,
|
||||
/* 0x0158, */ 0x0000000000000000UL,
|
||||
/* 0x0160, */ 0x0000000000000000UL,
|
||||
/* 0x0168, */ 0x0000000000000000UL,
|
||||
/* 0x0170, */ 0x0000000000000000UL,
|
||||
/* 0x0178, */ 0x0000000000000000UL,
|
||||
/* 0x0180, */ 0x0000000000000000UL,
|
||||
/* 0x0188, */ 0x0000000000000000UL,
|
||||
/* 0x0190, */ 0x0000000000000000UL,
|
||||
/* 0x0198, */ 0x0000000000000000UL,
|
||||
/* 0x01a0, */ 0x0000000000000000UL,
|
||||
/* 0x01a8, */ 0x0000000000000000UL,
|
||||
/* 0x01b0, */ 0x0000000000000000UL,
|
||||
/* 0x01b8, */ 0x0000000000000000UL,
|
||||
/* 0x01c0, */ 0x0000000000000000UL,
|
||||
/* 0x01c8, */ 0x0000000000000000UL,
|
||||
/* 0x01d0, */ 0x0000000000000000UL,
|
||||
/* 0x01d8, */ 0x0000000000000000UL,
|
||||
/* 0x01e0, */ 0x0000000000000000UL,
|
||||
/* 0x01e8, */ 0x0000000000000000UL,
|
||||
/* 0x01f0, */ 0x0000000000000000UL,
|
||||
/* 0x01f8, */ 0x0000000000000000UL,
|
||||
/* 0x0200, */ 0x0000000000000000UL,
|
||||
/* 0x0208, */ 0x0000000000000000UL,
|
||||
/* 0x0210, */ 0x0000000000000000UL,
|
||||
/* 0x0218, */ 0x0000000000000000UL,
|
||||
/* 0x0220, */ 0x0000000000000000UL,
|
||||
/* 0x0228, */ 0x0000000000000000UL,
|
||||
/* 0x0230, */ 0x0000000000000000UL,
|
||||
/* 0x0238, */ 0x0000000000000000UL,
|
||||
/* 0x0240, */ 0x0000000000000000UL,
|
||||
/* 0x0248, */ 0x0000000000000000UL,
|
||||
/* 0x0250, */ 0x0000000000000000UL,
|
||||
/* 0x0258, */ 0x0000000000000000UL,
|
||||
/* 0x0260, */ 0x0000000000000000UL,
|
||||
/* 0x0268, */ 0x0000000000000000UL,
|
||||
/* 0x0270, */ 0x0000000000000000UL,
|
||||
/* 0x0278, */ 0x0000000000000000UL,
|
||||
/* 0x0280, */ 0x0000000000000000UL,
|
||||
/* 0x0288, */ 0x0000000000000000UL,
|
||||
/* 0x0290, */ 0x0000000000000000UL,
|
||||
/* 0x0298, */ 0x0000000000000000UL,
|
||||
/* 0x02a0, */ 0x0000000000000000UL,
|
||||
/* 0x02a8, */ 0x0000000000000000UL,
|
||||
/* 0x02b0, */ 0x0000000000000000UL,
|
||||
/* 0x02b8, */ 0x0000000000000000UL,
|
||||
/* 0x02c0, */ 0x0000000000000000UL,
|
||||
/* 0x02c8, */ 0x0000000000000000UL,
|
||||
/* 0x02d0, */ 0x0000000000000000UL,
|
||||
/* 0x02d8, */ 0x0000000000000000UL,
|
||||
/* 0x02e0, */ 0x0000000000000000UL,
|
||||
/* 0x02e8, */ 0x0000000000000000UL,
|
||||
/* 0x02f0, */ 0x0000000000000000UL,
|
||||
/* 0x02f8, */ 0x0000000000000000UL,
|
||||
/* 0x0300, */ 0x0000000000000000UL,
|
||||
/* 0x0308, */ 0x0000000000000000UL,
|
||||
/* 0x0310, */ 0x0000000000000000UL,
|
||||
/* 0x0318, */ 0x0000000000000000UL,
|
||||
/* 0x0320, */ 0x0000000000000000UL,
|
||||
/* 0x0328, */ 0x0000000000000000UL,
|
||||
/* 0x0330, */ 0x0000000000000000UL,
|
||||
/* 0x0338, */ 0x0000000000000000UL,
|
||||
/* 0x0340, */ 0x0000000000000000UL,
|
||||
/* 0x0348, */ 0x0000000000000000UL,
|
||||
/* 0x0350, */ 0x0000000000000000UL,
|
||||
/* 0x0358, */ 0x0000000000000000UL,
|
||||
/* 0x0360, */ 0x0000000000000000UL,
|
||||
/* 0x0368, */ 0x0000000000000000UL,
|
||||
};
|
231
drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30_qoswt390.h
Normal file
231
drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30_qoswt390.h
Normal file
|
@ -0,0 +1,231 @@
|
|||
/*
|
||||
* Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
static uint64_t qoswt_fix[] = {
|
||||
/* 0x0000, */ 0x0000000000000000UL,
|
||||
/* 0x0008, */ 0x0000000000000000UL,
|
||||
/* 0x0010, */ 0x0000000000000000UL,
|
||||
/* 0x0018, */ 0x0000000000000000UL,
|
||||
/* 0x0020, */ 0x0000000000000000UL,
|
||||
/* 0x0028, */ 0x0000000000000000UL,
|
||||
/* 0x0030, */ 0x001008070000C010UL,
|
||||
/* 0x0038, */ 0x0010100D0000C010UL,
|
||||
/* 0x0040, */ 0x00141C0E0000FFF0UL,
|
||||
/* 0x0048, */ 0x0000000000000000UL,
|
||||
/* 0x0050, */ 0x0000000000000000UL,
|
||||
/* 0x0058, */ 0x00141C190000C010UL,
|
||||
/* 0x0060, */ 0x00141C190000C010UL,
|
||||
/* 0x0068, */ 0x0000000000000000UL,
|
||||
/* 0x0070, */ 0x0000000000000000UL,
|
||||
/* 0x0078, */ 0x0000000000000000UL,
|
||||
/* 0x0080, */ 0x0000000000000000UL,
|
||||
/* 0x0088, */ 0x00141C0E0000FFF0UL,
|
||||
/* 0x0090, */ 0x0000000000000000UL,
|
||||
/* 0x0098, */ 0x0000000000000000UL,
|
||||
/* 0x00a0, */ 0x0000000000000000UL,
|
||||
/* 0x00a8, */ 0x0000000000000000UL,
|
||||
/* 0x00b0, */ 0x0000000000000000UL,
|
||||
/* 0x00b8, */ 0x0000000000000000UL,
|
||||
/* 0x00c0, */ 0x0000000000000000UL,
|
||||
/* 0x00c8, */ 0x0000000000000000UL,
|
||||
/* 0x00d0, */ 0x0000000000000000UL,
|
||||
/* 0x00d8, */ 0x0000000000000000UL,
|
||||
/* 0x00e0, */ 0x0000000000000000UL,
|
||||
/* 0x00e8, */ 0x0000000000000000UL,
|
||||
/* 0x00f0, */ 0x0000000000000000UL,
|
||||
/* 0x00f8, */ 0x0000000000000000UL,
|
||||
/* 0x0100, */ 0x0000000000000000UL,
|
||||
/* 0x0108, */ 0x0000000000000000UL,
|
||||
/* 0x0110, */ 0x0000000000000000UL,
|
||||
/* 0x0118, */ 0x0000000000000000UL,
|
||||
/* 0x0120, */ 0x0000000000000000UL,
|
||||
/* 0x0128, */ 0x0000000000000000UL,
|
||||
/* 0x0130, */ 0x0000000000000000UL,
|
||||
/* 0x0138, */ 0x0000000000000000UL,
|
||||
/* 0x0140, */ 0x0000000000000000UL,
|
||||
/* 0x0148, */ 0x0000000000000000UL,
|
||||
/* 0x0150, */ 0x0000000000000000UL,
|
||||
/* 0x0158, */ 0x0000000000000000UL,
|
||||
/* 0x0160, */ 0x0000000000000000UL,
|
||||
/* 0x0168, */ 0x0000000000000000UL,
|
||||
/* 0x0170, */ 0x0000000000000000UL,
|
||||
/* 0x0178, */ 0x0000000000000000UL,
|
||||
/* 0x0180, */ 0x0000000000000000UL,
|
||||
/* 0x0188, */ 0x0000000000000000UL,
|
||||
/* 0x0190, */ 0x0000000000000000UL,
|
||||
/* 0x0198, */ 0x0000000000000000UL,
|
||||
/* 0x01a0, */ 0x0000000000000000UL,
|
||||
/* 0x01a8, */ 0x0000000000000000UL,
|
||||
/* 0x01b0, */ 0x0000000000000000UL,
|
||||
/* 0x01b8, */ 0x0000000000000000UL,
|
||||
/* 0x01c0, */ 0x0000000000000000UL,
|
||||
/* 0x01c8, */ 0x0000000000000000UL,
|
||||
/* 0x01d0, */ 0x0000000000000000UL,
|
||||
/* 0x01d8, */ 0x0000000000000000UL,
|
||||
/* 0x01e0, */ 0x0000000000000000UL,
|
||||
/* 0x01e8, */ 0x0000000000000000UL,
|
||||
/* 0x01f0, */ 0x0000000000000000UL,
|
||||
/* 0x01f8, */ 0x0000000000000000UL,
|
||||
/* 0x0200, */ 0x0000000000000000UL,
|
||||
/* 0x0208, */ 0x0000000000000000UL,
|
||||
/* 0x0210, */ 0x0000000000000000UL,
|
||||
/* 0x0218, */ 0x0000000000000000UL,
|
||||
/* 0x0220, */ 0x0000000000000000UL,
|
||||
/* 0x0228, */ 0x0000000000000000UL,
|
||||
/* 0x0230, */ 0x0000000000000000UL,
|
||||
/* 0x0238, */ 0x0000000000000000UL,
|
||||
/* 0x0240, */ 0x0000000000000000UL,
|
||||
/* 0x0248, */ 0x0000000000000000UL,
|
||||
/* 0x0250, */ 0x0000000000000000UL,
|
||||
/* 0x0258, */ 0x0000000000000000UL,
|
||||
/* 0x0260, */ 0x000C0C030000FFF0UL,
|
||||
/* 0x0268, */ 0x001410010000FFF0UL,
|
||||
/* 0x0270, */ 0x001404010000FFF0UL,
|
||||
/* 0x0278, */ 0x000C08020000FFF0UL,
|
||||
/* 0x0280, */ 0x0000000000000000UL,
|
||||
/* 0x0288, */ 0x0000000000000000UL,
|
||||
/* 0x0290, */ 0x001410010000FFF0UL,
|
||||
/* 0x0298, */ 0x001404010000FFF0UL,
|
||||
/* 0x02a0, */ 0x0000000000000000UL,
|
||||
/* 0x02a8, */ 0x0000000000000000UL,
|
||||
/* 0x02b0, */ 0x0000000000000000UL,
|
||||
/* 0x02b8, */ 0x0000000000000000UL,
|
||||
/* 0x02c0, */ 0x0000000000000000UL,
|
||||
/* 0x02c8, */ 0x0000000000000000UL,
|
||||
/* 0x02d0, */ 0x0000000000000000UL,
|
||||
/* 0x02d8, */ 0x0000000000000000UL,
|
||||
/* 0x02e0, */ 0x0000000000000000UL,
|
||||
/* 0x02e8, */ 0x0000000000000000UL,
|
||||
/* 0x02f0, */ 0x0000000000000000UL,
|
||||
/* 0x02f8, */ 0x0000000000000000UL,
|
||||
/* 0x0300, */ 0x0000000000000000UL,
|
||||
/* 0x0308, */ 0x0000000000000000UL,
|
||||
/* 0x0310, */ 0x0000000000000000UL,
|
||||
/* 0x0318, */ 0x0000000000000000UL,
|
||||
/* 0x0320, */ 0x0000000000000000UL,
|
||||
/* 0x0328, */ 0x0000000000000000UL,
|
||||
/* 0x0330, */ 0x0000000000000000UL,
|
||||
/* 0x0338, */ 0x0000000000000000UL,
|
||||
/* 0x0340, */ 0x0000000000000000UL,
|
||||
/* 0x0348, */ 0x0000000000000000UL,
|
||||
/* 0x0350, */ 0x0000000000000000UL,
|
||||
/* 0x0358, */ 0x0000000000000000UL,
|
||||
/* 0x0360, */ 0x0000000000000000UL,
|
||||
/* 0x0368, */ 0x0000000000000000UL,
|
||||
};
|
||||
|
||||
static uint64_t qoswt_be[] = {
|
||||
/* 0x0000, */ 0x0000000000000000UL,
|
||||
/* 0x0008, */ 0x0000000000000000UL,
|
||||
/* 0x0010, */ 0x0000000000000000UL,
|
||||
/* 0x0018, */ 0x0000000000000000UL,
|
||||
/* 0x0020, */ 0x0000000000000000UL,
|
||||
/* 0x0028, */ 0x0000000000000000UL,
|
||||
/* 0x0030, */ 0x0000000000000000UL,
|
||||
/* 0x0038, */ 0x0000000000000000UL,
|
||||
/* 0x0040, */ 0x0000000000000000UL,
|
||||
/* 0x0048, */ 0x0000000000000000UL,
|
||||
/* 0x0050, */ 0x0000000000000000UL,
|
||||
/* 0x0058, */ 0x0000000000000000UL,
|
||||
/* 0x0060, */ 0x0000000000000000UL,
|
||||
/* 0x0068, */ 0x0000000000000000UL,
|
||||
/* 0x0070, */ 0x0000000000000000UL,
|
||||
/* 0x0078, */ 0x0000000000000000UL,
|
||||
/* 0x0080, */ 0x0000000000000000UL,
|
||||
/* 0x0088, */ 0x0000000000000000UL,
|
||||
/* 0x0090, */ 0x0000000000000000UL,
|
||||
/* 0x0098, */ 0x0000000000000000UL,
|
||||
/* 0x00a0, */ 0x0000000000000000UL,
|
||||
/* 0x00a8, */ 0x0000000000000000UL,
|
||||
/* 0x00b0, */ 0x0000000000000000UL,
|
||||
/* 0x00b8, */ 0x0000000000000000UL,
|
||||
/* 0x00c0, */ 0x0000000000000000UL,
|
||||
/* 0x00c8, */ 0x0000000000000000UL,
|
||||
/* 0x00d0, */ 0x0000000000000000UL,
|
||||
/* 0x00d8, */ 0x0000000000000000UL,
|
||||
/* 0x00e0, */ 0x0000000000000000UL,
|
||||
/* 0x00e8, */ 0x0000000000000000UL,
|
||||
/* 0x00f0, */ 0x0000000000000000UL,
|
||||
/* 0x00f8, */ 0x0000000000000000UL,
|
||||
/* 0x0100, */ 0x0000000000000000UL,
|
||||
/* 0x0108, */ 0x0000000000000000UL,
|
||||
/* 0x0110, */ 0x0000000000000000UL,
|
||||
/* 0x0118, */ 0x0000000000000000UL,
|
||||
/* 0x0120, */ 0x0000000000000000UL,
|
||||
/* 0x0128, */ 0x0000000000000000UL,
|
||||
/* 0x0130, */ 0x0000000000000000UL,
|
||||
/* 0x0138, */ 0x0000000000000000UL,
|
||||
/* 0x0140, */ 0x0000000000000000UL,
|
||||
/* 0x0148, */ 0x0000000000000000UL,
|
||||
/* 0x0150, */ 0x0000000000000000UL,
|
||||
/* 0x0158, */ 0x0000000000000000UL,
|
||||
/* 0x0160, */ 0x0000000000000000UL,
|
||||
/* 0x0168, */ 0x0000000000000000UL,
|
||||
/* 0x0170, */ 0x0000000000000000UL,
|
||||
/* 0x0178, */ 0x0000000000000000UL,
|
||||
/* 0x0180, */ 0x0000000000000000UL,
|
||||
/* 0x0188, */ 0x0000000000000000UL,
|
||||
/* 0x0190, */ 0x0000000000000000UL,
|
||||
/* 0x0198, */ 0x0000000000000000UL,
|
||||
/* 0x01a0, */ 0x0000000000000000UL,
|
||||
/* 0x01a8, */ 0x0000000000000000UL,
|
||||
/* 0x01b0, */ 0x0000000000000000UL,
|
||||
/* 0x01b8, */ 0x0000000000000000UL,
|
||||
/* 0x01c0, */ 0x0000000000000000UL,
|
||||
/* 0x01c8, */ 0x0000000000000000UL,
|
||||
/* 0x01d0, */ 0x0000000000000000UL,
|
||||
/* 0x01d8, */ 0x0000000000000000UL,
|
||||
/* 0x01e0, */ 0x0000000000000000UL,
|
||||
/* 0x01e8, */ 0x0000000000000000UL,
|
||||
/* 0x01f0, */ 0x0000000000000000UL,
|
||||
/* 0x01f8, */ 0x0000000000000000UL,
|
||||
/* 0x0200, */ 0x0000000000000000UL,
|
||||
/* 0x0208, */ 0x0000000000000000UL,
|
||||
/* 0x0210, */ 0x0000000000000000UL,
|
||||
/* 0x0218, */ 0x0000000000000000UL,
|
||||
/* 0x0220, */ 0x0000000000000000UL,
|
||||
/* 0x0228, */ 0x0000000000000000UL,
|
||||
/* 0x0230, */ 0x0000000000000000UL,
|
||||
/* 0x0238, */ 0x0000000000000000UL,
|
||||
/* 0x0240, */ 0x0000000000000000UL,
|
||||
/* 0x0248, */ 0x0000000000000000UL,
|
||||
/* 0x0250, */ 0x0000000000000000UL,
|
||||
/* 0x0258, */ 0x0000000000000000UL,
|
||||
/* 0x0260, */ 0x0000000000000000UL,
|
||||
/* 0x0268, */ 0x0000000000000000UL,
|
||||
/* 0x0270, */ 0x0000000000000000UL,
|
||||
/* 0x0278, */ 0x0000000000000000UL,
|
||||
/* 0x0280, */ 0x0000000000000000UL,
|
||||
/* 0x0288, */ 0x0000000000000000UL,
|
||||
/* 0x0290, */ 0x0000000000000000UL,
|
||||
/* 0x0298, */ 0x0000000000000000UL,
|
||||
/* 0x02a0, */ 0x0000000000000000UL,
|
||||
/* 0x02a8, */ 0x0000000000000000UL,
|
||||
/* 0x02b0, */ 0x0000000000000000UL,
|
||||
/* 0x02b8, */ 0x0000000000000000UL,
|
||||
/* 0x02c0, */ 0x0000000000000000UL,
|
||||
/* 0x02c8, */ 0x0000000000000000UL,
|
||||
/* 0x02d0, */ 0x0000000000000000UL,
|
||||
/* 0x02d8, */ 0x0000000000000000UL,
|
||||
/* 0x02e0, */ 0x0000000000000000UL,
|
||||
/* 0x02e8, */ 0x0000000000000000UL,
|
||||
/* 0x02f0, */ 0x0000000000000000UL,
|
||||
/* 0x02f8, */ 0x0000000000000000UL,
|
||||
/* 0x0300, */ 0x0000000000000000UL,
|
||||
/* 0x0308, */ 0x0000000000000000UL,
|
||||
/* 0x0310, */ 0x0000000000000000UL,
|
||||
/* 0x0318, */ 0x0000000000000000UL,
|
||||
/* 0x0320, */ 0x0000000000000000UL,
|
||||
/* 0x0328, */ 0x0000000000000000UL,
|
||||
/* 0x0330, */ 0x0000000000000000UL,
|
||||
/* 0x0338, */ 0x0000000000000000UL,
|
||||
/* 0x0340, */ 0x0000000000000000UL,
|
||||
/* 0x0348, */ 0x0000000000000000UL,
|
||||
/* 0x0350, */ 0x0000000000000000UL,
|
||||
/* 0x0358, */ 0x0000000000000000UL,
|
||||
/* 0x0360, */ 0x0000000000000000UL,
|
||||
/* 0x0368, */ 0x0000000000000000UL,
|
||||
};
|
554
drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v10.c
Normal file
554
drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v10.c
Normal file
|
@ -0,0 +1,554 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <debug.h>
|
||||
#include "../qos_common.h"
|
||||
#include "qos_init_m3_v10.h"
|
||||
|
||||
#define RCAR_QOS_VERSION "rev.0.19"
|
||||
|
||||
#define RCAR_QOS_NONE (3U)
|
||||
#define RCAR_QOS_TYPE_DEFAULT (0U)
|
||||
|
||||
#define RCAR_DRAM_SPLIT_LINEAR (0U)
|
||||
#define RCAR_DRAM_SPLIT_4CH (1U)
|
||||
#define RCAR_DRAM_SPLIT_2CH (2U)
|
||||
#define RCAR_DRAM_SPLIT_AUTO (3U)
|
||||
|
||||
#define RST_BASE (0xE6160000U)
|
||||
#define RST_MODEMR (RST_BASE + 0x0060U)
|
||||
|
||||
#define DBSC_BASE (0xE6790000U)
|
||||
#define DBSC_DBCAM0CNF0 (DBSC_BASE + 0x0900U)
|
||||
#define DBSC_DBCAM0CNF1 (DBSC_BASE + 0x0904U)
|
||||
#define DBSC_DBCAM0CNF2 (DBSC_BASE + 0x0908U)
|
||||
#define DBSC_DBCAM0CNF3 (DBSC_BASE + 0x090CU)
|
||||
#define DBSC_DBCAMDIS (DBSC_BASE + 0x09fCU)
|
||||
#define DBSC_DBSCHCNT0 (DBSC_BASE + 0x1000U)
|
||||
#define DBSC_DBSCHCNT1 (DBSC_BASE + 0x1004U)
|
||||
#define DBSC_DBSCHSZ0 (DBSC_BASE + 0x1010U)
|
||||
#define DBSC_DBSCHRW0 (DBSC_BASE + 0x1020U)
|
||||
#define DBSC_DBSCHQOS_0_0 (DBSC_BASE + 0x1030U)
|
||||
#define DBSC_DBSCHQOS_0_1 (DBSC_BASE + 0x1034U)
|
||||
#define DBSC_DBSCHQOS_0_2 (DBSC_BASE + 0x1038U)
|
||||
#define DBSC_DBSCHQOS_0_3 (DBSC_BASE + 0x103CU)
|
||||
#define DBSC_DBSCHQOS_1_0 (DBSC_BASE + 0x1040U)
|
||||
#define DBSC_DBSCHQOS_1_1 (DBSC_BASE + 0x1044U)
|
||||
#define DBSC_DBSCHQOS_1_2 (DBSC_BASE + 0x1048U)
|
||||
#define DBSC_DBSCHQOS_1_3 (DBSC_BASE + 0x104CU)
|
||||
#define DBSC_DBSCHQOS_2_0 (DBSC_BASE + 0x1050U)
|
||||
#define DBSC_DBSCHQOS_2_1 (DBSC_BASE + 0x1054U)
|
||||
#define DBSC_DBSCHQOS_2_2 (DBSC_BASE + 0x1058U)
|
||||
#define DBSC_DBSCHQOS_2_3 (DBSC_BASE + 0x105CU)
|
||||
#define DBSC_DBSCHQOS_3_0 (DBSC_BASE + 0x1060U)
|
||||
#define DBSC_DBSCHQOS_3_1 (DBSC_BASE + 0x1064U)
|
||||
#define DBSC_DBSCHQOS_3_2 (DBSC_BASE + 0x1068U)
|
||||
#define DBSC_DBSCHQOS_3_3 (DBSC_BASE + 0x106CU)
|
||||
#define DBSC_DBSCHQOS_4_0 (DBSC_BASE + 0x1070U)
|
||||
#define DBSC_DBSCHQOS_4_1 (DBSC_BASE + 0x1074U)
|
||||
#define DBSC_DBSCHQOS_4_2 (DBSC_BASE + 0x1078U)
|
||||
#define DBSC_DBSCHQOS_4_3 (DBSC_BASE + 0x107CU)
|
||||
#define DBSC_DBSCHQOS_5_0 (DBSC_BASE + 0x1080U)
|
||||
#define DBSC_DBSCHQOS_5_1 (DBSC_BASE + 0x1084U)
|
||||
#define DBSC_DBSCHQOS_5_2 (DBSC_BASE + 0x1088U)
|
||||
#define DBSC_DBSCHQOS_5_3 (DBSC_BASE + 0x108CU)
|
||||
#define DBSC_DBSCHQOS_6_0 (DBSC_BASE + 0x1090U)
|
||||
#define DBSC_DBSCHQOS_6_1 (DBSC_BASE + 0x1094U)
|
||||
#define DBSC_DBSCHQOS_6_2 (DBSC_BASE + 0x1098U)
|
||||
#define DBSC_DBSCHQOS_6_3 (DBSC_BASE + 0x109CU)
|
||||
#define DBSC_DBSCHQOS_7_0 (DBSC_BASE + 0x10A0U)
|
||||
#define DBSC_DBSCHQOS_7_1 (DBSC_BASE + 0x10A4U)
|
||||
#define DBSC_DBSCHQOS_7_2 (DBSC_BASE + 0x10A8U)
|
||||
#define DBSC_DBSCHQOS_7_3 (DBSC_BASE + 0x10ACU)
|
||||
#define DBSC_DBSCHQOS_8_0 (DBSC_BASE + 0x10B0U)
|
||||
#define DBSC_DBSCHQOS_8_1 (DBSC_BASE + 0x10B4U)
|
||||
#define DBSC_DBSCHQOS_8_2 (DBSC_BASE + 0x10B8U)
|
||||
#define DBSC_DBSCHQOS_8_3 (DBSC_BASE + 0x10BCU)
|
||||
#define DBSC_DBSCHQOS_9_0 (DBSC_BASE + 0x10C0U)
|
||||
#define DBSC_DBSCHQOS_9_1 (DBSC_BASE + 0x10C4U)
|
||||
#define DBSC_DBSCHQOS_9_2 (DBSC_BASE + 0x10C8U)
|
||||
#define DBSC_DBSCHQOS_9_3 (DBSC_BASE + 0x10CCU)
|
||||
#define DBSC_DBSCHQOS_10_0 (DBSC_BASE + 0x10D0U)
|
||||
#define DBSC_DBSCHQOS_10_1 (DBSC_BASE + 0x10D4U)
|
||||
#define DBSC_DBSCHQOS_10_2 (DBSC_BASE + 0x10D8U)
|
||||
#define DBSC_DBSCHQOS_10_3 (DBSC_BASE + 0x10DCU)
|
||||
#define DBSC_DBSCHQOS_11_0 (DBSC_BASE + 0x10E0U)
|
||||
#define DBSC_DBSCHQOS_11_1 (DBSC_BASE + 0x10E4U)
|
||||
#define DBSC_DBSCHQOS_11_2 (DBSC_BASE + 0x10E8U)
|
||||
#define DBSC_DBSCHQOS_11_3 (DBSC_BASE + 0x10ECU)
|
||||
#define DBSC_DBSCHQOS_12_0 (DBSC_BASE + 0x10F0U)
|
||||
#define DBSC_DBSCHQOS_12_1 (DBSC_BASE + 0x10F4U)
|
||||
#define DBSC_DBSCHQOS_12_2 (DBSC_BASE + 0x10F8U)
|
||||
#define DBSC_DBSCHQOS_12_3 (DBSC_BASE + 0x10FCU)
|
||||
#define DBSC_DBSCHQOS_13_0 (DBSC_BASE + 0x1100U)
|
||||
#define DBSC_DBSCHQOS_13_1 (DBSC_BASE + 0x1104U)
|
||||
#define DBSC_DBSCHQOS_13_2 (DBSC_BASE + 0x1108U)
|
||||
#define DBSC_DBSCHQOS_13_3 (DBSC_BASE + 0x110CU)
|
||||
#define DBSC_DBSCHQOS_14_0 (DBSC_BASE + 0x1110U)
|
||||
#define DBSC_DBSCHQOS_14_1 (DBSC_BASE + 0x1114U)
|
||||
#define DBSC_DBSCHQOS_14_2 (DBSC_BASE + 0x1118U)
|
||||
#define DBSC_DBSCHQOS_14_3 (DBSC_BASE + 0x111CU)
|
||||
#define DBSC_DBSCHQOS_15_0 (DBSC_BASE + 0x1120U)
|
||||
#define DBSC_DBSCHQOS_15_1 (DBSC_BASE + 0x1124U)
|
||||
#define DBSC_DBSCHQOS_15_2 (DBSC_BASE + 0x1128U)
|
||||
#define DBSC_DBSCHQOS_15_3 (DBSC_BASE + 0x112CU)
|
||||
#define DBSC_SCFCTST2 (DBSC_BASE + 0x170CU)
|
||||
|
||||
#define AXI_BASE (0xE6784000U)
|
||||
#define AXI_ADSPLCR0 (AXI_BASE + 0x0008U)
|
||||
#define AXI_ADSPLCR1 (AXI_BASE + 0x000CU)
|
||||
#define AXI_ADSPLCR2 (AXI_BASE + 0x0010U)
|
||||
#define AXI_ADSPLCR3 (AXI_BASE + 0x0014U)
|
||||
#define ADSPLCR0_ADRMODE_DEFAULT ((uint32_t)0U << 31U)
|
||||
#define ADSPLCR0_ADRMODE_GEN2 ((uint32_t)1U << 31U)
|
||||
#define ADSPLCR0_SPLITSEL(x) ((uint32_t)(x) << 16U)
|
||||
#define ADSPLCR0_AREA(x) ((uint32_t)(x) << 8U)
|
||||
#define ADSPLCR0_SWP (0x0CU)
|
||||
|
||||
#define MSTAT_BASE (0xE67E0000U)
|
||||
#define MSTAT_FIX_QOS_BANK0 (MSTAT_BASE + 0x0000U)
|
||||
#define MSTAT_FIX_QOS_BANK1 (MSTAT_BASE + 0x1000U)
|
||||
#define MSTAT_BE_QOS_BANK0 (MSTAT_BASE + 0x2000U)
|
||||
#define MSTAT_BE_QOS_BANK1 (MSTAT_BASE + 0x3000U)
|
||||
#define MSTAT_SL_INIT (MSTAT_BASE + 0x8000U)
|
||||
#define MSTAT_REF_ARS (MSTAT_BASE + 0x8004U)
|
||||
#define MSTAT_STATQC (MSTAT_BASE + 0x8008U)
|
||||
|
||||
#define RALLOC_BASE (0xE67F0000U)
|
||||
#define RALLOC_RAS (RALLOC_BASE + 0x0000U)
|
||||
#define RALLOC_FIXTH (RALLOC_BASE + 0x0004U)
|
||||
#define RALLOC_RAEN (RALLOC_BASE + 0x0018U)
|
||||
#define RALLOC_REGGD (RALLOC_BASE + 0x0020U)
|
||||
#define RALLOC_DANN (RALLOC_BASE + 0x0030U)
|
||||
#define RALLOC_DANT (RALLOC_BASE + 0x0038U)
|
||||
#define RALLOC_EC (RALLOC_BASE + 0x003CU)
|
||||
#define RALLOC_EMS (RALLOC_BASE + 0x0040U)
|
||||
#define RALLOC_FSS (RALLOC_BASE + 0x0048U)
|
||||
#define RALLOC_INSFC (RALLOC_BASE + 0x0050U)
|
||||
#define RALLOC_BERR (RALLOC_BASE + 0x0054U)
|
||||
#define RALLOC_RACNT0 (RALLOC_BASE + 0x0080U)
|
||||
|
||||
#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
|
||||
static const mstat_slot_t mstat_fix[] = {
|
||||
{0x0000U, 0x0000000000000000UL},
|
||||
{0x0008U, 0x0000000000000000UL},
|
||||
{0x0010U, 0x0000000000000000UL},
|
||||
{0x0018U, 0x0000000000000000UL},
|
||||
{0x0020U, 0x0000000000000000UL},
|
||||
{0x0028U, 0x0000000000000000UL},
|
||||
{0x0030U, 0x001004030000FFFFUL},
|
||||
{0x0038U, 0x001004030000FFFFUL},
|
||||
{0x0040U, 0x001414090000FFFFUL},
|
||||
{0x0048U, 0x0000000000000000UL},
|
||||
{0x0050U, 0x001410010000FFFFUL},
|
||||
{0x0058U, 0x00140C090000FFFFUL},
|
||||
{0x0060U, 0x00140C090000FFFFUL},
|
||||
{0x0068U, 0x0000000000000000UL},
|
||||
{0x0070U, 0x001410010000FFFFUL},
|
||||
{0x0078U, 0x001004020000FFFFUL},
|
||||
{0x0080U, 0x0000000000000000UL},
|
||||
{0x0088U, 0x001414090000FFFFUL},
|
||||
{0x0090U, 0x001408060000FFFFUL},
|
||||
{0x0098U, 0x0000000000000000UL},
|
||||
{0x00A0U, 0x000C08020000FFFFUL},
|
||||
{0x00A8U, 0x000C04010000FFFFUL},
|
||||
{0x00B0U, 0x000C04010000FFFFUL},
|
||||
{0x00B8U, 0x0000000000000000UL},
|
||||
{0x00C0U, 0x000C08020000FFFFUL},
|
||||
{0x00C8U, 0x000C04010000FFFFUL},
|
||||
{0x00D0U, 0x000C04010000FFFFUL},
|
||||
{0x00D8U, 0x000C04030000FFFFUL},
|
||||
{0x00E0U, 0x000C100F0000FFFFUL},
|
||||
{0x00E8U, 0x0000000000000000UL},
|
||||
{0x00F0U, 0x001010080000FFFFUL},
|
||||
{0x00F8U, 0x0000000000000000UL},
|
||||
{0x0100U, 0x0000000000000000UL},
|
||||
{0x0108U, 0x0000000000000000UL},
|
||||
{0x0110U, 0x001010080000FFFFUL},
|
||||
{0x0118U, 0x0000000000000000UL},
|
||||
{0x0120U, 0x0000000000000000UL},
|
||||
{0x0128U, 0x0000000000000000UL},
|
||||
{0x0130U, 0x0000000000000000UL},
|
||||
{0x0138U, 0x00100C0A0000FFFFUL},
|
||||
{0x0140U, 0x0000000000000000UL},
|
||||
{0x0148U, 0x0000000000000000UL},
|
||||
{0x0150U, 0x00100C0A0000FFFFUL},
|
||||
{0x0158U, 0x0000000000000000UL},
|
||||
{0x0160U, 0x00100C0A0000FFFFUL},
|
||||
{0x0168U, 0x0000000000000000UL},
|
||||
{0x0170U, 0x0000000000000000UL},
|
||||
{0x0178U, 0x001008050000FFFFUL},
|
||||
{0x0180U, 0x0000000000000000UL},
|
||||
{0x0188U, 0x0000000000000000UL},
|
||||
{0x0190U, 0x001028280000FFFFUL},
|
||||
{0x0198U, 0x0000000000000000UL},
|
||||
{0x01A0U, 0x00100C0A0000FFFFUL},
|
||||
{0x01A8U, 0x0000000000000000UL},
|
||||
{0x01B0U, 0x0000000000000000UL},
|
||||
{0x01B8U, 0x0000000000000000UL},
|
||||
{0x01C0U, 0x0000000000000000UL},
|
||||
{0x01C8U, 0x0000000000000000UL},
|
||||
{0x01D0U, 0x0000000000000000UL},
|
||||
{0x01D8U, 0x0000000000000000UL},
|
||||
{0x01E0U, 0x0000000000000000UL},
|
||||
{0x01E8U, 0x0000000000000000UL},
|
||||
{0x01F0U, 0x0000000000000000UL},
|
||||
{0x01F8U, 0x0000000000000000UL},
|
||||
{0x0200U, 0x0000000000000000UL},
|
||||
{0x0208U, 0x0000000000000000UL},
|
||||
{0x0210U, 0x0000000000000000UL},
|
||||
{0x0218U, 0x0000000000000000UL},
|
||||
{0x0220U, 0x0000000000000000UL},
|
||||
{0x0228U, 0x0000000000000000UL},
|
||||
{0x0230U, 0x0000000000000000UL},
|
||||
{0x0238U, 0x0000000000000000UL},
|
||||
{0x0240U, 0x0000000000000000UL},
|
||||
{0x0248U, 0x0000000000000000UL},
|
||||
{0x0250U, 0x0000000000000000UL},
|
||||
{0x0258U, 0x0000000000000000UL},
|
||||
{0x0260U, 0x0000000000000000UL},
|
||||
{0x0268U, 0x001408010000FFFFUL},
|
||||
{0x0270U, 0x001404010000FFFFUL},
|
||||
{0x0278U, 0x0000000000000000UL},
|
||||
{0x0280U, 0x0000000000000000UL},
|
||||
{0x0288U, 0x0000000000000000UL},
|
||||
{0x0290U, 0x001408010000FFFFUL},
|
||||
{0x0298U, 0x001404010000FFFFUL},
|
||||
{0x02A0U, 0x000C04010000FFFFUL},
|
||||
{0x02A8U, 0x000C04010000FFFFUL},
|
||||
{0x02B0U, 0x001404010000FFFFUL},
|
||||
{0x02B8U, 0x0000000000000000UL},
|
||||
{0x02C0U, 0x0000000000000000UL},
|
||||
{0x02C8U, 0x0000000000000000UL},
|
||||
{0x02D0U, 0x000C04010000FFFFUL},
|
||||
{0x02D8U, 0x000C04010000FFFFUL},
|
||||
{0x02E0U, 0x001404010000FFFFUL},
|
||||
{0x02E8U, 0x0000000000000000UL},
|
||||
{0x02F0U, 0x0000000000000000UL},
|
||||
{0x02F8U, 0x0000000000000000UL},
|
||||
{0x0300U, 0x0000000000000000UL},
|
||||
{0x0308U, 0x0000000000000000UL},
|
||||
{0x0310U, 0x0000000000000000UL},
|
||||
{0x0318U, 0x0000000000000000UL},
|
||||
{0x0320U, 0x0000000000000000UL},
|
||||
{0x0328U, 0x0000000000000000UL},
|
||||
{0x0330U, 0x0000000000000000UL},
|
||||
{0x0338U, 0x0000000000000000UL},
|
||||
{0x0340U, 0x0000000000000000UL},
|
||||
{0x0348U, 0x0000000000000000UL},
|
||||
{0x0350U, 0x0000000000000000UL},
|
||||
};
|
||||
|
||||
static const mstat_slot_t mstat_be[] = {
|
||||
{0x0000U, 0x001200100C89C401UL},
|
||||
{0x0008U, 0x001200100C89C401UL},
|
||||
{0x0010U, 0x001200100C89C401UL},
|
||||
{0x0018U, 0x001200100C89C401UL},
|
||||
{0x0020U, 0x0000000000000000UL},
|
||||
{0x0028U, 0x001100100C803401UL},
|
||||
{0x0030U, 0x0000000000000000UL},
|
||||
{0x0038U, 0x0000000000000000UL},
|
||||
{0x0040U, 0x0000000000000000UL},
|
||||
{0x0048U, 0x0000000000000000UL},
|
||||
{0x0050U, 0x0000000000000000UL},
|
||||
{0x0058U, 0x0000000000000000UL},
|
||||
{0x0060U, 0x0000000000000000UL},
|
||||
{0x0068U, 0x0000000000000000UL},
|
||||
{0x0070U, 0x0000000000000000UL},
|
||||
{0x0078U, 0x0000000000000000UL},
|
||||
{0x0080U, 0x0000000000000000UL},
|
||||
{0x0088U, 0x0000000000000000UL},
|
||||
{0x0090U, 0x0000000000000000UL},
|
||||
{0x0098U, 0x0000000000000000UL},
|
||||
{0x00A0U, 0x0000000000000000UL},
|
||||
{0x00A8U, 0x0000000000000000UL},
|
||||
{0x00B0U, 0x0000000000000000UL},
|
||||
{0x00B8U, 0x0000000000000000UL},
|
||||
{0x00C0U, 0x0000000000000000UL},
|
||||
{0x00C8U, 0x0000000000000000UL},
|
||||
{0x00D0U, 0x0000000000000000UL},
|
||||
{0x00D8U, 0x0000000000000000UL},
|
||||
{0x00E0U, 0x0000000000000000UL},
|
||||
{0x00E8U, 0x0000000000000000UL},
|
||||
{0x00F0U, 0x0000000000000000UL},
|
||||
{0x00F8U, 0x0000000000000000UL},
|
||||
{0x0100U, 0x0000000000000000UL},
|
||||
{0x0108U, 0x0000000000000000UL},
|
||||
{0x0110U, 0x0000000000000000UL},
|
||||
{0x0118U, 0x0000000000000000UL},
|
||||
{0x0120U, 0x0000000000000000UL},
|
||||
{0x0128U, 0x0000000000000000UL},
|
||||
{0x0130U, 0x0000000000000000UL},
|
||||
{0x0138U, 0x0000000000000000UL},
|
||||
{0x0140U, 0x0000000000000000UL},
|
||||
{0x0148U, 0x0000000000000000UL},
|
||||
{0x0150U, 0x0000000000000000UL},
|
||||
{0x0158U, 0x0000000000000000UL},
|
||||
{0x0160U, 0x0000000000000000UL},
|
||||
{0x0168U, 0x0000000000000000UL},
|
||||
{0x0170U, 0x0000000000000000UL},
|
||||
{0x0178U, 0x0000000000000000UL},
|
||||
{0x0180U, 0x0000000000000000UL},
|
||||
{0x0188U, 0x0000000000000000UL},
|
||||
{0x0190U, 0x0000000000000000UL},
|
||||
{0x0198U, 0x0000000000000000UL},
|
||||
{0x01A0U, 0x0000000000000000UL},
|
||||
{0x01A8U, 0x0000000000000000UL},
|
||||
{0x01B0U, 0x0000000000000000UL},
|
||||
{0x01B8U, 0x0000000000000000UL},
|
||||
{0x01C0U, 0x001100500C8FFC01UL},
|
||||
{0x01C8U, 0x001100500C8FFC01UL},
|
||||
{0x01D0U, 0x001100500C8FFC01UL},
|
||||
{0x01D8U, 0x001100500C8FFC01UL},
|
||||
{0x01E0U, 0x0000000000000000UL},
|
||||
{0x01E8U, 0x001200100C803401UL},
|
||||
{0x01F0U, 0x001100100C80FC01UL},
|
||||
{0x01F8U, 0x0000000000000000UL},
|
||||
{0x0200U, 0x0000000000000000UL},
|
||||
{0x0208U, 0x001200100C80FC01UL},
|
||||
{0x0210U, 0x001100100C80FC01UL},
|
||||
{0x0218U, 0x001100100C825801UL},
|
||||
{0x0220U, 0x001100100C825801UL},
|
||||
{0x0228U, 0x0000000000000000UL},
|
||||
{0x0230U, 0x001100100C825801UL},
|
||||
{0x0238U, 0x001100100C825801UL},
|
||||
{0x0240U, 0x001200100C8BB801UL},
|
||||
{0x0248U, 0x001100100C8EA401UL},
|
||||
{0x0250U, 0x001200100C8BB801UL},
|
||||
{0x0258U, 0x001100100C8EA401UL},
|
||||
{0x0260U, 0x001100100C84E401UL},
|
||||
{0x0268U, 0x0000000000000000UL},
|
||||
{0x0270U, 0x0000000000000000UL},
|
||||
{0x0278U, 0x001100100C81F401UL},
|
||||
{0x0280U, 0x0000000000000000UL},
|
||||
{0x0288U, 0x0000000000000000UL},
|
||||
{0x0290U, 0x0000000000000000UL},
|
||||
{0x0298U, 0x0000000000000000UL},
|
||||
{0x02A0U, 0x0000000000000000UL},
|
||||
{0x02A8U, 0x0000000000000000UL},
|
||||
{0x02B0U, 0x0000000000000000UL},
|
||||
{0x02B8U, 0x001100100C803401UL},
|
||||
{0x02C0U, 0x0000000000000000UL},
|
||||
{0x02C8U, 0x0000000000000000UL},
|
||||
{0x02D0U, 0x0000000000000000UL},
|
||||
{0x02D8U, 0x0000000000000000UL},
|
||||
{0x02E0U, 0x0000000000000000UL},
|
||||
{0x02E8U, 0x001100100C803401UL},
|
||||
{0x02F0U, 0x001100300C8FFC01UL},
|
||||
{0x02F8U, 0x001100500C8FFC01UL},
|
||||
{0x0300U, 0x0000000000000000UL},
|
||||
{0x0308U, 0x001100300C8FFC01UL},
|
||||
{0x0310U, 0x001100500C8FFC01UL},
|
||||
{0x0318U, 0x001200100C803401UL},
|
||||
{0x0320U, 0x0000000000000000UL},
|
||||
{0x0328U, 0x0000000000000000UL},
|
||||
{0x0330U, 0x0000000000000000UL},
|
||||
{0x0338U, 0x0000000000000000UL},
|
||||
{0x0340U, 0x0000000000000000UL},
|
||||
{0x0348U, 0x0000000000000000UL},
|
||||
{0x0350U, 0x0000000000000000UL},
|
||||
};
|
||||
#endif
|
||||
|
||||
static void dbsc_setting(void)
|
||||
{
|
||||
uint32_t md = 0;
|
||||
|
||||
/* BUFCAM settings */
|
||||
/* DBSC_DBCAM0CNF0 not set */
|
||||
io_write_32(DBSC_DBCAM0CNF1, 0x00043218); /* dbcam0cnf1 */
|
||||
io_write_32(DBSC_DBCAM0CNF2, 0x000000F4); /* dbcam0cnf2 */
|
||||
io_write_32(DBSC_DBCAM0CNF3, 0x00000000); /* dbcam0cnf3 */
|
||||
io_write_32(DBSC_DBSCHCNT0, 0x080F0037); /* dbschcnt0 */
|
||||
/* DBSC_DBSCHCNT1 not set */
|
||||
io_write_32(DBSC_DBSCHSZ0, 0x00000001); /* dbschsz0 */
|
||||
io_write_32(DBSC_DBSCHRW0, 0x22421111); /* dbschrw0 */
|
||||
|
||||
md = (*((volatile uint32_t *)RST_MODEMR) & 0x000A0000) >> 17;
|
||||
|
||||
switch (md) {
|
||||
case 0x0:
|
||||
/* DDR3200 */
|
||||
io_write_32(DBSC_SCFCTST2, 0x012F1123);
|
||||
break;
|
||||
case 0x1: /* MD19=0,MD17=1 : LPDDR4-3000, 4GByte(1GByte x4) */
|
||||
/* DDR2800 */
|
||||
io_write_32(DBSC_SCFCTST2, 0x012F1123);
|
||||
break;
|
||||
case 0x4: /* MD19=1,MD17=0 : LPDDR4-2400, 4GByte(1GByte x4) */
|
||||
/* DDR2400 */
|
||||
io_write_32(DBSC_SCFCTST2, 0x012F1123);
|
||||
break;
|
||||
default: /* MD19=1,MD17=1 : LPDDR4-1600, 4GByte(1GByte x4) */
|
||||
/* DDR1600 */
|
||||
io_write_32(DBSC_SCFCTST2, 0x012F1123);
|
||||
break;
|
||||
}
|
||||
|
||||
/* QoS Settings */
|
||||
io_write_32(DBSC_DBSCHQOS_0_0, 0x00000F00);
|
||||
io_write_32(DBSC_DBSCHQOS_0_1, 0x00000B00);
|
||||
io_write_32(DBSC_DBSCHQOS_0_2, 0x00000000);
|
||||
io_write_32(DBSC_DBSCHQOS_0_3, 0x00000000);
|
||||
/* DBSC_DBSCHQOS_1_0 not set */
|
||||
/* DBSC_DBSCHQOS_1_1 not set */
|
||||
/* DBSC_DBSCHQOS_1_2 not set */
|
||||
/* DBSC_DBSCHQOS_1_3 not set */
|
||||
/* DBSC_DBSCHQOS_2_0 not set */
|
||||
/* DBSC_DBSCHQOS_2_1 not set */
|
||||
/* DBSC_DBSCHQOS_2_2 not set */
|
||||
/* DBSC_DBSCHQOS_2_3 not set */
|
||||
/* DBSC_DBSCHQOS_3_0 not set */
|
||||
/* DBSC_DBSCHQOS_3_1 not set */
|
||||
/* DBSC_DBSCHQOS_3_2 not set */
|
||||
/* DBSC_DBSCHQOS_3_3 not set */
|
||||
io_write_32(DBSC_DBSCHQOS_4_0, 0x00000300);
|
||||
io_write_32(DBSC_DBSCHQOS_4_1, 0x000002F0);
|
||||
io_write_32(DBSC_DBSCHQOS_4_2, 0x00000200);
|
||||
io_write_32(DBSC_DBSCHQOS_4_3, 0x00000100);
|
||||
/* DBSC_DBSCHQOS_5_0 not set */
|
||||
/* DBSC_DBSCHQOS_5_1 not set */
|
||||
/* DBSC_DBSCHQOS_5_2 not set */
|
||||
/* DBSC_DBSCHQOS_5_3 not set */
|
||||
/* DBSC_DBSCHQOS_6_0 not set */
|
||||
/* DBSC_DBSCHQOS_6_1 not set */
|
||||
/* DBSC_DBSCHQOS_6_2 not set */
|
||||
/* DBSC_DBSCHQOS_6_3 not set */
|
||||
/* DBSC_DBSCHQOS_7_0 not set */
|
||||
/* DBSC_DBSCHQOS_7_1 not set */
|
||||
/* DBSC_DBSCHQOS_7_2 not set */
|
||||
/* DBSC_DBSCHQOS_7_3 not set */
|
||||
/* DBSC_DBSCHQOS_8_0 not set */
|
||||
/* DBSC_DBSCHQOS_8_1 not set */
|
||||
/* DBSC_DBSCHQOS_8_2 not set */
|
||||
/* DBSC_DBSCHQOS_8_3 not set */
|
||||
io_write_32(DBSC_DBSCHQOS_9_0, 0x00000300);
|
||||
io_write_32(DBSC_DBSCHQOS_9_1, 0x000002F0);
|
||||
io_write_32(DBSC_DBSCHQOS_9_2, 0x00000200);
|
||||
io_write_32(DBSC_DBSCHQOS_9_3, 0x00000100);
|
||||
/* DBSC_DBSCHQOS_10_0 not set */
|
||||
/* DBSC_DBSCHQOS_10_1 not set */
|
||||
/* DBSC_DBSCHQOS_10_2 not set */
|
||||
/* DBSC_DBSCHQOS_10_3 not set */
|
||||
/* DBSC_DBSCHQOS_11_0 not set */
|
||||
/* DBSC_DBSCHQOS_11_1 not set */
|
||||
/* DBSC_DBSCHQOS_11_2 not set */
|
||||
/* DBSC_DBSCHQOS_11_3 not set */
|
||||
/* DBSC_DBSCHQOS_12_0 not set */
|
||||
/* DBSC_DBSCHQOS_12_1 not set */
|
||||
/* DBSC_DBSCHQOS_12_2 not set */
|
||||
/* DBSC_DBSCHQOS_12_3 not set */
|
||||
io_write_32(DBSC_DBSCHQOS_13_0, 0x00000100);
|
||||
io_write_32(DBSC_DBSCHQOS_13_1, 0x000000F0);
|
||||
io_write_32(DBSC_DBSCHQOS_13_2, 0x000000A0);
|
||||
io_write_32(DBSC_DBSCHQOS_13_3, 0x00000040);
|
||||
io_write_32(DBSC_DBSCHQOS_14_0, 0x000000C0);
|
||||
io_write_32(DBSC_DBSCHQOS_14_1, 0x000000B0);
|
||||
io_write_32(DBSC_DBSCHQOS_14_2, 0x00000080);
|
||||
io_write_32(DBSC_DBSCHQOS_14_3, 0x00000040);
|
||||
io_write_32(DBSC_DBSCHQOS_15_0, 0x00000040);
|
||||
io_write_32(DBSC_DBSCHQOS_15_1, 0x00000030);
|
||||
io_write_32(DBSC_DBSCHQOS_15_2, 0x00000020);
|
||||
io_write_32(DBSC_DBSCHQOS_15_3, 0x00000010);
|
||||
}
|
||||
|
||||
void qos_init_m3_v10(void)
|
||||
{
|
||||
dbsc_setting();
|
||||
|
||||
/* DRAM Split Address mapping */
|
||||
#if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH
|
||||
#if RCAR_LSI == RCAR_M3
|
||||
#error "Don't set DRAM Split 4ch(M3)"
|
||||
#else
|
||||
ERROR("DRAM Split 4ch not supported.(M3)");
|
||||
panic();
|
||||
#endif
|
||||
#elif (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH) || \
|
||||
(RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO)
|
||||
NOTICE("BL2: DRAM Split is 2ch\n");
|
||||
io_write_32(AXI_ADSPLCR0, 0x00000000U);
|
||||
io_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT
|
||||
| ADSPLCR0_SPLITSEL(0xFFU)
|
||||
| ADSPLCR0_AREA(0x1CU)
|
||||
| ADSPLCR0_SWP);
|
||||
io_write_32(AXI_ADSPLCR2, 0x089A0000U);
|
||||
io_write_32(AXI_ADSPLCR3, 0x00000000U);
|
||||
#else
|
||||
NOTICE("BL2: DRAM Split is OFF\n");
|
||||
#endif
|
||||
|
||||
#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
|
||||
#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
|
||||
NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
|
||||
#endif
|
||||
|
||||
/* Resource Alloc setting */
|
||||
io_write_32(RALLOC_RAS, 0x00000028U);
|
||||
io_write_32(RALLOC_FIXTH, 0x000F0005U);
|
||||
io_write_32(RALLOC_REGGD, 0x00000000U);
|
||||
io_write_64(RALLOC_DANN, 0x0101010102020201UL);
|
||||
io_write_32(RALLOC_DANT, 0x00100804U);
|
||||
io_write_32(RALLOC_EC, 0x00000000U);
|
||||
io_write_64(RALLOC_EMS, 0x0000000000000000UL);
|
||||
io_write_32(RALLOC_FSS, 0x000003e8U);
|
||||
io_write_32(RALLOC_INSFC, 0xC7840001U);
|
||||
io_write_32(RALLOC_BERR, 0x00000000U);
|
||||
io_write_32(RALLOC_RACNT0, 0x00000000U);
|
||||
|
||||
/* MSTAT setting */
|
||||
io_write_32(MSTAT_SL_INIT,
|
||||
SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT | SL_INIT_SSLOTCLK);
|
||||
io_write_32(MSTAT_REF_ARS, 0x00330000U);
|
||||
|
||||
/* MSTAT SRAM setting */
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
|
||||
io_write_64(MSTAT_FIX_QOS_BANK0 + mstat_fix[i].addr,
|
||||
mstat_fix[i].value);
|
||||
io_write_64(MSTAT_FIX_QOS_BANK1 + mstat_fix[i].addr,
|
||||
mstat_fix[i].value);
|
||||
}
|
||||
for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
|
||||
io_write_64(MSTAT_BE_QOS_BANK0 + mstat_be[i].addr,
|
||||
mstat_be[i].value);
|
||||
io_write_64(MSTAT_BE_QOS_BANK1 + mstat_be[i].addr,
|
||||
mstat_be[i].value);
|
||||
}
|
||||
}
|
||||
|
||||
/* 3DG bus Leaf setting */
|
||||
io_write_32(0xFD820808U, 0x00001234U);
|
||||
io_write_32(0xFD820800U, 0x00000006U);
|
||||
io_write_32(0xFD821800U, 0x00000006U);
|
||||
io_write_32(0xFD822800U, 0x00000006U);
|
||||
io_write_32(0xFD823800U, 0x00000006U);
|
||||
io_write_32(0xFD824800U, 0x00000006U);
|
||||
io_write_32(0xFD825800U, 0x00000006U);
|
||||
io_write_32(0xFD826800U, 0x00000006U);
|
||||
io_write_32(0xFD827800U, 0x00000006U);
|
||||
|
||||
/* RT bus Leaf setting */
|
||||
io_write_32(0xFFC50800U, 0x00000000U);
|
||||
io_write_32(0xFFC51800U, 0x00000000U);
|
||||
|
||||
/* Resource Alloc start */
|
||||
io_write_32(RALLOC_RAEN, 0x00000001U);
|
||||
|
||||
/* MSTAT start */
|
||||
io_write_32(MSTAT_STATQC, 0x00000001U);
|
||||
#else
|
||||
NOTICE("BL2: QoS is None\n");
|
||||
|
||||
/* Resource Alloc setting */
|
||||
io_write_32(RALLOC_EC, 0x00000000U);
|
||||
/* Resource Alloc start */
|
||||
io_write_32(RALLOC_RAEN, 0x00000001U);
|
||||
#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
|
||||
}
|
12
drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v10.h
Normal file
12
drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v10.h
Normal file
|
@ -0,0 +1,12 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef QOS_INIT_H_M3_V10__
|
||||
#define QOS_INIT_H_M3_V10__
|
||||
|
||||
void qos_init_m3_v10(void);
|
||||
|
||||
#endif /* QOS_INIT_H_M3_V10__ */
|
240
drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.c
Normal file
240
drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.c
Normal file
|
@ -0,0 +1,240 @@
|
|||
/*
|
||||
* Copyright (c) 2017-2018, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <debug.h>
|
||||
#include "../qos_common.h"
|
||||
#include "../qos_reg.h"
|
||||
#include "qos_init_m3_v11.h"
|
||||
|
||||
#define RCAR_QOS_VERSION "rev.0.17"
|
||||
|
||||
#define QOSWT_TIME_BANK0 (20000000U) /* unit:ns */
|
||||
|
||||
#define QOSWT_WTEN_ENABLE (0x1U)
|
||||
|
||||
#define QOSCTRL_REF_ARS_ARBSTOPCYCLE_M3_11 (SL_INIT_SSLOTCLK_M3_11 - 0x5U)
|
||||
|
||||
#define OSWT_WTREF_SLOT0_EN_REQ1_SLOT (3U)
|
||||
#define OSWT_WTREF_SLOT0_EN_REQ2_SLOT (9U)
|
||||
#define QOSWT_WTREF_SLOT0_EN ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
|
||||
#define QOSWT_WTREF_SLOT1_EN ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
|
||||
|
||||
#define QOSWT_WTSET0_REQ_SSLOT0 (5U)
|
||||
#define WT_BASE_SUB_SLOT_NUM0 (12U)
|
||||
#define QOSWT_WTSET0_PERIOD0_M3_11 ((QOSWT_TIME_BANK0/QOSWT_WTSET0_CYCLE_M3_11)-1U)
|
||||
#define QOSWT_WTSET0_SSLOT0 (QOSWT_WTSET0_REQ_SSLOT0 -1U)
|
||||
#define QOSWT_WTSET0_SLOTSLOT0 (WT_BASE_SUB_SLOT_NUM0 -1U)
|
||||
|
||||
#define QOSWT_WTSET1_PERIOD1_M3_11 ((QOSWT_TIME_BANK0/QOSWT_WTSET0_CYCLE_M3_11)-1U)
|
||||
#define QOSWT_WTSET1_SSLOT1 (QOSWT_WTSET0_REQ_SSLOT0 -1U)
|
||||
#define QOSWT_WTSET1_SLOTSLOT1 (WT_BASE_SUB_SLOT_NUM0 -1U)
|
||||
|
||||
#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
|
||||
|
||||
#if RCAR_REF_INT == RCAR_REF_DEFAULT
|
||||
#include "qos_init_m3_v11_mstat195.h"
|
||||
#else
|
||||
#include "qos_init_m3_v11_mstat390.h"
|
||||
#endif
|
||||
|
||||
#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
|
||||
|
||||
#if RCAR_REF_INT == RCAR_REF_DEFAULT
|
||||
#include "qos_init_m3_v11_qoswt195.h"
|
||||
#else
|
||||
#include "qos_init_m3_v11_qoswt390.h"
|
||||
#endif
|
||||
|
||||
#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
|
||||
#endif
|
||||
|
||||
static void dbsc_setting(void)
|
||||
{
|
||||
uint32_t md = 0;
|
||||
|
||||
/* BUFCAM settings */
|
||||
io_write_32(DBSC_DBCAM0CNF1, 0x00043218); /* dbcam0cnf1 */
|
||||
io_write_32(DBSC_DBCAM0CNF2, 0x000000F4); /* dbcam0cnf2 */
|
||||
io_write_32(DBSC_DBCAM0CNF3, 0x00000000); /* dbcam0cnf3 */
|
||||
io_write_32(DBSC_DBSCHCNT0, 0x000F0037); /* dbschcnt0 */
|
||||
io_write_32(DBSC_DBSCHSZ0, 0x00000001); /* dbschsz0 */
|
||||
io_write_32(DBSC_DBSCHRW0, 0x22421111); /* dbschrw0 */
|
||||
|
||||
md = (*((volatile uint32_t *)RST_MODEMR) & 0x000A0000) >> 17;
|
||||
|
||||
switch (md) {
|
||||
case 0x0:
|
||||
/* DDR3200 */
|
||||
io_write_32(DBSC_SCFCTST2, 0x012F1123);
|
||||
break;
|
||||
case 0x1: /* MD19=0,MD17=1 : LPDDR4-3000, 4GByte(1GByte x4) */
|
||||
/* DDR2800 */
|
||||
io_write_32(DBSC_SCFCTST2, 0x012F1123);
|
||||
break;
|
||||
case 0x4: /* MD19=1,MD17=0 : LPDDR4-2400, 4GByte(1GByte x4) */
|
||||
/* DDR2400 */
|
||||
io_write_32(DBSC_SCFCTST2, 0x012F1123);
|
||||
break;
|
||||
default: /* MD19=1,MD17=1 : LPDDR4-1600, 4GByte(1GByte x4) */
|
||||
/* DDR1600 */
|
||||
io_write_32(DBSC_SCFCTST2, 0x012F1123);
|
||||
break;
|
||||
}
|
||||
|
||||
/* QoS Settings */
|
||||
io_write_32(DBSC_DBSCHQOS00, 0x00000F00);
|
||||
io_write_32(DBSC_DBSCHQOS01, 0x00000B00);
|
||||
io_write_32(DBSC_DBSCHQOS02, 0x00000000);
|
||||
io_write_32(DBSC_DBSCHQOS03, 0x00000000);
|
||||
io_write_32(DBSC_DBSCHQOS40, 0x00000300);
|
||||
io_write_32(DBSC_DBSCHQOS41, 0x000002F0);
|
||||
io_write_32(DBSC_DBSCHQOS42, 0x00000200);
|
||||
io_write_32(DBSC_DBSCHQOS43, 0x00000100);
|
||||
io_write_32(DBSC_DBSCHQOS90, 0x00000100);
|
||||
io_write_32(DBSC_DBSCHQOS91, 0x000000F0);
|
||||
io_write_32(DBSC_DBSCHQOS92, 0x000000A0);
|
||||
io_write_32(DBSC_DBSCHQOS93, 0x00000040);
|
||||
io_write_32(DBSC_DBSCHQOS120, 0x00000040);
|
||||
io_write_32(DBSC_DBSCHQOS121, 0x00000030);
|
||||
io_write_32(DBSC_DBSCHQOS122, 0x00000020);
|
||||
io_write_32(DBSC_DBSCHQOS123, 0x00000010);
|
||||
io_write_32(DBSC_DBSCHQOS130, 0x00000100);
|
||||
io_write_32(DBSC_DBSCHQOS131, 0x000000F0);
|
||||
io_write_32(DBSC_DBSCHQOS132, 0x000000A0);
|
||||
io_write_32(DBSC_DBSCHQOS133, 0x00000040);
|
||||
io_write_32(DBSC_DBSCHQOS140, 0x000000C0);
|
||||
io_write_32(DBSC_DBSCHQOS141, 0x000000B0);
|
||||
io_write_32(DBSC_DBSCHQOS142, 0x00000080);
|
||||
io_write_32(DBSC_DBSCHQOS143, 0x00000040);
|
||||
io_write_32(DBSC_DBSCHQOS150, 0x00000040);
|
||||
io_write_32(DBSC_DBSCHQOS151, 0x00000030);
|
||||
io_write_32(DBSC_DBSCHQOS152, 0x00000020);
|
||||
io_write_32(DBSC_DBSCHQOS153, 0x00000010);
|
||||
}
|
||||
|
||||
void qos_init_m3_v11(void)
|
||||
{
|
||||
dbsc_setting();
|
||||
|
||||
/* DRAM Split Address mapping */
|
||||
#if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH
|
||||
#if RCAR_LSI == RCAR_M3
|
||||
#error "Don't set DRAM Split 4ch(M3)"
|
||||
#else
|
||||
ERROR("DRAM Split 4ch not supported.(M3)");
|
||||
panic();
|
||||
#endif
|
||||
#elif (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH) || \
|
||||
(RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO)
|
||||
NOTICE("BL2: DRAM Split is 2ch\n");
|
||||
io_write_32(AXI_ADSPLCR0, 0x00000000U);
|
||||
io_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT
|
||||
| ADSPLCR0_SPLITSEL(0xFFU)
|
||||
| ADSPLCR0_AREA(0x1CU)
|
||||
| ADSPLCR0_SWP);
|
||||
io_write_32(AXI_ADSPLCR2, 0x00001004U);
|
||||
io_write_32(AXI_ADSPLCR3, 0x00000000U);
|
||||
#else
|
||||
NOTICE("BL2: DRAM Split is OFF\n");
|
||||
#endif
|
||||
|
||||
#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
|
||||
#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
|
||||
NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
|
||||
#endif
|
||||
|
||||
#if RCAR_REF_INT == RCAR_REF_DEFAULT
|
||||
NOTICE("BL2: DRAM refresh interval 1.95 usec\n");
|
||||
#else
|
||||
NOTICE("BL2: DRAM refresh interval 3.9 usec\n");
|
||||
#endif
|
||||
|
||||
#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
|
||||
NOTICE("BL2: Periodic Write DQ Training\n");
|
||||
#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
|
||||
|
||||
io_write_32(QOSCTRL_RAS, 0x00000044U);
|
||||
io_write_64(QOSCTRL_DANN, 0x0404020002020201UL);
|
||||
io_write_32(QOSCTRL_DANT, 0x0020100AU);
|
||||
io_write_32(QOSCTRL_INSFC, 0x06330001U);
|
||||
io_write_32(QOSCTRL_RACNT0, 0x02010003U); /* GPU Boost Mode ON */
|
||||
|
||||
io_write_32(QOSCTRL_SL_INIT,
|
||||
SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT |
|
||||
SL_INIT_SSLOTCLK_M3_11);
|
||||
#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
|
||||
io_write_32(QOSCTRL_REF_ARS,
|
||||
((QOSCTRL_REF_ARS_ARBSTOPCYCLE_M3_11 << 16)));
|
||||
#else
|
||||
io_write_32(QOSCTRL_REF_ARS, 0x00330000U);
|
||||
#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
|
||||
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
|
||||
io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
|
||||
io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
|
||||
}
|
||||
for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
|
||||
io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
|
||||
io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
|
||||
}
|
||||
#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
|
||||
for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) {
|
||||
io_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8,
|
||||
qoswt_fix[i]);
|
||||
io_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8,
|
||||
qoswt_fix[i]);
|
||||
}
|
||||
for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) {
|
||||
io_write_64(QOSWT_BE_WTQOS_BANK0 + i * 8, qoswt_be[i]);
|
||||
io_write_64(QOSWT_BE_WTQOS_BANK1 + i * 8, qoswt_be[i]);
|
||||
}
|
||||
#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
|
||||
}
|
||||
|
||||
/* 3DG bus Leaf setting */
|
||||
io_write_32(GPU_ACT_GRD, 0x00001234U);
|
||||
io_write_32(GPU_ACT0, 0x00000000U);
|
||||
io_write_32(GPU_ACT1, 0x00000000U);
|
||||
io_write_32(GPU_ACT2, 0x00000000U);
|
||||
io_write_32(GPU_ACT3, 0x00000000U);
|
||||
|
||||
/* RT bus Leaf setting */
|
||||
io_write_32(RT_ACT0, 0x00000000U);
|
||||
io_write_32(RT_ACT1, 0x00000000U);
|
||||
|
||||
/* CCI bus Leaf setting */
|
||||
io_write_32(CPU_ACT0, 0x00000003U);
|
||||
io_write_32(CPU_ACT1, 0x00000003U);
|
||||
io_write_32(CPU_ACT2, 0x00000003U);
|
||||
io_write_32(CPU_ACT3, 0x00000003U);
|
||||
|
||||
io_write_32(QOSCTRL_RAEN, 0x00000001U);
|
||||
|
||||
#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
|
||||
/* re-write training setting */
|
||||
io_write_32(QOSWT_WTREF,
|
||||
((QOSWT_WTREF_SLOT1_EN << 16) | QOSWT_WTREF_SLOT0_EN));
|
||||
io_write_32(QOSWT_WTSET0,
|
||||
((QOSWT_WTSET0_PERIOD0_M3_11 << 16) |
|
||||
(QOSWT_WTSET0_SSLOT0 << 8) | QOSWT_WTSET0_SLOTSLOT0));
|
||||
io_write_32(QOSWT_WTSET1,
|
||||
((QOSWT_WTSET1_PERIOD1_M3_11 << 16) |
|
||||
(QOSWT_WTSET1_SSLOT1 << 8) | QOSWT_WTSET1_SLOTSLOT1));
|
||||
|
||||
io_write_32(QOSWT_WTEN, QOSWT_WTEN_ENABLE);
|
||||
#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
|
||||
|
||||
io_write_32(QOSCTRL_STATQC, 0x00000001U);
|
||||
#else
|
||||
NOTICE("BL2: QoS is None\n");
|
||||
|
||||
io_write_32(QOSCTRL_RAEN, 0x00000001U);
|
||||
#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
|
||||
}
|
12
drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.h
Normal file
12
drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.h
Normal file
|
@ -0,0 +1,12 @@
|
|||
/*
|
||||
* Copyright (c) 2017, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef QOS_INIT_H_M3_V11__
|
||||
#define QOS_INIT_H_M3_V11__
|
||||
|
||||
void qos_init_m3_v11(void);
|
||||
|
||||
#endif /* QOS_INIT_H_M3_V11__ */
|
225
drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11_mstat195.h
Normal file
225
drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11_mstat195.h
Normal file
|
@ -0,0 +1,225 @@
|
|||
/*
|
||||
* Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
static uint64_t mstat_fix[] = {
|
||||
/* 0x0000, */ 0x0000000000000000UL,
|
||||
/* 0x0008, */ 0x0000000000000000UL,
|
||||
/* 0x0010, */ 0x0000000000000000UL,
|
||||
/* 0x0018, */ 0x0000000000000000UL,
|
||||
/* 0x0020, */ 0x0000000000000000UL,
|
||||
/* 0x0028, */ 0x0000000000000000UL,
|
||||
/* 0x0030, */ 0x001004040000FFFFUL,
|
||||
/* 0x0038, */ 0x001004040000FFFFUL,
|
||||
/* 0x0040, */ 0x001414090000FFFFUL,
|
||||
/* 0x0048, */ 0x0000000000000000UL,
|
||||
/* 0x0050, */ 0x001404010000FFFFUL,
|
||||
/* 0x0058, */ 0x00140C0A0000FFFFUL,
|
||||
/* 0x0060, */ 0x00140C0A0000FFFFUL,
|
||||
/* 0x0068, */ 0x0000000000000000UL,
|
||||
/* 0x0070, */ 0x001404010000FFFFUL,
|
||||
/* 0x0078, */ 0x001004030000FFFFUL,
|
||||
/* 0x0080, */ 0x0000000000000000UL,
|
||||
/* 0x0088, */ 0x001414090000FFFFUL,
|
||||
/* 0x0090, */ 0x001408070000FFFFUL,
|
||||
/* 0x0098, */ 0x0000000000000000UL,
|
||||
/* 0x00a0, */ 0x000C04020000FFFFUL,
|
||||
/* 0x00a8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x00b0, */ 0x000C04010000FFFFUL,
|
||||
/* 0x00b8, */ 0x0000000000000000UL,
|
||||
/* 0x00c0, */ 0x000C04020000FFFFUL,
|
||||
/* 0x00c8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x00d0, */ 0x000C04010000FFFFUL,
|
||||
/* 0x00d8, */ 0x000C08050000FFFFUL,
|
||||
/* 0x00e0, */ 0x000C14120000FFFFUL,
|
||||
/* 0x00e8, */ 0x0000000000000000UL,
|
||||
/* 0x00f0, */ 0x001024090000FFFFUL,
|
||||
/* 0x00f8, */ 0x0000000000000000UL,
|
||||
/* 0x0100, */ 0x0000000000000000UL,
|
||||
/* 0x0108, */ 0x0000000000000000UL,
|
||||
/* 0x0110, */ 0x00100C090000FFFFUL,
|
||||
/* 0x0118, */ 0x0000000000000000UL,
|
||||
/* 0x0120, */ 0x0000000000000000UL,
|
||||
/* 0x0128, */ 0x0000000000000000UL,
|
||||
/* 0x0130, */ 0x0000000000000000UL,
|
||||
/* 0x0138, */ 0x00100C0B0000FFFFUL,
|
||||
/* 0x0140, */ 0x0000000000000000UL,
|
||||
/* 0x0148, */ 0x0000000000000000UL,
|
||||
/* 0x0150, */ 0x0010100D0000FFFFUL,
|
||||
/* 0x0158, */ 0x0000000000000000UL,
|
||||
/* 0x0160, */ 0x00100C0B0000FFFFUL,
|
||||
/* 0x0168, */ 0x0000000000000000UL,
|
||||
/* 0x0170, */ 0x0000000000000000UL,
|
||||
/* 0x0178, */ 0x001008060000FFFFUL,
|
||||
/* 0x0180, */ 0x0000000000000000UL,
|
||||
/* 0x0188, */ 0x0000000000000000UL,
|
||||
/* 0x0190, */ 0x00102C2C0000FFFFUL,
|
||||
/* 0x0198, */ 0x0000000000000000UL,
|
||||
/* 0x01a0, */ 0x00100C0B0000FFFFUL,
|
||||
/* 0x01a8, */ 0x0000000000000000UL,
|
||||
/* 0x01b0, */ 0x0000000000000000UL,
|
||||
/* 0x01b8, */ 0x0000000000000000UL,
|
||||
/* 0x01c0, */ 0x000C04010000FFFFUL,
|
||||
/* 0x01c8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x01d0, */ 0x000C04010000FFFFUL,
|
||||
/* 0x01d8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x01e0, */ 0x0000000000000000UL,
|
||||
/* 0x01e8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x01f0, */ 0x000C04010000FFFFUL,
|
||||
/* 0x01f8, */ 0x0000000000000000UL,
|
||||
/* 0x0200, */ 0x0000000000000000UL,
|
||||
/* 0x0208, */ 0x000C04010000FFFFUL,
|
||||
/* 0x0210, */ 0x000C04010000FFFFUL,
|
||||
/* 0x0218, */ 0x0000000000000000UL,
|
||||
/* 0x0220, */ 0x0000000000000000UL,
|
||||
/* 0x0228, */ 0x0000000000000000UL,
|
||||
/* 0x0230, */ 0x0000000000000000UL,
|
||||
/* 0x0238, */ 0x0000000000000000UL,
|
||||
/* 0x0240, */ 0x0000000000000000UL,
|
||||
/* 0x0248, */ 0x0000000000000000UL,
|
||||
/* 0x0250, */ 0x0000000000000000UL,
|
||||
/* 0x0258, */ 0x0000000000000000UL,
|
||||
/* 0x0260, */ 0x000C08020000FFFFUL,
|
||||
/* 0x0268, */ 0x001408010000FFFFUL,
|
||||
/* 0x0270, */ 0x001404010000FFFFUL,
|
||||
/* 0x0278, */ 0x000C04010000FFFFUL,
|
||||
/* 0x0280, */ 0x0000000000000000UL,
|
||||
/* 0x0288, */ 0x0000000000000000UL,
|
||||
/* 0x0290, */ 0x001408010000FFFFUL,
|
||||
/* 0x0298, */ 0x001404010000FFFFUL,
|
||||
/* 0x02a0, */ 0x000C04010000FFFFUL,
|
||||
/* 0x02a8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x02b0, */ 0x001408010000FFFFUL,
|
||||
/* 0x02b8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x02c0, */ 0x0000000000000000UL,
|
||||
/* 0x02c8, */ 0x0000000000000000UL,
|
||||
/* 0x02d0, */ 0x000C04010000FFFFUL,
|
||||
/* 0x02d8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x02e0, */ 0x001408010000FFFFUL,
|
||||
/* 0x02e8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x02f0, */ 0x0000000000000000UL,
|
||||
/* 0x02f8, */ 0x0000000000000000UL,
|
||||
/* 0x0300, */ 0x0000000000000000UL,
|
||||
/* 0x0308, */ 0x0000000000000000UL,
|
||||
/* 0x0310, */ 0x0000000000000000UL,
|
||||
/* 0x0318, */ 0x0000000000000000UL,
|
||||
/* 0x0320, */ 0x0000000000000000UL,
|
||||
/* 0x0328, */ 0x0000000000000000UL,
|
||||
/* 0x0330, */ 0x0000000000000000UL,
|
||||
/* 0x0338, */ 0x0000000000000000UL,
|
||||
/* 0x0340, */ 0x0000000000000000UL,
|
||||
/* 0x0348, */ 0x0000000000000000UL,
|
||||
/* 0x0350, */ 0x0000000000000000UL,
|
||||
};
|
||||
|
||||
static uint64_t mstat_be[] = {
|
||||
/* 0x0000, */ 0x001200200BDFFC01UL,
|
||||
/* 0x0008, */ 0x001200200BDFFC01UL,
|
||||
/* 0x0010, */ 0x001200200BDFFC01UL,
|
||||
/* 0x0018, */ 0x001200200BDFFC01UL,
|
||||
/* 0x0020, */ 0x0000000000000000UL,
|
||||
/* 0x0028, */ 0x001200100BD03401UL,
|
||||
/* 0x0030, */ 0x0000000000000000UL,
|
||||
/* 0x0038, */ 0x0000000000000000UL,
|
||||
/* 0x0040, */ 0x0000000000000000UL,
|
||||
/* 0x0048, */ 0x0000000000000000UL,
|
||||
/* 0x0050, */ 0x0000000000000000UL,
|
||||
/* 0x0058, */ 0x0000000000000000UL,
|
||||
/* 0x0060, */ 0x0000000000000000UL,
|
||||
/* 0x0068, */ 0x0000000000000000UL,
|
||||
/* 0x0070, */ 0x0000000000000000UL,
|
||||
/* 0x0078, */ 0x0000000000000000UL,
|
||||
/* 0x0080, */ 0x0000000000000000UL,
|
||||
/* 0x0088, */ 0x0000000000000000UL,
|
||||
/* 0x0090, */ 0x0000000000000000UL,
|
||||
/* 0x0098, */ 0x0000000000000000UL,
|
||||
/* 0x00a0, */ 0x0000000000000000UL,
|
||||
/* 0x00a8, */ 0x0000000000000000UL,
|
||||
/* 0x00b0, */ 0x0000000000000000UL,
|
||||
/* 0x00b8, */ 0x0000000000000000UL,
|
||||
/* 0x00c0, */ 0x0000000000000000UL,
|
||||
/* 0x00c8, */ 0x0000000000000000UL,
|
||||
/* 0x00d0, */ 0x0000000000000000UL,
|
||||
/* 0x00d8, */ 0x0000000000000000UL,
|
||||
/* 0x00e0, */ 0x0000000000000000UL,
|
||||
/* 0x00e8, */ 0x0000000000000000UL,
|
||||
/* 0x00f0, */ 0x0000000000000000UL,
|
||||
/* 0x00f8, */ 0x0000000000000000UL,
|
||||
/* 0x0100, */ 0x0000000000000000UL,
|
||||
/* 0x0108, */ 0x0000000000000000UL,
|
||||
/* 0x0110, */ 0x0000000000000000UL,
|
||||
/* 0x0118, */ 0x0000000000000000UL,
|
||||
/* 0x0120, */ 0x0000000000000000UL,
|
||||
/* 0x0128, */ 0x0000000000000000UL,
|
||||
/* 0x0130, */ 0x0000000000000000UL,
|
||||
/* 0x0138, */ 0x0000000000000000UL,
|
||||
/* 0x0140, */ 0x0000000000000000UL,
|
||||
/* 0x0148, */ 0x0000000000000000UL,
|
||||
/* 0x0150, */ 0x0000000000000000UL,
|
||||
/* 0x0158, */ 0x0000000000000000UL,
|
||||
/* 0x0160, */ 0x0000000000000000UL,
|
||||
/* 0x0168, */ 0x0000000000000000UL,
|
||||
/* 0x0170, */ 0x0000000000000000UL,
|
||||
/* 0x0178, */ 0x0000000000000000UL,
|
||||
/* 0x0180, */ 0x0000000000000000UL,
|
||||
/* 0x0188, */ 0x0000000000000000UL,
|
||||
/* 0x0190, */ 0x0000000000000000UL,
|
||||
/* 0x0198, */ 0x0000000000000000UL,
|
||||
/* 0x01a0, */ 0x0000000000000000UL,
|
||||
/* 0x01a8, */ 0x0000000000000000UL,
|
||||
/* 0x01b0, */ 0x0000000000000000UL,
|
||||
/* 0x01b8, */ 0x0000000000000000UL,
|
||||
/* 0x01c0, */ 0x002100600BDFFC01UL,
|
||||
/* 0x01c8, */ 0x002100600BDFFC01UL,
|
||||
/* 0x01d0, */ 0x002100600BDFFC01UL,
|
||||
/* 0x01d8, */ 0x002100600BDFFC01UL,
|
||||
/* 0x01e0, */ 0x0000000000000000UL,
|
||||
/* 0x01e8, */ 0x0000000000000000UL,
|
||||
/* 0x01f0, */ 0x002100200BDFFC01UL,
|
||||
/* 0x01f8, */ 0x0000000000000000UL,
|
||||
/* 0x0200, */ 0x0000000000000000UL,
|
||||
/* 0x0208, */ 0x0000000000000000UL,
|
||||
/* 0x0210, */ 0x002100200BDFFC01UL,
|
||||
/* 0x0218, */ 0x001100200BDFFC01UL,
|
||||
/* 0x0220, */ 0x001100200BDFFC01UL,
|
||||
/* 0x0228, */ 0x0000000000000000UL,
|
||||
/* 0x0230, */ 0x001100200BDFFC01UL,
|
||||
/* 0x0238, */ 0x001100200BDFFC01UL,
|
||||
/* 0x0240, */ 0x001200200BDFFC01UL,
|
||||
/* 0x0248, */ 0x001100200BDFFC01UL,
|
||||
/* 0x0250, */ 0x001200200BDFFC01UL,
|
||||
/* 0x0258, */ 0x001100200BDFFC01UL,
|
||||
/* 0x0260, */ 0x0000000000000000UL,
|
||||
/* 0x0268, */ 0x0000000000000000UL,
|
||||
/* 0x0270, */ 0x0000000000000000UL,
|
||||
/* 0x0278, */ 0x0000000000000000UL,
|
||||
/* 0x0280, */ 0x0000000000000000UL,
|
||||
/* 0x0288, */ 0x0000000000000000UL,
|
||||
/* 0x0290, */ 0x0000000000000000UL,
|
||||
/* 0x0298, */ 0x0000000000000000UL,
|
||||
/* 0x02a0, */ 0x0000000000000000UL,
|
||||
/* 0x02a8, */ 0x0000000000000000UL,
|
||||
/* 0x02b0, */ 0x0000000000000000UL,
|
||||
/* 0x02b8, */ 0x0000000000000000UL,
|
||||
/* 0x02c0, */ 0x0000000000000000UL,
|
||||
/* 0x02c8, */ 0x0000000000000000UL,
|
||||
/* 0x02d0, */ 0x0000000000000000UL,
|
||||
/* 0x02d8, */ 0x0000000000000000UL,
|
||||
/* 0x02e0, */ 0x0000000000000000UL,
|
||||
/* 0x02e8, */ 0x0000000000000000UL,
|
||||
/* 0x02f0, */ 0x001100400BDFFC01UL,
|
||||
/* 0x02f8, */ 0x001100600BDFFC01UL,
|
||||
/* 0x0300, */ 0x0000000000000000UL,
|
||||
/* 0x0308, */ 0x001100400BDFFC01UL,
|
||||
/* 0x0310, */ 0x001100600BDFFC01UL,
|
||||
/* 0x0318, */ 0x001200100BD03401UL,
|
||||
/* 0x0320, */ 0x0000000000000000UL,
|
||||
/* 0x0328, */ 0x0000000000000000UL,
|
||||
/* 0x0330, */ 0x0000000000000000UL,
|
||||
/* 0x0338, */ 0x0000000000000000UL,
|
||||
/* 0x0340, */ 0x0000000000000000UL,
|
||||
/* 0x0348, */ 0x0000000000000000UL,
|
||||
/* 0x0350, */ 0x0000000000000000UL,
|
||||
};
|
225
drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11_mstat390.h
Normal file
225
drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11_mstat390.h
Normal file
|
@ -0,0 +1,225 @@
|
|||
/*
|
||||
* Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
static uint64_t mstat_fix[] = {
|
||||
/* 0x0000, */ 0x0000000000000000UL,
|
||||
/* 0x0008, */ 0x0000000000000000UL,
|
||||
/* 0x0010, */ 0x0000000000000000UL,
|
||||
/* 0x0018, */ 0x0000000000000000UL,
|
||||
/* 0x0020, */ 0x0000000000000000UL,
|
||||
/* 0x0028, */ 0x0000000000000000UL,
|
||||
/* 0x0030, */ 0x001008070000FFFFUL,
|
||||
/* 0x0038, */ 0x001008070000FFFFUL,
|
||||
/* 0x0040, */ 0x001424120000FFFFUL,
|
||||
/* 0x0048, */ 0x0000000000000000UL,
|
||||
/* 0x0050, */ 0x001404010000FFFFUL,
|
||||
/* 0x0058, */ 0x001414130000FFFFUL,
|
||||
/* 0x0060, */ 0x001414130000FFFFUL,
|
||||
/* 0x0068, */ 0x0000000000000000UL,
|
||||
/* 0x0070, */ 0x001404010000FFFFUL,
|
||||
/* 0x0078, */ 0x001008050000FFFFUL,
|
||||
/* 0x0080, */ 0x0000000000000000UL,
|
||||
/* 0x0088, */ 0x001424120000FFFFUL,
|
||||
/* 0x0090, */ 0x0014100D0000FFFFUL,
|
||||
/* 0x0098, */ 0x0000000000000000UL,
|
||||
/* 0x00a0, */ 0x000C08040000FFFFUL,
|
||||
/* 0x00a8, */ 0x000C04020000FFFFUL,
|
||||
/* 0x00b0, */ 0x000C04020000FFFFUL,
|
||||
/* 0x00b8, */ 0x0000000000000000UL,
|
||||
/* 0x00c0, */ 0x000C08040000FFFFUL,
|
||||
/* 0x00c8, */ 0x000C04020000FFFFUL,
|
||||
/* 0x00d0, */ 0x000C04020000FFFFUL,
|
||||
/* 0x00d8, */ 0x000C0C0A0000FFFFUL,
|
||||
/* 0x00e0, */ 0x000C24230000FFFFUL,
|
||||
/* 0x00e8, */ 0x0000000000000000UL,
|
||||
/* 0x00f0, */ 0x001044110000FFFFUL,
|
||||
/* 0x00f8, */ 0x0000000000000000UL,
|
||||
/* 0x0100, */ 0x0000000000000000UL,
|
||||
/* 0x0108, */ 0x0000000000000000UL,
|
||||
/* 0x0110, */ 0x001014110000FFFFUL,
|
||||
/* 0x0118, */ 0x0000000000000000UL,
|
||||
/* 0x0120, */ 0x0000000000000000UL,
|
||||
/* 0x0128, */ 0x0000000000000000UL,
|
||||
/* 0x0130, */ 0x0000000000000000UL,
|
||||
/* 0x0138, */ 0x001018150000FFFFUL,
|
||||
/* 0x0140, */ 0x0000000000000000UL,
|
||||
/* 0x0148, */ 0x0000000000000000UL,
|
||||
/* 0x0150, */ 0x00101C190000FFFFUL,
|
||||
/* 0x0158, */ 0x0000000000000000UL,
|
||||
/* 0x0160, */ 0x001018150000FFFFUL,
|
||||
/* 0x0168, */ 0x0000000000000000UL,
|
||||
/* 0x0170, */ 0x0000000000000000UL,
|
||||
/* 0x0178, */ 0x00100C0B0000FFFFUL,
|
||||
/* 0x0180, */ 0x0000000000000000UL,
|
||||
/* 0x0188, */ 0x0000000000000000UL,
|
||||
/* 0x0190, */ 0x001058570000FFFFUL,
|
||||
/* 0x0198, */ 0x0000000000000000UL,
|
||||
/* 0x01a0, */ 0x001018150000FFFFUL,
|
||||
/* 0x01a8, */ 0x0000000000000000UL,
|
||||
/* 0x01b0, */ 0x0000000000000000UL,
|
||||
/* 0x01b8, */ 0x0000000000000000UL,
|
||||
/* 0x01c0, */ 0x000C04010000FFFFUL,
|
||||
/* 0x01c8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x01d0, */ 0x000C04010000FFFFUL,
|
||||
/* 0x01d8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x01e0, */ 0x0000000000000000UL,
|
||||
/* 0x01e8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x01f0, */ 0x000C04010000FFFFUL,
|
||||
/* 0x01f8, */ 0x0000000000000000UL,
|
||||
/* 0x0200, */ 0x0000000000000000UL,
|
||||
/* 0x0208, */ 0x000C04010000FFFFUL,
|
||||
/* 0x0210, */ 0x000C04010000FFFFUL,
|
||||
/* 0x0218, */ 0x0000000000000000UL,
|
||||
/* 0x0220, */ 0x0000000000000000UL,
|
||||
/* 0x0228, */ 0x0000000000000000UL,
|
||||
/* 0x0230, */ 0x0000000000000000UL,
|
||||
/* 0x0238, */ 0x0000000000000000UL,
|
||||
/* 0x0240, */ 0x0000000000000000UL,
|
||||
/* 0x0248, */ 0x0000000000000000UL,
|
||||
/* 0x0250, */ 0x0000000000000000UL,
|
||||
/* 0x0258, */ 0x0000000000000000UL,
|
||||
/* 0x0260, */ 0x000C0C030000FFFFUL,
|
||||
/* 0x0268, */ 0x001410010000FFFFUL,
|
||||
/* 0x0270, */ 0x001404010000FFFFUL,
|
||||
/* 0x0278, */ 0x000C08020000FFFFUL,
|
||||
/* 0x0280, */ 0x0000000000000000UL,
|
||||
/* 0x0288, */ 0x0000000000000000UL,
|
||||
/* 0x0290, */ 0x001410010000FFFFUL,
|
||||
/* 0x0298, */ 0x001404010000FFFFUL,
|
||||
/* 0x02a0, */ 0x000C04010000FFFFUL,
|
||||
/* 0x02a8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x02b0, */ 0x00140C010000FFFFUL,
|
||||
/* 0x02b8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x02c0, */ 0x0000000000000000UL,
|
||||
/* 0x02c8, */ 0x0000000000000000UL,
|
||||
/* 0x02d0, */ 0x000C04010000FFFFUL,
|
||||
/* 0x02d8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x02e0, */ 0x00140C010000FFFFUL,
|
||||
/* 0x02e8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x02f0, */ 0x0000000000000000UL,
|
||||
/* 0x02f8, */ 0x0000000000000000UL,
|
||||
/* 0x0300, */ 0x0000000000000000UL,
|
||||
/* 0x0308, */ 0x0000000000000000UL,
|
||||
/* 0x0310, */ 0x0000000000000000UL,
|
||||
/* 0x0318, */ 0x0000000000000000UL,
|
||||
/* 0x0320, */ 0x0000000000000000UL,
|
||||
/* 0x0328, */ 0x0000000000000000UL,
|
||||
/* 0x0330, */ 0x0000000000000000UL,
|
||||
/* 0x0338, */ 0x0000000000000000UL,
|
||||
/* 0x0340, */ 0x0000000000000000UL,
|
||||
/* 0x0348, */ 0x0000000000000000UL,
|
||||
/* 0x0350, */ 0x0000000000000000UL,
|
||||
};
|
||||
|
||||
static uint64_t mstat_be[] = {
|
||||
/* 0x0000, */ 0x0012003005EFFC01UL,
|
||||
/* 0x0008, */ 0x0012003005EFFC01UL,
|
||||
/* 0x0010, */ 0x0012003005EFFC01UL,
|
||||
/* 0x0018, */ 0x0012003005EFFC01UL,
|
||||
/* 0x0020, */ 0x0000000000000000UL,
|
||||
/* 0x0028, */ 0x0012001005E03401UL,
|
||||
/* 0x0030, */ 0x0000000000000000UL,
|
||||
/* 0x0038, */ 0x0000000000000000UL,
|
||||
/* 0x0040, */ 0x0000000000000000UL,
|
||||
/* 0x0048, */ 0x0000000000000000UL,
|
||||
/* 0x0050, */ 0x0000000000000000UL,
|
||||
/* 0x0058, */ 0x0000000000000000UL,
|
||||
/* 0x0060, */ 0x0000000000000000UL,
|
||||
/* 0x0068, */ 0x0000000000000000UL,
|
||||
/* 0x0070, */ 0x0000000000000000UL,
|
||||
/* 0x0078, */ 0x0000000000000000UL,
|
||||
/* 0x0080, */ 0x0000000000000000UL,
|
||||
/* 0x0088, */ 0x0000000000000000UL,
|
||||
/* 0x0090, */ 0x0000000000000000UL,
|
||||
/* 0x0098, */ 0x0000000000000000UL,
|
||||
/* 0x00a0, */ 0x0000000000000000UL,
|
||||
/* 0x00a8, */ 0x0000000000000000UL,
|
||||
/* 0x00b0, */ 0x0000000000000000UL,
|
||||
/* 0x00b8, */ 0x0000000000000000UL,
|
||||
/* 0x00c0, */ 0x0000000000000000UL,
|
||||
/* 0x00c8, */ 0x0000000000000000UL,
|
||||
/* 0x00d0, */ 0x0000000000000000UL,
|
||||
/* 0x00d8, */ 0x0000000000000000UL,
|
||||
/* 0x00e0, */ 0x0000000000000000UL,
|
||||
/* 0x00e8, */ 0x0000000000000000UL,
|
||||
/* 0x00f0, */ 0x0000000000000000UL,
|
||||
/* 0x00f8, */ 0x0000000000000000UL,
|
||||
/* 0x0100, */ 0x0000000000000000UL,
|
||||
/* 0x0108, */ 0x0000000000000000UL,
|
||||
/* 0x0110, */ 0x0000000000000000UL,
|
||||
/* 0x0118, */ 0x0000000000000000UL,
|
||||
/* 0x0120, */ 0x0000000000000000UL,
|
||||
/* 0x0128, */ 0x0000000000000000UL,
|
||||
/* 0x0130, */ 0x0000000000000000UL,
|
||||
/* 0x0138, */ 0x0000000000000000UL,
|
||||
/* 0x0140, */ 0x0000000000000000UL,
|
||||
/* 0x0148, */ 0x0000000000000000UL,
|
||||
/* 0x0150, */ 0x0000000000000000UL,
|
||||
/* 0x0158, */ 0x0000000000000000UL,
|
||||
/* 0x0160, */ 0x0000000000000000UL,
|
||||
/* 0x0168, */ 0x0000000000000000UL,
|
||||
/* 0x0170, */ 0x0000000000000000UL,
|
||||
/* 0x0178, */ 0x0000000000000000UL,
|
||||
/* 0x0180, */ 0x0000000000000000UL,
|
||||
/* 0x0188, */ 0x0000000000000000UL,
|
||||
/* 0x0190, */ 0x0000000000000000UL,
|
||||
/* 0x0198, */ 0x0000000000000000UL,
|
||||
/* 0x01a0, */ 0x0000000000000000UL,
|
||||
/* 0x01a8, */ 0x0000000000000000UL,
|
||||
/* 0x01b0, */ 0x0000000000000000UL,
|
||||
/* 0x01b8, */ 0x0000000000000000UL,
|
||||
/* 0x01c0, */ 0x002100B005EFFC01UL,
|
||||
/* 0x01c8, */ 0x002100B005EFFC01UL,
|
||||
/* 0x01d0, */ 0x002100B005EFFC01UL,
|
||||
/* 0x01d8, */ 0x002100B005EFFC01UL,
|
||||
/* 0x01e0, */ 0x0000000000000000UL,
|
||||
/* 0x01e8, */ 0x0000000000000000UL,
|
||||
/* 0x01f0, */ 0x0021003005EFFC01UL,
|
||||
/* 0x01f8, */ 0x0000000000000000UL,
|
||||
/* 0x0200, */ 0x0000000000000000UL,
|
||||
/* 0x0208, */ 0x0000000000000000UL,
|
||||
/* 0x0210, */ 0x0021003005EFFC01UL,
|
||||
/* 0x0218, */ 0x0011003005EFFC01UL,
|
||||
/* 0x0220, */ 0x0011003005EFFC01UL,
|
||||
/* 0x0228, */ 0x0000000000000000UL,
|
||||
/* 0x0230, */ 0x0011003005EFFC01UL,
|
||||
/* 0x0238, */ 0x0011003005EFFC01UL,
|
||||
/* 0x0240, */ 0x0012003005EFFC01UL,
|
||||
/* 0x0248, */ 0x0011003005EFFC01UL,
|
||||
/* 0x0250, */ 0x0012003005EFFC01UL,
|
||||
/* 0x0258, */ 0x0011003005EFFC01UL,
|
||||
/* 0x0260, */ 0x0000000000000000UL,
|
||||
/* 0x0268, */ 0x0000000000000000UL,
|
||||
/* 0x0270, */ 0x0000000000000000UL,
|
||||
/* 0x0278, */ 0x0000000000000000UL,
|
||||
/* 0x0280, */ 0x0000000000000000UL,
|
||||
/* 0x0288, */ 0x0000000000000000UL,
|
||||
/* 0x0290, */ 0x0000000000000000UL,
|
||||
/* 0x0298, */ 0x0000000000000000UL,
|
||||
/* 0x02a0, */ 0x0000000000000000UL,
|
||||
/* 0x02a8, */ 0x0000000000000000UL,
|
||||
/* 0x02b0, */ 0x0000000000000000UL,
|
||||
/* 0x02b8, */ 0x0000000000000000UL,
|
||||
/* 0x02c0, */ 0x0000000000000000UL,
|
||||
/* 0x02c8, */ 0x0000000000000000UL,
|
||||
/* 0x02d0, */ 0x0000000000000000UL,
|
||||
/* 0x02d8, */ 0x0000000000000000UL,
|
||||
/* 0x02e0, */ 0x0000000000000000UL,
|
||||
/* 0x02e8, */ 0x0000000000000000UL,
|
||||
/* 0x02f0, */ 0x0011007005EFFC01UL,
|
||||
/* 0x02f8, */ 0x001100B005EFFC01UL,
|
||||
/* 0x0300, */ 0x0000000000000000UL,
|
||||
/* 0x0308, */ 0x0011007005EFFC01UL,
|
||||
/* 0x0310, */ 0x001100B005EFFC01UL,
|
||||
/* 0x0318, */ 0x0012001005E03401UL,
|
||||
/* 0x0320, */ 0x0000000000000000UL,
|
||||
/* 0x0328, */ 0x0000000000000000UL,
|
||||
/* 0x0330, */ 0x0000000000000000UL,
|
||||
/* 0x0338, */ 0x0000000000000000UL,
|
||||
/* 0x0340, */ 0x0000000000000000UL,
|
||||
/* 0x0348, */ 0x0000000000000000UL,
|
||||
/* 0x0350, */ 0x0000000000000000UL,
|
||||
};
|
225
drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11_qoswt195.h
Normal file
225
drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11_qoswt195.h
Normal file
|
@ -0,0 +1,225 @@
|
|||
/*
|
||||
* Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
static uint64_t qoswt_fix[] = {
|
||||
/* 0x0000, */ 0x0000000000000000UL,
|
||||
/* 0x0008, */ 0x0000000000000000UL,
|
||||
/* 0x0010, */ 0x0000000000000000UL,
|
||||
/* 0x0018, */ 0x0000000000000000UL,
|
||||
/* 0x0020, */ 0x0000000000000000UL,
|
||||
/* 0x0028, */ 0x0000000000000000UL,
|
||||
/* 0x0030, */ 0x001004040000C010UL,
|
||||
/* 0x0038, */ 0x001004040000C010UL,
|
||||
/* 0x0040, */ 0x001414090000FFF0UL,
|
||||
/* 0x0048, */ 0x0000000000000000UL,
|
||||
/* 0x0050, */ 0x0000000000000000UL,
|
||||
/* 0x0058, */ 0x00140C0A0000C010UL,
|
||||
/* 0x0060, */ 0x00140C0A0000C010UL,
|
||||
/* 0x0068, */ 0x0000000000000000UL,
|
||||
/* 0x0070, */ 0x0000000000000000UL,
|
||||
/* 0x0078, */ 0x001004030000C010UL,
|
||||
/* 0x0080, */ 0x0000000000000000UL,
|
||||
/* 0x0088, */ 0x001414090000FFF0UL,
|
||||
/* 0x0090, */ 0x001408070000C010UL,
|
||||
/* 0x0098, */ 0x0000000000000000UL,
|
||||
/* 0x00a0, */ 0x0000000000000000UL,
|
||||
/* 0x00a8, */ 0x0000000000000000UL,
|
||||
/* 0x00b0, */ 0x0000000000000000UL,
|
||||
/* 0x00b8, */ 0x0000000000000000UL,
|
||||
/* 0x00c0, */ 0x0000000000000000UL,
|
||||
/* 0x00c8, */ 0x0000000000000000UL,
|
||||
/* 0x00d0, */ 0x0000000000000000UL,
|
||||
/* 0x00d8, */ 0x0000000000000000UL,
|
||||
/* 0x00e0, */ 0x0000000000000000UL,
|
||||
/* 0x00e8, */ 0x0000000000000000UL,
|
||||
/* 0x00f0, */ 0x0000000000000000UL,
|
||||
/* 0x00f8, */ 0x0000000000000000UL,
|
||||
/* 0x0100, */ 0x0000000000000000UL,
|
||||
/* 0x0108, */ 0x0000000000000000UL,
|
||||
/* 0x0110, */ 0x0000000000000000UL,
|
||||
/* 0x0118, */ 0x0000000000000000UL,
|
||||
/* 0x0120, */ 0x0000000000000000UL,
|
||||
/* 0x0128, */ 0x0000000000000000UL,
|
||||
/* 0x0130, */ 0x0000000000000000UL,
|
||||
/* 0x0138, */ 0x0000000000000000UL,
|
||||
/* 0x0140, */ 0x0000000000000000UL,
|
||||
/* 0x0148, */ 0x0000000000000000UL,
|
||||
/* 0x0150, */ 0x0000000000000000UL,
|
||||
/* 0x0158, */ 0x0000000000000000UL,
|
||||
/* 0x0160, */ 0x0000000000000000UL,
|
||||
/* 0x0168, */ 0x0000000000000000UL,
|
||||
/* 0x0170, */ 0x0000000000000000UL,
|
||||
/* 0x0178, */ 0x0000000000000000UL,
|
||||
/* 0x0180, */ 0x0000000000000000UL,
|
||||
/* 0x0188, */ 0x0000000000000000UL,
|
||||
/* 0x0190, */ 0x0000000000000000UL,
|
||||
/* 0x0198, */ 0x0000000000000000UL,
|
||||
/* 0x01a0, */ 0x0000000000000000UL,
|
||||
/* 0x01a8, */ 0x0000000000000000UL,
|
||||
/* 0x01b0, */ 0x0000000000000000UL,
|
||||
/* 0x01b8, */ 0x0000000000000000UL,
|
||||
/* 0x01c0, */ 0x0000000000000000UL,
|
||||
/* 0x01c8, */ 0x0000000000000000UL,
|
||||
/* 0x01d0, */ 0x0000000000000000UL,
|
||||
/* 0x01d8, */ 0x0000000000000000UL,
|
||||
/* 0x01e0, */ 0x0000000000000000UL,
|
||||
/* 0x01e8, */ 0x0000000000000000UL,
|
||||
/* 0x01f0, */ 0x0000000000000000UL,
|
||||
/* 0x01f8, */ 0x0000000000000000UL,
|
||||
/* 0x0200, */ 0x0000000000000000UL,
|
||||
/* 0x0208, */ 0x0000000000000000UL,
|
||||
/* 0x0210, */ 0x0000000000000000UL,
|
||||
/* 0x0218, */ 0x0000000000000000UL,
|
||||
/* 0x0220, */ 0x0000000000000000UL,
|
||||
/* 0x0228, */ 0x0000000000000000UL,
|
||||
/* 0x0230, */ 0x0000000000000000UL,
|
||||
/* 0x0238, */ 0x0000000000000000UL,
|
||||
/* 0x0240, */ 0x0000000000000000UL,
|
||||
/* 0x0248, */ 0x0000000000000000UL,
|
||||
/* 0x0250, */ 0x0000000000000000UL,
|
||||
/* 0x0258, */ 0x0000000000000000UL,
|
||||
/* 0x0260, */ 0x000C08020000FFF0UL,
|
||||
/* 0x0268, */ 0x001408010000FFF0UL,
|
||||
/* 0x0270, */ 0x001404010000FFF0UL,
|
||||
/* 0x0278, */ 0x000C04010000FFF0UL,
|
||||
/* 0x0280, */ 0x0000000000000000UL,
|
||||
/* 0x0288, */ 0x0000000000000000UL,
|
||||
/* 0x0290, */ 0x001408010000FFF0UL,
|
||||
/* 0x0298, */ 0x001404010000FFF0UL,
|
||||
/* 0x02a0, */ 0x0000000000000000UL,
|
||||
/* 0x02a8, */ 0x0000000000000000UL,
|
||||
/* 0x02b0, */ 0x0000000000000000UL,
|
||||
/* 0x02b8, */ 0x0000000000000000UL,
|
||||
/* 0x02c0, */ 0x0000000000000000UL,
|
||||
/* 0x02c8, */ 0x0000000000000000UL,
|
||||
/* 0x02d0, */ 0x0000000000000000UL,
|
||||
/* 0x02d8, */ 0x0000000000000000UL,
|
||||
/* 0x02e0, */ 0x0000000000000000UL,
|
||||
/* 0x02e8, */ 0x0000000000000000UL,
|
||||
/* 0x02f0, */ 0x0000000000000000UL,
|
||||
/* 0x02f8, */ 0x0000000000000000UL,
|
||||
/* 0x0300, */ 0x0000000000000000UL,
|
||||
/* 0x0308, */ 0x0000000000000000UL,
|
||||
/* 0x0310, */ 0x0000000000000000UL,
|
||||
/* 0x0318, */ 0x0000000000000000UL,
|
||||
/* 0x0320, */ 0x0000000000000000UL,
|
||||
/* 0x0328, */ 0x0000000000000000UL,
|
||||
/* 0x0330, */ 0x0000000000000000UL,
|
||||
/* 0x0338, */ 0x0000000000000000UL,
|
||||
/* 0x0340, */ 0x0000000000000000UL,
|
||||
/* 0x0348, */ 0x0000000000000000UL,
|
||||
/* 0x0350, */ 0x0000000000000000UL,
|
||||
};
|
||||
|
||||
static uint64_t qoswt_be[] = {
|
||||
/* 0x0000, */ 0x0000000000000000UL,
|
||||
/* 0x0008, */ 0x0000000000000000UL,
|
||||
/* 0x0010, */ 0x0000000000000000UL,
|
||||
/* 0x0018, */ 0x0000000000000000UL,
|
||||
/* 0x0020, */ 0x0000000000000000UL,
|
||||
/* 0x0028, */ 0x0000000000000000UL,
|
||||
/* 0x0030, */ 0x0000000000000000UL,
|
||||
/* 0x0038, */ 0x0000000000000000UL,
|
||||
/* 0x0040, */ 0x0000000000000000UL,
|
||||
/* 0x0048, */ 0x0000000000000000UL,
|
||||
/* 0x0050, */ 0x0000000000000000UL,
|
||||
/* 0x0058, */ 0x0000000000000000UL,
|
||||
/* 0x0060, */ 0x0000000000000000UL,
|
||||
/* 0x0068, */ 0x0000000000000000UL,
|
||||
/* 0x0070, */ 0x0000000000000000UL,
|
||||
/* 0x0078, */ 0x0000000000000000UL,
|
||||
/* 0x0080, */ 0x0000000000000000UL,
|
||||
/* 0x0088, */ 0x0000000000000000UL,
|
||||
/* 0x0090, */ 0x0000000000000000UL,
|
||||
/* 0x0098, */ 0x0000000000000000UL,
|
||||
/* 0x00a0, */ 0x0000000000000000UL,
|
||||
/* 0x00a8, */ 0x0000000000000000UL,
|
||||
/* 0x00b0, */ 0x0000000000000000UL,
|
||||
/* 0x00b8, */ 0x0000000000000000UL,
|
||||
/* 0x00c0, */ 0x0000000000000000UL,
|
||||
/* 0x00c8, */ 0x0000000000000000UL,
|
||||
/* 0x00d0, */ 0x0000000000000000UL,
|
||||
/* 0x00d8, */ 0x0000000000000000UL,
|
||||
/* 0x00e0, */ 0x0000000000000000UL,
|
||||
/* 0x00e8, */ 0x0000000000000000UL,
|
||||
/* 0x00f0, */ 0x0000000000000000UL,
|
||||
/* 0x00f8, */ 0x0000000000000000UL,
|
||||
/* 0x0100, */ 0x0000000000000000UL,
|
||||
/* 0x0108, */ 0x0000000000000000UL,
|
||||
/* 0x0110, */ 0x0000000000000000UL,
|
||||
/* 0x0118, */ 0x0000000000000000UL,
|
||||
/* 0x0120, */ 0x0000000000000000UL,
|
||||
/* 0x0128, */ 0x0000000000000000UL,
|
||||
/* 0x0130, */ 0x0000000000000000UL,
|
||||
/* 0x0138, */ 0x0000000000000000UL,
|
||||
/* 0x0140, */ 0x0000000000000000UL,
|
||||
/* 0x0148, */ 0x0000000000000000UL,
|
||||
/* 0x0150, */ 0x0000000000000000UL,
|
||||
/* 0x0158, */ 0x0000000000000000UL,
|
||||
/* 0x0160, */ 0x0000000000000000UL,
|
||||
/* 0x0168, */ 0x0000000000000000UL,
|
||||
/* 0x0170, */ 0x0000000000000000UL,
|
||||
/* 0x0178, */ 0x0000000000000000UL,
|
||||
/* 0x0180, */ 0x0000000000000000UL,
|
||||
/* 0x0188, */ 0x0000000000000000UL,
|
||||
/* 0x0190, */ 0x0000000000000000UL,
|
||||
/* 0x0198, */ 0x0000000000000000UL,
|
||||
/* 0x01a0, */ 0x0000000000000000UL,
|
||||
/* 0x01a8, */ 0x0000000000000000UL,
|
||||
/* 0x01b0, */ 0x0000000000000000UL,
|
||||
/* 0x01b8, */ 0x0000000000000000UL,
|
||||
/* 0x01c0, */ 0x0000000000000000UL,
|
||||
/* 0x01c8, */ 0x0000000000000000UL,
|
||||
/* 0x01d0, */ 0x0000000000000000UL,
|
||||
/* 0x01d8, */ 0x0000000000000000UL,
|
||||
/* 0x01e0, */ 0x0000000000000000UL,
|
||||
/* 0x01e8, */ 0x0000000000000000UL,
|
||||
/* 0x01f0, */ 0x0000000000000000UL,
|
||||
/* 0x01f8, */ 0x0000000000000000UL,
|
||||
/* 0x0200, */ 0x0000000000000000UL,
|
||||
/* 0x0208, */ 0x0000000000000000UL,
|
||||
/* 0x0210, */ 0x0000000000000000UL,
|
||||
/* 0x0218, */ 0x0000000000000000UL,
|
||||
/* 0x0220, */ 0x0000000000000000UL,
|
||||
/* 0x0228, */ 0x0000000000000000UL,
|
||||
/* 0x0230, */ 0x0000000000000000UL,
|
||||
/* 0x0238, */ 0x0000000000000000UL,
|
||||
/* 0x0240, */ 0x0000000000000000UL,
|
||||
/* 0x0248, */ 0x0000000000000000UL,
|
||||
/* 0x0250, */ 0x0000000000000000UL,
|
||||
/* 0x0258, */ 0x0000000000000000UL,
|
||||
/* 0x0260, */ 0x0000000000000000UL,
|
||||
/* 0x0268, */ 0x0000000000000000UL,
|
||||
/* 0x0270, */ 0x0000000000000000UL,
|
||||
/* 0x0278, */ 0x0000000000000000UL,
|
||||
/* 0x0280, */ 0x0000000000000000UL,
|
||||
/* 0x0288, */ 0x0000000000000000UL,
|
||||
/* 0x0290, */ 0x0000000000000000UL,
|
||||
/* 0x0298, */ 0x0000000000000000UL,
|
||||
/* 0x02a0, */ 0x0000000000000000UL,
|
||||
/* 0x02a8, */ 0x0000000000000000UL,
|
||||
/* 0x02b0, */ 0x0000000000000000UL,
|
||||
/* 0x02b8, */ 0x0000000000000000UL,
|
||||
/* 0x02c0, */ 0x0000000000000000UL,
|
||||
/* 0x02c8, */ 0x0000000000000000UL,
|
||||
/* 0x02d0, */ 0x0000000000000000UL,
|
||||
/* 0x02d8, */ 0x0000000000000000UL,
|
||||
/* 0x02e0, */ 0x0000000000000000UL,
|
||||
/* 0x02e8, */ 0x0000000000000000UL,
|
||||
/* 0x02f0, */ 0x0000000000000000UL,
|
||||
/* 0x02f8, */ 0x0000000000000000UL,
|
||||
/* 0x0300, */ 0x0000000000000000UL,
|
||||
/* 0x0308, */ 0x0000000000000000UL,
|
||||
/* 0x0310, */ 0x0000000000000000UL,
|
||||
/* 0x0318, */ 0x0000000000000000UL,
|
||||
/* 0x0320, */ 0x0000000000000000UL,
|
||||
/* 0x0328, */ 0x0000000000000000UL,
|
||||
/* 0x0330, */ 0x0000000000000000UL,
|
||||
/* 0x0338, */ 0x0000000000000000UL,
|
||||
/* 0x0340, */ 0x0000000000000000UL,
|
||||
/* 0x0348, */ 0x0000000000000000UL,
|
||||
/* 0x0350, */ 0x0000000000000000UL,
|
||||
};
|
225
drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11_qoswt390.h
Normal file
225
drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11_qoswt390.h
Normal file
|
@ -0,0 +1,225 @@
|
|||
/*
|
||||
* Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
static uint64_t qoswt_fix[] = {
|
||||
/* 0x0000, */ 0x0000000000000000UL,
|
||||
/* 0x0008, */ 0x0000000000000000UL,
|
||||
/* 0x0010, */ 0x0000000000000000UL,
|
||||
/* 0x0018, */ 0x0000000000000000UL,
|
||||
/* 0x0020, */ 0x0000000000000000UL,
|
||||
/* 0x0028, */ 0x0000000000000000UL,
|
||||
/* 0x0030, */ 0x001008070000C010UL,
|
||||
/* 0x0038, */ 0x001008070000C010UL,
|
||||
/* 0x0040, */ 0x001424120000FFF0UL,
|
||||
/* 0x0048, */ 0x0000000000000000UL,
|
||||
/* 0x0050, */ 0x0000000000000000UL,
|
||||
/* 0x0058, */ 0x001414130000C010UL,
|
||||
/* 0x0060, */ 0x001414130000C010UL,
|
||||
/* 0x0068, */ 0x0000000000000000UL,
|
||||
/* 0x0070, */ 0x0000000000000000UL,
|
||||
/* 0x0078, */ 0x001008050000C010UL,
|
||||
/* 0x0080, */ 0x0000000000000000UL,
|
||||
/* 0x0088, */ 0x001424120000FFF0UL,
|
||||
/* 0x0090, */ 0x0014100D0000C010UL,
|
||||
/* 0x0098, */ 0x0000000000000000UL,
|
||||
/* 0x00a0, */ 0x0000000000000000UL,
|
||||
/* 0x00a8, */ 0x0000000000000000UL,
|
||||
/* 0x00b0, */ 0x0000000000000000UL,
|
||||
/* 0x00b8, */ 0x0000000000000000UL,
|
||||
/* 0x00c0, */ 0x0000000000000000UL,
|
||||
/* 0x00c8, */ 0x0000000000000000UL,
|
||||
/* 0x00d0, */ 0x0000000000000000UL,
|
||||
/* 0x00d8, */ 0x0000000000000000UL,
|
||||
/* 0x00e0, */ 0x0000000000000000UL,
|
||||
/* 0x00e8, */ 0x0000000000000000UL,
|
||||
/* 0x00f0, */ 0x0000000000000000UL,
|
||||
/* 0x00f8, */ 0x0000000000000000UL,
|
||||
/* 0x0100, */ 0x0000000000000000UL,
|
||||
/* 0x0108, */ 0x0000000000000000UL,
|
||||
/* 0x0110, */ 0x0000000000000000UL,
|
||||
/* 0x0118, */ 0x0000000000000000UL,
|
||||
/* 0x0120, */ 0x0000000000000000UL,
|
||||
/* 0x0128, */ 0x0000000000000000UL,
|
||||
/* 0x0130, */ 0x0000000000000000UL,
|
||||
/* 0x0138, */ 0x0000000000000000UL,
|
||||
/* 0x0140, */ 0x0000000000000000UL,
|
||||
/* 0x0148, */ 0x0000000000000000UL,
|
||||
/* 0x0150, */ 0x0000000000000000UL,
|
||||
/* 0x0158, */ 0x0000000000000000UL,
|
||||
/* 0x0160, */ 0x0000000000000000UL,
|
||||
/* 0x0168, */ 0x0000000000000000UL,
|
||||
/* 0x0170, */ 0x0000000000000000UL,
|
||||
/* 0x0178, */ 0x0000000000000000UL,
|
||||
/* 0x0180, */ 0x0000000000000000UL,
|
||||
/* 0x0188, */ 0x0000000000000000UL,
|
||||
/* 0x0190, */ 0x0000000000000000UL,
|
||||
/* 0x0198, */ 0x0000000000000000UL,
|
||||
/* 0x01a0, */ 0x0000000000000000UL,
|
||||
/* 0x01a8, */ 0x0000000000000000UL,
|
||||
/* 0x01b0, */ 0x0000000000000000UL,
|
||||
/* 0x01b8, */ 0x0000000000000000UL,
|
||||
/* 0x01c0, */ 0x0000000000000000UL,
|
||||
/* 0x01c8, */ 0x0000000000000000UL,
|
||||
/* 0x01d0, */ 0x0000000000000000UL,
|
||||
/* 0x01d8, */ 0x0000000000000000UL,
|
||||
/* 0x01e0, */ 0x0000000000000000UL,
|
||||
/* 0x01e8, */ 0x0000000000000000UL,
|
||||
/* 0x01f0, */ 0x0000000000000000UL,
|
||||
/* 0x01f8, */ 0x0000000000000000UL,
|
||||
/* 0x0200, */ 0x0000000000000000UL,
|
||||
/* 0x0208, */ 0x0000000000000000UL,
|
||||
/* 0x0210, */ 0x0000000000000000UL,
|
||||
/* 0x0218, */ 0x0000000000000000UL,
|
||||
/* 0x0220, */ 0x0000000000000000UL,
|
||||
/* 0x0228, */ 0x0000000000000000UL,
|
||||
/* 0x0230, */ 0x0000000000000000UL,
|
||||
/* 0x0238, */ 0x0000000000000000UL,
|
||||
/* 0x0240, */ 0x0000000000000000UL,
|
||||
/* 0x0248, */ 0x0000000000000000UL,
|
||||
/* 0x0250, */ 0x0000000000000000UL,
|
||||
/* 0x0258, */ 0x0000000000000000UL,
|
||||
/* 0x0260, */ 0x000C0C030000FFF0UL,
|
||||
/* 0x0268, */ 0x001410010000FFF0UL,
|
||||
/* 0x0270, */ 0x001404010000FFF0UL,
|
||||
/* 0x0278, */ 0x000C08020000FFF0UL,
|
||||
/* 0x0280, */ 0x0000000000000000UL,
|
||||
/* 0x0288, */ 0x0000000000000000UL,
|
||||
/* 0x0290, */ 0x001410010000FFF0UL,
|
||||
/* 0x0298, */ 0x001404010000FFF0UL,
|
||||
/* 0x02a0, */ 0x0000000000000000UL,
|
||||
/* 0x02a8, */ 0x0000000000000000UL,
|
||||
/* 0x02b0, */ 0x0000000000000000UL,
|
||||
/* 0x02b8, */ 0x0000000000000000UL,
|
||||
/* 0x02c0, */ 0x0000000000000000UL,
|
||||
/* 0x02c8, */ 0x0000000000000000UL,
|
||||
/* 0x02d0, */ 0x0000000000000000UL,
|
||||
/* 0x02d8, */ 0x0000000000000000UL,
|
||||
/* 0x02e0, */ 0x0000000000000000UL,
|
||||
/* 0x02e8, */ 0x0000000000000000UL,
|
||||
/* 0x02f0, */ 0x0000000000000000UL,
|
||||
/* 0x02f8, */ 0x0000000000000000UL,
|
||||
/* 0x0300, */ 0x0000000000000000UL,
|
||||
/* 0x0308, */ 0x0000000000000000UL,
|
||||
/* 0x0310, */ 0x0000000000000000UL,
|
||||
/* 0x0318, */ 0x0000000000000000UL,
|
||||
/* 0x0320, */ 0x0000000000000000UL,
|
||||
/* 0x0328, */ 0x0000000000000000UL,
|
||||
/* 0x0330, */ 0x0000000000000000UL,
|
||||
/* 0x0338, */ 0x0000000000000000UL,
|
||||
/* 0x0340, */ 0x0000000000000000UL,
|
||||
/* 0x0348, */ 0x0000000000000000UL,
|
||||
/* 0x0350, */ 0x0000000000000000UL,
|
||||
};
|
||||
|
||||
static uint64_t qoswt_be[] = {
|
||||
/* 0x0000, */ 0x0000000000000000UL,
|
||||
/* 0x0008, */ 0x0000000000000000UL,
|
||||
/* 0x0010, */ 0x0000000000000000UL,
|
||||
/* 0x0018, */ 0x0000000000000000UL,
|
||||
/* 0x0020, */ 0x0000000000000000UL,
|
||||
/* 0x0028, */ 0x0000000000000000UL,
|
||||
/* 0x0030, */ 0x0000000000000000UL,
|
||||
/* 0x0038, */ 0x0000000000000000UL,
|
||||
/* 0x0040, */ 0x0000000000000000UL,
|
||||
/* 0x0048, */ 0x0000000000000000UL,
|
||||
/* 0x0050, */ 0x0000000000000000UL,
|
||||
/* 0x0058, */ 0x0000000000000000UL,
|
||||
/* 0x0060, */ 0x0000000000000000UL,
|
||||
/* 0x0068, */ 0x0000000000000000UL,
|
||||
/* 0x0070, */ 0x0000000000000000UL,
|
||||
/* 0x0078, */ 0x0000000000000000UL,
|
||||
/* 0x0080, */ 0x0000000000000000UL,
|
||||
/* 0x0088, */ 0x0000000000000000UL,
|
||||
/* 0x0090, */ 0x0000000000000000UL,
|
||||
/* 0x0098, */ 0x0000000000000000UL,
|
||||
/* 0x00a0, */ 0x0000000000000000UL,
|
||||
/* 0x00a8, */ 0x0000000000000000UL,
|
||||
/* 0x00b0, */ 0x0000000000000000UL,
|
||||
/* 0x00b8, */ 0x0000000000000000UL,
|
||||
/* 0x00c0, */ 0x0000000000000000UL,
|
||||
/* 0x00c8, */ 0x0000000000000000UL,
|
||||
/* 0x00d0, */ 0x0000000000000000UL,
|
||||
/* 0x00d8, */ 0x0000000000000000UL,
|
||||
/* 0x00e0, */ 0x0000000000000000UL,
|
||||
/* 0x00e8, */ 0x0000000000000000UL,
|
||||
/* 0x00f0, */ 0x0000000000000000UL,
|
||||
/* 0x00f8, */ 0x0000000000000000UL,
|
||||
/* 0x0100, */ 0x0000000000000000UL,
|
||||
/* 0x0108, */ 0x0000000000000000UL,
|
||||
/* 0x0110, */ 0x0000000000000000UL,
|
||||
/* 0x0118, */ 0x0000000000000000UL,
|
||||
/* 0x0120, */ 0x0000000000000000UL,
|
||||
/* 0x0128, */ 0x0000000000000000UL,
|
||||
/* 0x0130, */ 0x0000000000000000UL,
|
||||
/* 0x0138, */ 0x0000000000000000UL,
|
||||
/* 0x0140, */ 0x0000000000000000UL,
|
||||
/* 0x0148, */ 0x0000000000000000UL,
|
||||
/* 0x0150, */ 0x0000000000000000UL,
|
||||
/* 0x0158, */ 0x0000000000000000UL,
|
||||
/* 0x0160, */ 0x0000000000000000UL,
|
||||
/* 0x0168, */ 0x0000000000000000UL,
|
||||
/* 0x0170, */ 0x0000000000000000UL,
|
||||
/* 0x0178, */ 0x0000000000000000UL,
|
||||
/* 0x0180, */ 0x0000000000000000UL,
|
||||
/* 0x0188, */ 0x0000000000000000UL,
|
||||
/* 0x0190, */ 0x0000000000000000UL,
|
||||
/* 0x0198, */ 0x0000000000000000UL,
|
||||
/* 0x01a0, */ 0x0000000000000000UL,
|
||||
/* 0x01a8, */ 0x0000000000000000UL,
|
||||
/* 0x01b0, */ 0x0000000000000000UL,
|
||||
/* 0x01b8, */ 0x0000000000000000UL,
|
||||
/* 0x01c0, */ 0x0000000000000000UL,
|
||||
/* 0x01c8, */ 0x0000000000000000UL,
|
||||
/* 0x01d0, */ 0x0000000000000000UL,
|
||||
/* 0x01d8, */ 0x0000000000000000UL,
|
||||
/* 0x01e0, */ 0x0000000000000000UL,
|
||||
/* 0x01e8, */ 0x0000000000000000UL,
|
||||
/* 0x01f0, */ 0x0000000000000000UL,
|
||||
/* 0x01f8, */ 0x0000000000000000UL,
|
||||
/* 0x0200, */ 0x0000000000000000UL,
|
||||
/* 0x0208, */ 0x0000000000000000UL,
|
||||
/* 0x0210, */ 0x0000000000000000UL,
|
||||
/* 0x0218, */ 0x0000000000000000UL,
|
||||
/* 0x0220, */ 0x0000000000000000UL,
|
||||
/* 0x0228, */ 0x0000000000000000UL,
|
||||
/* 0x0230, */ 0x0000000000000000UL,
|
||||
/* 0x0238, */ 0x0000000000000000UL,
|
||||
/* 0x0240, */ 0x0000000000000000UL,
|
||||
/* 0x0248, */ 0x0000000000000000UL,
|
||||
/* 0x0250, */ 0x0000000000000000UL,
|
||||
/* 0x0258, */ 0x0000000000000000UL,
|
||||
/* 0x0260, */ 0x0000000000000000UL,
|
||||
/* 0x0268, */ 0x0000000000000000UL,
|
||||
/* 0x0270, */ 0x0000000000000000UL,
|
||||
/* 0x0278, */ 0x0000000000000000UL,
|
||||
/* 0x0280, */ 0x0000000000000000UL,
|
||||
/* 0x0288, */ 0x0000000000000000UL,
|
||||
/* 0x0290, */ 0x0000000000000000UL,
|
||||
/* 0x0298, */ 0x0000000000000000UL,
|
||||
/* 0x02a0, */ 0x0000000000000000UL,
|
||||
/* 0x02a8, */ 0x0000000000000000UL,
|
||||
/* 0x02b0, */ 0x0000000000000000UL,
|
||||
/* 0x02b8, */ 0x0000000000000000UL,
|
||||
/* 0x02c0, */ 0x0000000000000000UL,
|
||||
/* 0x02c8, */ 0x0000000000000000UL,
|
||||
/* 0x02d0, */ 0x0000000000000000UL,
|
||||
/* 0x02d8, */ 0x0000000000000000UL,
|
||||
/* 0x02e0, */ 0x0000000000000000UL,
|
||||
/* 0x02e8, */ 0x0000000000000000UL,
|
||||
/* 0x02f0, */ 0x0000000000000000UL,
|
||||
/* 0x02f8, */ 0x0000000000000000UL,
|
||||
/* 0x0300, */ 0x0000000000000000UL,
|
||||
/* 0x0308, */ 0x0000000000000000UL,
|
||||
/* 0x0310, */ 0x0000000000000000UL,
|
||||
/* 0x0318, */ 0x0000000000000000UL,
|
||||
/* 0x0320, */ 0x0000000000000000UL,
|
||||
/* 0x0328, */ 0x0000000000000000UL,
|
||||
/* 0x0330, */ 0x0000000000000000UL,
|
||||
/* 0x0338, */ 0x0000000000000000UL,
|
||||
/* 0x0340, */ 0x0000000000000000UL,
|
||||
/* 0x0348, */ 0x0000000000000000UL,
|
||||
/* 0x0350, */ 0x0000000000000000UL,
|
||||
};
|
237
drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
Normal file
237
drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
Normal file
|
@ -0,0 +1,237 @@
|
|||
/*
|
||||
* Copyright (c) 2017-2018, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <debug.h>
|
||||
#include "../qos_common.h"
|
||||
#include "../qos_reg.h"
|
||||
#include "qos_init_m3n_v10.h"
|
||||
|
||||
#define RCAR_QOS_VERSION "rev.0.06"
|
||||
|
||||
#define QOSCTRL_EARLYR (QOS_BASE1 + 0x0060U)
|
||||
#define QOSCTRL_FSS (QOS_BASE1 + 0x0048U)
|
||||
|
||||
#define REF_ARS_ARBSTOPCYCLE_M3N (((SL_INIT_SSLOTCLK_M3N) - 5U) << 16U)
|
||||
|
||||
#define QOSWT_TIME_BANK0 (20000000U) /* unit:ns */
|
||||
|
||||
#define QOSWT_WTEN_ENABLE (0x1U)
|
||||
|
||||
#define OSWT_WTREF_SLOT0_EN_REQ1_SLOT (3U)
|
||||
#define OSWT_WTREF_SLOT0_EN_REQ2_SLOT (9U)
|
||||
#define QOSWT_WTREF_SLOT0_EN ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
|
||||
#define QOSWT_WTREF_SLOT1_EN QOSWT_WTREF_SLOT0_EN
|
||||
|
||||
#define QOSWT_WTSET0_REQ_SSLOT0 (5U)
|
||||
#define WT_BASE_SUB_SLOT_NUM0 (12U)
|
||||
#define QOSWT_WTSET0_PERIOD0_M3N ((QOSWT_TIME_BANK0/QOSWT_WTSET0_CYCLE_M3N)-1U)
|
||||
#define QOSWT_WTSET0_SSLOT0 (QOSWT_WTSET0_REQ_SSLOT0 -1U)
|
||||
#define QOSWT_WTSET0_SLOTSLOT0 (WT_BASE_SUB_SLOT_NUM0 -1U)
|
||||
|
||||
#define QOSWT_WTSET1_PERIOD1_M3N QOSWT_WTSET0_PERIOD0_M3N
|
||||
#define QOSWT_WTSET1_SSLOT1 QOSWT_WTSET0_SSLOT0
|
||||
#define QOSWT_WTSET1_SLOTSLOT1 QOSWT_WTSET0_SLOTSLOT0
|
||||
|
||||
#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
|
||||
|
||||
#if RCAR_REF_INT == RCAR_REF_DEFAULT
|
||||
#include "qos_init_m3n_v10_mstat195.h"
|
||||
#else
|
||||
#include "qos_init_m3n_v10_mstat390.h"
|
||||
#endif
|
||||
|
||||
#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
|
||||
|
||||
#if RCAR_REF_INT == RCAR_REF_DEFAULT
|
||||
#include "qos_init_m3n_v10_qoswt195.h"
|
||||
#else
|
||||
#include "qos_init_m3n_v10_qoswt390.h"
|
||||
#endif
|
||||
|
||||
#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
|
||||
#endif
|
||||
|
||||
static void dbsc_setting(void)
|
||||
{
|
||||
uint32_t md = 0;
|
||||
|
||||
/* Register write enable */
|
||||
io_write_32(DBSC_DBSYSCNT0, 0x00001234U);
|
||||
|
||||
/* BUFCAM settings */
|
||||
io_write_32(DBSC_DBCAM0CNF1, 0x00043218); /* dbcam0cnf1 */
|
||||
io_write_32(DBSC_DBCAM0CNF2, 0x000000F4); /* dbcam0cnf2 */
|
||||
io_write_32(DBSC_DBSCHCNT0, 0x000F0037); /* dbschcnt0 */
|
||||
io_write_32(DBSC_DBSCHSZ0, 0x00000001); /* dbschsz0 */
|
||||
io_write_32(DBSC_DBSCHRW0, 0x22421111); /* dbschrw0 */
|
||||
|
||||
md = (*((volatile uint32_t *)RST_MODEMR) & 0x000A0000) >> 17;
|
||||
|
||||
switch (md) {
|
||||
case 0x0:
|
||||
/* DDR3200 */
|
||||
io_write_32(DBSC_SCFCTST2, 0x012F1123);
|
||||
break;
|
||||
case 0x1: /* MD19=0,MD17=1 : LPDDR4-3000, 4GByte(1GByte x4) */
|
||||
/* DDR2800 */
|
||||
io_write_32(DBSC_SCFCTST2, 0x012F1123);
|
||||
break;
|
||||
case 0x4: /* MD19=1,MD17=0 : LPDDR4-2400, 4GByte(1GByte x4) */
|
||||
/* DDR2400 */
|
||||
io_write_32(DBSC_SCFCTST2, 0x012F1123);
|
||||
break;
|
||||
default: /* MD19=1,MD17=1 : LPDDR4-1600, 4GByte(1GByte x4) */
|
||||
/* DDR1600 */
|
||||
io_write_32(DBSC_SCFCTST2, 0x012F1123);
|
||||
break;
|
||||
}
|
||||
|
||||
/* QoS Settings */
|
||||
io_write_32(DBSC_DBSCHQOS00, 0x00000F00);
|
||||
io_write_32(DBSC_DBSCHQOS01, 0x00000B00);
|
||||
io_write_32(DBSC_DBSCHQOS02, 0x00000000);
|
||||
io_write_32(DBSC_DBSCHQOS03, 0x00000000);
|
||||
io_write_32(DBSC_DBSCHQOS40, 0x00000300);
|
||||
io_write_32(DBSC_DBSCHQOS41, 0x000002F0);
|
||||
io_write_32(DBSC_DBSCHQOS42, 0x00000200);
|
||||
io_write_32(DBSC_DBSCHQOS43, 0x00000100);
|
||||
io_write_32(DBSC_DBSCHQOS90, 0x00000100);
|
||||
io_write_32(DBSC_DBSCHQOS91, 0x000000F0);
|
||||
io_write_32(DBSC_DBSCHQOS92, 0x000000A0);
|
||||
io_write_32(DBSC_DBSCHQOS93, 0x00000040);
|
||||
io_write_32(DBSC_DBSCHQOS130, 0x00000100);
|
||||
io_write_32(DBSC_DBSCHQOS131, 0x000000F0);
|
||||
io_write_32(DBSC_DBSCHQOS132, 0x000000A0);
|
||||
io_write_32(DBSC_DBSCHQOS133, 0x00000040);
|
||||
io_write_32(DBSC_DBSCHQOS140, 0x000000C0);
|
||||
io_write_32(DBSC_DBSCHQOS141, 0x000000B0);
|
||||
io_write_32(DBSC_DBSCHQOS142, 0x00000080);
|
||||
io_write_32(DBSC_DBSCHQOS143, 0x00000040);
|
||||
io_write_32(DBSC_DBSCHQOS150, 0x00000040);
|
||||
io_write_32(DBSC_DBSCHQOS151, 0x00000030);
|
||||
io_write_32(DBSC_DBSCHQOS152, 0x00000020);
|
||||
io_write_32(DBSC_DBSCHQOS153, 0x00000010);
|
||||
|
||||
/* Register write protect */
|
||||
io_write_32(DBSC_DBSYSCNT0, 0x00000000U);
|
||||
}
|
||||
|
||||
void qos_init_m3n_v10(void)
|
||||
{
|
||||
dbsc_setting();
|
||||
|
||||
/* DRAM Split Address mapping */
|
||||
#if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH
|
||||
#if RCAR_LSI == RCAR_M3N
|
||||
#error "Don't set DRAM Split 4ch(M3N)"
|
||||
#else
|
||||
ERROR("DRAM Split 4ch not supported.(M3N)");
|
||||
panic();
|
||||
#endif
|
||||
#elif (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH)
|
||||
#if RCAR_LSI == RCAR_M3N
|
||||
#error "Don't set DRAM Split 2ch(M3N)"
|
||||
#else
|
||||
ERROR("DRAM Split 2ch not supported.(M3N)");
|
||||
panic();
|
||||
#endif
|
||||
#else
|
||||
NOTICE("BL2: DRAM Split is OFF\n");
|
||||
#endif
|
||||
|
||||
#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
|
||||
#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
|
||||
NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
|
||||
#endif
|
||||
|
||||
#if RCAR_REF_INT == RCAR_REF_DEFAULT
|
||||
NOTICE("BL2: DRAM refresh interval 1.95 usec\n");
|
||||
#else
|
||||
NOTICE("BL2: DRAM refresh interval 3.9 usec\n");
|
||||
#endif
|
||||
|
||||
#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
|
||||
NOTICE("BL2: Periodic Write DQ Training\n");
|
||||
#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
|
||||
|
||||
io_write_32(QOSCTRL_RAS, 0x00000028U);
|
||||
io_write_64(QOSCTRL_DANN, 0x0402000002020201UL);
|
||||
io_write_32(QOSCTRL_DANT, 0x00100804U);
|
||||
io_write_32(QOSCTRL_FSS, 0x0000000AU);
|
||||
io_write_32(QOSCTRL_INSFC, 0x06330001U);
|
||||
io_write_32(QOSCTRL_EARLYR, 0x00000001U);
|
||||
io_write_32(QOSCTRL_RACNT0, 0x00010003U);
|
||||
|
||||
io_write_32(QOSCTRL_SL_INIT,
|
||||
SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT |
|
||||
SL_INIT_SSLOTCLK_M3N);
|
||||
io_write_32(QOSCTRL_REF_ARS, REF_ARS_ARBSTOPCYCLE_M3N);
|
||||
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
|
||||
io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
|
||||
io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
|
||||
}
|
||||
for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
|
||||
io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
|
||||
io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
|
||||
}
|
||||
#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
|
||||
for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) {
|
||||
io_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8,
|
||||
qoswt_fix[i]);
|
||||
io_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8,
|
||||
qoswt_fix[i]);
|
||||
}
|
||||
for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) {
|
||||
io_write_64(QOSWT_BE_WTQOS_BANK0 + i * 8, qoswt_be[i]);
|
||||
io_write_64(QOSWT_BE_WTQOS_BANK1 + i * 8, qoswt_be[i]);
|
||||
}
|
||||
#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
|
||||
}
|
||||
|
||||
/* 3DG bus Leaf setting */
|
||||
io_write_32(GPU_ACT_GRD, 0x00001234U);
|
||||
io_write_32(GPU_ACT0, 0x00000000U);
|
||||
io_write_32(GPU_ACT1, 0x00000000U);
|
||||
io_write_32(GPU_ACT2, 0x00000000U);
|
||||
io_write_32(GPU_ACT3, 0x00000000U);
|
||||
io_write_32(GPU_ACT_GRD, 0x00000000U);
|
||||
|
||||
/* RT bus Leaf setting */
|
||||
io_write_32(RT_ACT0, 0x00000000U);
|
||||
io_write_32(RT_ACT1, 0x00000000U);
|
||||
|
||||
/* CCI bus Leaf setting */
|
||||
io_write_32(CPU_ACT0, 0x00000003U);
|
||||
io_write_32(CPU_ACT1, 0x00000003U);
|
||||
|
||||
io_write_32(QOSCTRL_RAEN, 0x00000001U);
|
||||
|
||||
#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
|
||||
/* re-write training setting */
|
||||
io_write_32(QOSWT_WTREF,
|
||||
((QOSWT_WTREF_SLOT1_EN << 16) | QOSWT_WTREF_SLOT0_EN));
|
||||
io_write_32(QOSWT_WTSET0,
|
||||
((QOSWT_WTSET0_PERIOD0_M3N << 16) |
|
||||
(QOSWT_WTSET0_SSLOT0 << 8) | QOSWT_WTSET0_SLOTSLOT0));
|
||||
io_write_32(QOSWT_WTSET1,
|
||||
((QOSWT_WTSET1_PERIOD1_M3N << 16) |
|
||||
(QOSWT_WTSET1_SSLOT1 << 8) | QOSWT_WTSET1_SLOTSLOT1));
|
||||
|
||||
io_write_32(QOSWT_WTEN, QOSWT_WTEN_ENABLE);
|
||||
#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
|
||||
|
||||
io_write_32(QOSCTRL_STATQC, 0x00000001U);
|
||||
#else
|
||||
NOTICE("BL2: QoS is None\n");
|
||||
|
||||
io_write_32(QOSCTRL_RAEN, 0x00000001U);
|
||||
#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
|
||||
}
|
12
drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10.h
Normal file
12
drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10.h
Normal file
|
@ -0,0 +1,12 @@
|
|||
/*
|
||||
* Copyright (c) 2017, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef QOS_INIT_H_M3N_V10__
|
||||
#define QOS_INIT_H_M3N_V10__
|
||||
|
||||
void qos_init_m3n_v10(void);
|
||||
|
||||
#endif /* QOS_INIT_H_M3N_V10__ */
|
241
drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10_mstat195.h
Normal file
241
drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10_mstat195.h
Normal file
|
@ -0,0 +1,241 @@
|
|||
/*
|
||||
* Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
static uint64_t mstat_fix[] = {
|
||||
/* 0x0000, */ 0x0000000000000000UL,
|
||||
/* 0x0008, */ 0x0000000000000000UL,
|
||||
/* 0x0010, */ 0x0000000000000000UL,
|
||||
/* 0x0018, */ 0x0000000000000000UL,
|
||||
/* 0x0020, */ 0x0000000000000000UL,
|
||||
/* 0x0028, */ 0x0000000000000000UL,
|
||||
/* 0x0030, */ 0x001004320000FFFFUL,
|
||||
/* 0x0038, */ 0x001004320000FFFFUL,
|
||||
/* 0x0040, */ 0x00140C5D0000FFFFUL,
|
||||
/* 0x0048, */ 0x0000000000000000UL,
|
||||
/* 0x0050, */ 0x001404040000FFFFUL,
|
||||
/* 0x0058, */ 0x00140C940000FFFFUL,
|
||||
/* 0x0060, */ 0x00140C940000FFFFUL,
|
||||
/* 0x0068, */ 0x0000000000000000UL,
|
||||
/* 0x0070, */ 0x001404040000FFFFUL,
|
||||
/* 0x0078, */ 0x0000000000000000UL,
|
||||
/* 0x0080, */ 0x0000000000000000UL,
|
||||
/* 0x0088, */ 0x0014041F0000FFFFUL,
|
||||
/* 0x0090, */ 0x0000000000000000UL,
|
||||
/* 0x0098, */ 0x0000000000000000UL,
|
||||
/* 0x00a0, */ 0x000C041D0000FFFFUL,
|
||||
/* 0x00a8, */ 0x000C04090000FFFFUL,
|
||||
/* 0x00b0, */ 0x000C04090000FFFFUL,
|
||||
/* 0x00b8, */ 0x0000000000000000UL,
|
||||
/* 0x00c0, */ 0x000C041D0000FFFFUL,
|
||||
/* 0x00c8, */ 0x000C04090000FFFFUL,
|
||||
/* 0x00d0, */ 0x000C04090000FFFFUL,
|
||||
/* 0x00d8, */ 0x0000000000000000UL,
|
||||
/* 0x00e0, */ 0x0000000000000000UL,
|
||||
/* 0x00e8, */ 0x0000000000000000UL,
|
||||
/* 0x00f0, */ 0x001024840000FFFFUL,
|
||||
/* 0x00f8, */ 0x000C084F0000FFFFUL,
|
||||
/* 0x0100, */ 0x0000000000000000UL,
|
||||
/* 0x0108, */ 0x0000000000000000UL,
|
||||
/* 0x0110, */ 0x00100C840000FFFFUL,
|
||||
/* 0x0118, */ 0x000C21E60000FFFFUL,
|
||||
/* 0x0120, */ 0x0000000000000000UL,
|
||||
/* 0x0128, */ 0x0000000000000000UL,
|
||||
/* 0x0130, */ 0x0000000000000000UL,
|
||||
/* 0x0138, */ 0x00100CA50000FFFFUL,
|
||||
/* 0x0140, */ 0x0000000000000000UL,
|
||||
/* 0x0148, */ 0x0000000000000000UL,
|
||||
/* 0x0150, */ 0x001010C90000FFFFUL,
|
||||
/* 0x0158, */ 0x0000000000000000UL,
|
||||
/* 0x0160, */ 0x00100CA50000FFFFUL,
|
||||
/* 0x0168, */ 0x0000000000000000UL,
|
||||
/* 0x0170, */ 0x0000000000000000UL,
|
||||
/* 0x0178, */ 0x001008530000FFFFUL,
|
||||
/* 0x0180, */ 0x0000000000000000UL,
|
||||
/* 0x0188, */ 0x0000000000000000UL,
|
||||
/* 0x0190, */ 0x00101D9D0000FFFFUL,
|
||||
/* 0x0198, */ 0x0000000000000000UL,
|
||||
/* 0x01a0, */ 0x00100CA50000FFFFUL,
|
||||
/* 0x01a8, */ 0x0000000000000000UL,
|
||||
/* 0x01b0, */ 0x0000000000000000UL,
|
||||
/* 0x01b8, */ 0x0000000000000000UL,
|
||||
/* 0x01c0, */ 0x000C04010000FFFFUL,
|
||||
/* 0x01c8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x01d0, */ 0x0000000000000000UL,
|
||||
/* 0x01d8, */ 0x0000000000000000UL,
|
||||
/* 0x01e0, */ 0x0000000000000000UL,
|
||||
/* 0x01e8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x01f0, */ 0x000C04050000FFFFUL,
|
||||
/* 0x01f8, */ 0x0000000000000000UL,
|
||||
/* 0x0200, */ 0x0000000000000000UL,
|
||||
/* 0x0208, */ 0x000C04050000FFFFUL,
|
||||
/* 0x0210, */ 0x000C04050000FFFFUL,
|
||||
/* 0x0218, */ 0x0000000000000000UL,
|
||||
/* 0x0220, */ 0x0000000000000000UL,
|
||||
/* 0x0228, */ 0x0000000000000000UL,
|
||||
/* 0x0230, */ 0x0000000000000000UL,
|
||||
/* 0x0238, */ 0x0000000000000000UL,
|
||||
/* 0x0240, */ 0x0000000000000000UL,
|
||||
/* 0x0248, */ 0x0000000000000000UL,
|
||||
/* 0x0250, */ 0x0000000000000000UL,
|
||||
/* 0x0258, */ 0x0000000000000000UL,
|
||||
/* 0x0260, */ 0x000C08150000FFFFUL,
|
||||
/* 0x0268, */ 0x001408020000FFFFUL,
|
||||
/* 0x0270, */ 0x001404010000FFFFUL,
|
||||
/* 0x0278, */ 0x000C04090000FFFFUL,
|
||||
/* 0x0280, */ 0x0000000000000000UL,
|
||||
/* 0x0288, */ 0x0000000000000000UL,
|
||||
/* 0x0290, */ 0x001408020000FFFFUL,
|
||||
/* 0x0298, */ 0x001404010000FFFFUL,
|
||||
/* 0x02a0, */ 0x000C04050000FFFFUL,
|
||||
/* 0x02a8, */ 0x000C04050000FFFFUL,
|
||||
/* 0x02b0, */ 0x001408050000FFFFUL,
|
||||
/* 0x02b8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x02c0, */ 0x0000000000000000UL,
|
||||
/* 0x02c8, */ 0x0000000000000000UL,
|
||||
/* 0x02d0, */ 0x000C04050000FFFFUL,
|
||||
/* 0x02d8, */ 0x000C04050000FFFFUL,
|
||||
/* 0x02e0, */ 0x001408050000FFFFUL,
|
||||
/* 0x02e8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x02f0, */ 0x0000000000000000UL,
|
||||
/* 0x02f8, */ 0x0000000000000000UL,
|
||||
/* 0x0300, */ 0x0000000000000000UL,
|
||||
/* 0x0308, */ 0x0000000000000000UL,
|
||||
/* 0x0310, */ 0x0000000000000000UL,
|
||||
/* 0x0318, */ 0x0000000000000000UL,
|
||||
/* 0x0320, */ 0x0000000000000000UL,
|
||||
/* 0x0328, */ 0x0000000000000000UL,
|
||||
/* 0x0330, */ 0x0000000000000000UL,
|
||||
/* 0x0338, */ 0x0000000000000000UL,
|
||||
/* 0x0340, */ 0x0000000000000000UL,
|
||||
/* 0x0348, */ 0x0000000000000000UL,
|
||||
/* 0x0350, */ 0x0000000000000000UL,
|
||||
/* 0x0358, */ 0x0000000000000000UL,
|
||||
/* 0x0360, */ 0x0000000000000000UL,
|
||||
/* 0x0368, */ 0x0000000000000000UL,
|
||||
/* 0x0370, */ 0x000C04010000FFFFUL,
|
||||
/* 0x0378, */ 0x000C04010000FFFFUL,
|
||||
/* 0x0380, */ 0x000C04050000FFFFUL,
|
||||
/* 0x0388, */ 0x000C04050000FFFFUL,
|
||||
/* 0x0390, */ 0x0000000000000000UL,
|
||||
};
|
||||
|
||||
static uint64_t mstat_be[] = {
|
||||
/* 0x0000, */ 0x0000000000000000UL,
|
||||
/* 0x0008, */ 0x0000000000000000UL,
|
||||
/* 0x0010, */ 0x0000000000000000UL,
|
||||
/* 0x0018, */ 0x0000000000000000UL,
|
||||
/* 0x0020, */ 0x0000000000000000UL,
|
||||
/* 0x0028, */ 0x001200100BD03401UL,
|
||||
/* 0x0030, */ 0x0000000000000000UL,
|
||||
/* 0x0038, */ 0x0000000000000000UL,
|
||||
/* 0x0040, */ 0x0000000000000000UL,
|
||||
/* 0x0048, */ 0x0000000000000000UL,
|
||||
/* 0x0050, */ 0x0000000000000000UL,
|
||||
/* 0x0058, */ 0x0000000000000000UL,
|
||||
/* 0x0060, */ 0x0000000000000000UL,
|
||||
/* 0x0068, */ 0x0000000000000000UL,
|
||||
/* 0x0070, */ 0x0000000000000000UL,
|
||||
/* 0x0078, */ 0x0000000000000000UL,
|
||||
/* 0x0080, */ 0x0000000000000000UL,
|
||||
/* 0x0088, */ 0x0000000000000000UL,
|
||||
/* 0x0090, */ 0x0000000000000000UL,
|
||||
/* 0x0098, */ 0x0000000000000000UL,
|
||||
/* 0x00a0, */ 0x0000000000000000UL,
|
||||
/* 0x00a8, */ 0x0000000000000000UL,
|
||||
/* 0x00b0, */ 0x0000000000000000UL,
|
||||
/* 0x00b8, */ 0x0000000000000000UL,
|
||||
/* 0x00c0, */ 0x0000000000000000UL,
|
||||
/* 0x00c8, */ 0x0000000000000000UL,
|
||||
/* 0x00d0, */ 0x0000000000000000UL,
|
||||
/* 0x00d8, */ 0x0000000000000000UL,
|
||||
/* 0x00e0, */ 0x0000000000000000UL,
|
||||
/* 0x00e8, */ 0x0000000000000000UL,
|
||||
/* 0x00f0, */ 0x0000000000000000UL,
|
||||
/* 0x00f8, */ 0x0000000000000000UL,
|
||||
/* 0x0100, */ 0x0000000000000000UL,
|
||||
/* 0x0108, */ 0x0000000000000000UL,
|
||||
/* 0x0110, */ 0x0000000000000000UL,
|
||||
/* 0x0118, */ 0x0000000000000000UL,
|
||||
/* 0x0120, */ 0x0000000000000000UL,
|
||||
/* 0x0128, */ 0x0000000000000000UL,
|
||||
/* 0x0130, */ 0x0000000000000000UL,
|
||||
/* 0x0138, */ 0x0000000000000000UL,
|
||||
/* 0x0140, */ 0x0000000000000000UL,
|
||||
/* 0x0148, */ 0x0000000000000000UL,
|
||||
/* 0x0150, */ 0x0000000000000000UL,
|
||||
/* 0x0158, */ 0x0000000000000000UL,
|
||||
/* 0x0160, */ 0x0000000000000000UL,
|
||||
/* 0x0168, */ 0x0000000000000000UL,
|
||||
/* 0x0170, */ 0x0000000000000000UL,
|
||||
/* 0x0178, */ 0x0000000000000000UL,
|
||||
/* 0x0180, */ 0x0000000000000000UL,
|
||||
/* 0x0188, */ 0x0000000000000000UL,
|
||||
/* 0x0190, */ 0x0000000000000000UL,
|
||||
/* 0x0198, */ 0x0000000000000000UL,
|
||||
/* 0x01a0, */ 0x0000000000000000UL,
|
||||
/* 0x01a8, */ 0x0000000000000000UL,
|
||||
/* 0x01b0, */ 0x0000000000000000UL,
|
||||
/* 0x01b8, */ 0x0000000000000000UL,
|
||||
/* 0x01c0, */ 0x002106000BDFFC01UL,
|
||||
/* 0x01c8, */ 0x002106000BDFFC01UL,
|
||||
/* 0x01d0, */ 0x0000000000000000UL,
|
||||
/* 0x01d8, */ 0x0000000000000000UL,
|
||||
/* 0x01e0, */ 0x0000000000000000UL,
|
||||
/* 0x01e8, */ 0x0000000000000000UL,
|
||||
/* 0x01f0, */ 0x002101000BDF2401UL,
|
||||
/* 0x01f8, */ 0x0000000000000000UL,
|
||||
/* 0x0200, */ 0x0000000000000000UL,
|
||||
/* 0x0208, */ 0x0000000000000000UL,
|
||||
/* 0x0210, */ 0x002101000BDF2401UL,
|
||||
/* 0x0218, */ 0x001101000BDF2401UL,
|
||||
/* 0x0220, */ 0x001101000BDF2401UL,
|
||||
/* 0x0228, */ 0x0000000000000000UL,
|
||||
/* 0x0230, */ 0x001101000BDF2401UL,
|
||||
/* 0x0238, */ 0x001101000BDF2401UL,
|
||||
/* 0x0240, */ 0x001201000BDF2401UL,
|
||||
/* 0x0248, */ 0x001101000BDF2401UL,
|
||||
/* 0x0250, */ 0x001201000BDF2401UL,
|
||||
/* 0x0258, */ 0x001101000BDF2401UL,
|
||||
/* 0x0260, */ 0x0000000000000000UL,
|
||||
/* 0x0268, */ 0x0000000000000000UL,
|
||||
/* 0x0270, */ 0x0000000000000000UL,
|
||||
/* 0x0278, */ 0x0000000000000000UL,
|
||||
/* 0x0280, */ 0x0000000000000000UL,
|
||||
/* 0x0288, */ 0x0000000000000000UL,
|
||||
/* 0x0290, */ 0x0000000000000000UL,
|
||||
/* 0x0298, */ 0x0000000000000000UL,
|
||||
/* 0x02a0, */ 0x0000000000000000UL,
|
||||
/* 0x02a8, */ 0x0000000000000000UL,
|
||||
/* 0x02b0, */ 0x0000000000000000UL,
|
||||
/* 0x02b8, */ 0x0000000000000000UL,
|
||||
/* 0x02c0, */ 0x0000000000000000UL,
|
||||
/* 0x02c8, */ 0x0000000000000000UL,
|
||||
/* 0x02d0, */ 0x0000000000000000UL,
|
||||
/* 0x02d8, */ 0x0000000000000000UL,
|
||||
/* 0x02e0, */ 0x0000000000000000UL,
|
||||
/* 0x02e8, */ 0x0000000000000000UL,
|
||||
/* 0x02f0, */ 0x001106000BDFFC01UL,
|
||||
/* 0x02f8, */ 0x001106000BDFFC01UL,
|
||||
/* 0x0300, */ 0x0000000000000000UL,
|
||||
/* 0x0308, */ 0x0000000000000000UL,
|
||||
/* 0x0310, */ 0x0000000000000000UL,
|
||||
/* 0x0318, */ 0x001200100BD03401UL,
|
||||
/* 0x0320, */ 0x0000000000000000UL,
|
||||
/* 0x0328, */ 0x0000000000000000UL,
|
||||
/* 0x0330, */ 0x0000000000000000UL,
|
||||
/* 0x0338, */ 0x0000000000000000UL,
|
||||
/* 0x0340, */ 0x0000000000000000UL,
|
||||
/* 0x0348, */ 0x0000000000000000UL,
|
||||
/* 0x0350, */ 0x0000000000000000UL,
|
||||
/* 0x0358, */ 0x001206000BDFFC01UL,
|
||||
/* 0x0360, */ 0x001206000BDFFC01UL,
|
||||
/* 0x0368, */ 0x001200100BD03401UL,
|
||||
/* 0x0370, */ 0x0000000000000000UL,
|
||||
/* 0x0378, */ 0x0000000000000000UL,
|
||||
/* 0x0380, */ 0x0000000000000000UL,
|
||||
/* 0x0388, */ 0x0000000000000000UL,
|
||||
/* 0x0390, */ 0x001200100BD03401UL,
|
||||
};
|
241
drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10_mstat390.h
Normal file
241
drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10_mstat390.h
Normal file
|
@ -0,0 +1,241 @@
|
|||
/*
|
||||
* Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
static uint64_t mstat_fix[] = {
|
||||
/* 0x0000, */ 0x0000000000000000UL,
|
||||
/* 0x0008, */ 0x0000000000000000UL,
|
||||
/* 0x0010, */ 0x0000000000000000UL,
|
||||
/* 0x0018, */ 0x0000000000000000UL,
|
||||
/* 0x0020, */ 0x0000000000000000UL,
|
||||
/* 0x0028, */ 0x0000000000000000UL,
|
||||
/* 0x0030, */ 0x001008630000FFFFUL,
|
||||
/* 0x0038, */ 0x001008630000FFFFUL,
|
||||
/* 0x0040, */ 0x001418BA0000FFFFUL,
|
||||
/* 0x0048, */ 0x0000000000000000UL,
|
||||
/* 0x0050, */ 0x001404070000FFFFUL,
|
||||
/* 0x0058, */ 0x001415270000FFFFUL,
|
||||
/* 0x0060, */ 0x001415270000FFFFUL,
|
||||
/* 0x0068, */ 0x0000000000000000UL,
|
||||
/* 0x0070, */ 0x001404070000FFFFUL,
|
||||
/* 0x0078, */ 0x0000000000000000UL,
|
||||
/* 0x0080, */ 0x0000000000000000UL,
|
||||
/* 0x0088, */ 0x0014083E0000FFFFUL,
|
||||
/* 0x0090, */ 0x0000000000000000UL,
|
||||
/* 0x0098, */ 0x0000000000000000UL,
|
||||
/* 0x00a0, */ 0x000C08390000FFFFUL,
|
||||
/* 0x00a8, */ 0x000C04110000FFFFUL,
|
||||
/* 0x00b0, */ 0x000C04110000FFFFUL,
|
||||
/* 0x00b8, */ 0x0000000000000000UL,
|
||||
/* 0x00c0, */ 0x000C08390000FFFFUL,
|
||||
/* 0x00c8, */ 0x000C04110000FFFFUL,
|
||||
/* 0x00d0, */ 0x000C04110000FFFFUL,
|
||||
/* 0x00d8, */ 0x0000000000000000UL,
|
||||
/* 0x00e0, */ 0x0000000000000000UL,
|
||||
/* 0x00e8, */ 0x0000000000000000UL,
|
||||
/* 0x00f0, */ 0x001045080000FFFFUL,
|
||||
/* 0x00f8, */ 0x000C0C9E0000FFFFUL,
|
||||
/* 0x0100, */ 0x0000000000000000UL,
|
||||
/* 0x0108, */ 0x0000000000000000UL,
|
||||
/* 0x0110, */ 0x001015080000FFFFUL,
|
||||
/* 0x0118, */ 0x000C43CB0000FFFFUL,
|
||||
/* 0x0120, */ 0x0000000000000000UL,
|
||||
/* 0x0128, */ 0x0000000000000000UL,
|
||||
/* 0x0130, */ 0x0000000000000000UL,
|
||||
/* 0x0138, */ 0x0010194A0000FFFFUL,
|
||||
/* 0x0140, */ 0x0000000000000000UL,
|
||||
/* 0x0148, */ 0x0000000000000000UL,
|
||||
/* 0x0150, */ 0x00101D910000FFFFUL,
|
||||
/* 0x0158, */ 0x0000000000000000UL,
|
||||
/* 0x0160, */ 0x0010194A0000FFFFUL,
|
||||
/* 0x0168, */ 0x0000000000000000UL,
|
||||
/* 0x0170, */ 0x0000000000000000UL,
|
||||
/* 0x0178, */ 0x00100CA50000FFFFUL,
|
||||
/* 0x0180, */ 0x0000000000000000UL,
|
||||
/* 0x0188, */ 0x0000000000000000UL,
|
||||
/* 0x0190, */ 0x001037390000FFFFUL,
|
||||
/* 0x0198, */ 0x0000000000000000UL,
|
||||
/* 0x01a0, */ 0x0010194A0000FFFFUL,
|
||||
/* 0x01a8, */ 0x0000000000000000UL,
|
||||
/* 0x01b0, */ 0x0000000000000000UL,
|
||||
/* 0x01b8, */ 0x0000000000000000UL,
|
||||
/* 0x01c0, */ 0x000C04010000FFFFUL,
|
||||
/* 0x01c8, */ 0x000C04010000FFFFUL,
|
||||
/* 0x01d0, */ 0x0000000000000000UL,
|
||||
/* 0x01d8, */ 0x0000000000000000UL,
|
||||
/* 0x01e0, */ 0x0000000000000000UL,
|
||||
/* 0x01e8, */ 0x000C04020000FFFFUL,
|
||||
/* 0x01f0, */ 0x000C04090000FFFFUL,
|
||||
/* 0x01f8, */ 0x0000000000000000UL,
|
||||
/* 0x0200, */ 0x0000000000000000UL,
|
||||
/* 0x0208, */ 0x000C04090000FFFFUL,
|
||||
/* 0x0210, */ 0x000C04090000FFFFUL,
|
||||
/* 0x0218, */ 0x0000000000000000UL,
|
||||
/* 0x0220, */ 0x0000000000000000UL,
|
||||
/* 0x0228, */ 0x0000000000000000UL,
|
||||
/* 0x0230, */ 0x0000000000000000UL,
|
||||
/* 0x0238, */ 0x0000000000000000UL,
|
||||
/* 0x0240, */ 0x0000000000000000UL,
|
||||
/* 0x0248, */ 0x0000000000000000UL,
|
||||
/* 0x0250, */ 0x0000000000000000UL,
|
||||
/* 0x0258, */ 0x0000000000000000UL,
|
||||
/* 0x0260, */ 0x000C0C2A0000FFFFUL,
|
||||
/* 0x0268, */ 0x001410040000FFFFUL,
|
||||
/* 0x0270, */ 0x001404020000FFFFUL,
|
||||
/* 0x0278, */ 0x000C08110000FFFFUL,
|
||||
/* 0x0280, */ 0x0000000000000000UL,
|
||||
/* 0x0288, */ 0x0000000000000000UL,
|
||||
/* 0x0290, */ 0x001410040000FFFFUL,
|
||||
/* 0x0298, */ 0x001404020000FFFFUL,
|
||||
/* 0x02a0, */ 0x000C04090000FFFFUL,
|
||||
/* 0x02a8, */ 0x000C04090000FFFFUL,
|
||||
/* 0x02b0, */ 0x00140C090000FFFFUL,
|
||||
/* 0x02b8, */ 0x000C04020000FFFFUL,
|
||||
/* 0x02c0, */ 0x0000000000000000UL,
|
||||
/* 0x02c8, */ 0x0000000000000000UL,
|
||||
/* 0x02d0, */ 0x000C04090000FFFFUL,
|
||||
/* 0x02d8, */ 0x000C04090000FFFFUL,
|
||||
/* 0x02e0, */ 0x00140C090000FFFFUL,
|
||||
/* 0x02e8, */ 0x000C04020000FFFFUL,
|
||||
/* 0x02f0, */ 0x0000000000000000UL,
|
||||
/* 0x02f8, */ 0x0000000000000000UL,
|
||||
/* 0x0300, */ 0x0000000000000000UL,
|
||||
/* 0x0308, */ 0x0000000000000000UL,
|
||||
/* 0x0310, */ 0x0000000000000000UL,
|
||||
/* 0x0318, */ 0x0000000000000000UL,
|
||||
/* 0x0320, */ 0x0000000000000000UL,
|
||||
/* 0x0328, */ 0x0000000000000000UL,
|
||||
/* 0x0330, */ 0x0000000000000000UL,
|
||||
/* 0x0338, */ 0x0000000000000000UL,
|
||||
/* 0x0340, */ 0x0000000000000000UL,
|
||||
/* 0x0348, */ 0x0000000000000000UL,
|
||||
/* 0x0350, */ 0x0000000000000000UL,
|
||||
/* 0x0358, */ 0x0000000000000000UL,
|
||||
/* 0x0360, */ 0x0000000000000000UL,
|
||||
/* 0x0368, */ 0x0000000000000000UL,
|
||||
/* 0x0370, */ 0x000C04020000FFFFUL,
|
||||
/* 0x0378, */ 0x000C04020000FFFFUL,
|
||||
/* 0x0380, */ 0x000C04090000FFFFUL,
|
||||
/* 0x0388, */ 0x000C04090000FFFFUL,
|
||||
/* 0x0390, */ 0x0000000000000000UL,
|
||||
};
|
||||
|
||||
static uint64_t mstat_be[] = {
|
||||
/* 0x0000, */ 0x0000000000000000UL,
|
||||
/* 0x0008, */ 0x0000000000000000UL,
|
||||
/* 0x0010, */ 0x0000000000000000UL,
|
||||
/* 0x0018, */ 0x0000000000000000UL,
|
||||
/* 0x0020, */ 0x0000000000000000UL,
|
||||
/* 0x0028, */ 0x0012001005E03401UL,
|
||||
/* 0x0030, */ 0x0000000000000000UL,
|
||||
/* 0x0038, */ 0x0000000000000000UL,
|
||||
/* 0x0040, */ 0x0000000000000000UL,
|
||||
/* 0x0048, */ 0x0000000000000000UL,
|
||||
/* 0x0050, */ 0x0000000000000000UL,
|
||||
/* 0x0058, */ 0x0000000000000000UL,
|
||||
/* 0x0060, */ 0x0000000000000000UL,
|
||||
/* 0x0068, */ 0x0000000000000000UL,
|
||||
/* 0x0070, */ 0x0000000000000000UL,
|
||||
/* 0x0078, */ 0x0000000000000000UL,
|
||||
/* 0x0080, */ 0x0000000000000000UL,
|
||||
/* 0x0088, */ 0x0000000000000000UL,
|
||||
/* 0x0090, */ 0x0000000000000000UL,
|
||||
/* 0x0098, */ 0x0000000000000000UL,
|
||||
/* 0x00a0, */ 0x0000000000000000UL,
|
||||
/* 0x00a8, */ 0x0000000000000000UL,
|
||||
/* 0x00b0, */ 0x0000000000000000UL,
|
||||
/* 0x00b8, */ 0x0000000000000000UL,
|
||||
/* 0x00c0, */ 0x0000000000000000UL,
|
||||
/* 0x00c8, */ 0x0000000000000000UL,
|
||||
/* 0x00d0, */ 0x0000000000000000UL,
|
||||
/* 0x00d8, */ 0x0000000000000000UL,
|
||||
/* 0x00e0, */ 0x0000000000000000UL,
|
||||
/* 0x00e8, */ 0x0000000000000000UL,
|
||||
/* 0x00f0, */ 0x0000000000000000UL,
|
||||
/* 0x00f8, */ 0x0000000000000000UL,
|
||||
/* 0x0100, */ 0x0000000000000000UL,
|
||||
/* 0x0108, */ 0x0000000000000000UL,
|
||||
/* 0x0110, */ 0x0000000000000000UL,
|
||||
/* 0x0118, */ 0x0000000000000000UL,
|
||||
/* 0x0120, */ 0x0000000000000000UL,
|
||||
/* 0x0128, */ 0x0000000000000000UL,
|
||||
/* 0x0130, */ 0x0000000000000000UL,
|
||||
/* 0x0138, */ 0x0000000000000000UL,
|
||||
/* 0x0140, */ 0x0000000000000000UL,
|
||||
/* 0x0148, */ 0x0000000000000000UL,
|
||||
/* 0x0150, */ 0x0000000000000000UL,
|
||||
/* 0x0158, */ 0x0000000000000000UL,
|
||||
/* 0x0160, */ 0x0000000000000000UL,
|
||||
/* 0x0168, */ 0x0000000000000000UL,
|
||||
/* 0x0170, */ 0x0000000000000000UL,
|
||||
/* 0x0178, */ 0x0000000000000000UL,
|
||||
/* 0x0180, */ 0x0000000000000000UL,
|
||||
/* 0x0188, */ 0x0000000000000000UL,
|
||||
/* 0x0190, */ 0x0000000000000000UL,
|
||||
/* 0x0198, */ 0x0000000000000000UL,
|
||||
/* 0x01a0, */ 0x0000000000000000UL,
|
||||
/* 0x01a8, */ 0x0000000000000000UL,
|
||||
/* 0x01b0, */ 0x0000000000000000UL,
|
||||
/* 0x01b8, */ 0x0000000000000000UL,
|
||||
/* 0x01c0, */ 0x0021060005EFFC01UL,
|
||||
/* 0x01c8, */ 0x0021060005EFFC01UL,
|
||||
/* 0x01d0, */ 0x0000000000000000UL,
|
||||
/* 0x01d8, */ 0x0000000000000000UL,
|
||||
/* 0x01e0, */ 0x0000000000000000UL,
|
||||
/* 0x01e8, */ 0x0000000000000000UL,
|
||||
/* 0x01f0, */ 0x0021010005E79401UL,
|
||||
/* 0x01f8, */ 0x0000000000000000UL,
|
||||
/* 0x0200, */ 0x0000000000000000UL,
|
||||
/* 0x0208, */ 0x0000000000000000UL,
|
||||
/* 0x0210, */ 0x0021010005E79401UL,
|
||||
/* 0x0218, */ 0x0011010005E79401UL,
|
||||
/* 0x0220, */ 0x0011010005E79401UL,
|
||||
/* 0x0228, */ 0x0000000000000000UL,
|
||||
/* 0x0230, */ 0x0011010005E79401UL,
|
||||
/* 0x0238, */ 0x0011010005E79401UL,
|
||||
/* 0x0240, */ 0x0012010005E79401UL,
|
||||
/* 0x0248, */ 0x0011010005E79401UL,
|
||||
/* 0x0250, */ 0x0012010005E79401UL,
|
||||
/* 0x0258, */ 0x0011010005E79401UL,
|
||||
/* 0x0260, */ 0x0000000000000000UL,
|
||||
/* 0x0268, */ 0x0000000000000000UL,
|
||||
/* 0x0270, */ 0x0000000000000000UL,
|
||||
/* 0x0278, */ 0x0000000000000000UL,
|
||||
/* 0x0280, */ 0x0000000000000000UL,
|
||||
/* 0x0288, */ 0x0000000000000000UL,
|
||||
/* 0x0290, */ 0x0000000000000000UL,
|
||||
/* 0x0298, */ 0x0000000000000000UL,
|
||||
/* 0x02a0, */ 0x0000000000000000UL,
|
||||
/* 0x02a8, */ 0x0000000000000000UL,
|
||||
/* 0x02b0, */ 0x0000000000000000UL,
|
||||
/* 0x02b8, */ 0x0000000000000000UL,
|
||||
/* 0x02c0, */ 0x0000000000000000UL,
|
||||
/* 0x02c8, */ 0x0000000000000000UL,
|
||||
/* 0x02d0, */ 0x0000000000000000UL,
|
||||
/* 0x02d8, */ 0x0000000000000000UL,
|
||||
/* 0x02e0, */ 0x0000000000000000UL,
|
||||
/* 0x02e8, */ 0x0000000000000000UL,
|
||||
/* 0x02f0, */ 0x0011060005EFFC01UL,
|
||||
/* 0x02f8, */ 0x0011060005EFFC01UL,
|
||||
/* 0x0300, */ 0x0000000000000000UL,
|
||||
/* 0x0308, */ 0x0000000000000000UL,
|
||||
/* 0x0310, */ 0x0000000000000000UL,
|
||||
/* 0x0318, */ 0x0012001005E03401UL,
|
||||
/* 0x0320, */ 0x0000000000000000UL,
|
||||
/* 0x0328, */ 0x0000000000000000UL,
|
||||
/* 0x0330, */ 0x0000000000000000UL,
|
||||
/* 0x0338, */ 0x0000000000000000UL,
|
||||
/* 0x0340, */ 0x0000000000000000UL,
|
||||
/* 0x0348, */ 0x0000000000000000UL,
|
||||
/* 0x0350, */ 0x0000000000000000UL,
|
||||
/* 0x0358, */ 0x0012060005EFFC01UL,
|
||||
/* 0x0360, */ 0x0012060005EFFC01UL,
|
||||
/* 0x0368, */ 0x0012001005E03401UL,
|
||||
/* 0x0370, */ 0x0000000000000000UL,
|
||||
/* 0x0378, */ 0x0000000000000000UL,
|
||||
/* 0x0380, */ 0x0000000000000000UL,
|
||||
/* 0x0388, */ 0x0000000000000000UL,
|
||||
/* 0x0390, */ 0x0012001005E03401UL,
|
||||
};
|
241
drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10_qoswt195.h
Normal file
241
drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10_qoswt195.h
Normal file
|
@ -0,0 +1,241 @@
|
|||
/*
|
||||
* Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
static uint64_t qoswt_fix[] = {
|
||||
/* 0x0000, */ 0x0000000000000000UL,
|
||||
/* 0x0008, */ 0x0000000000000000UL,
|
||||
/* 0x0010, */ 0x0000000000000000UL,
|
||||
/* 0x0018, */ 0x0000000000000000UL,
|
||||
/* 0x0020, */ 0x0000000000000000UL,
|
||||
/* 0x0028, */ 0x0000000000000000UL,
|
||||
/* 0x0030, */ 0x001004320000C010UL,
|
||||
/* 0x0038, */ 0x001004320000C010UL,
|
||||
/* 0x0040, */ 0x00140C5D0000FFF0UL,
|
||||
/* 0x0048, */ 0x0000000000000000UL,
|
||||
/* 0x0050, */ 0x0000000000000000UL,
|
||||
/* 0x0058, */ 0x00140C940000C010UL,
|
||||
/* 0x0060, */ 0x00140C940000C010UL,
|
||||
/* 0x0068, */ 0x0000000000000000UL,
|
||||
/* 0x0070, */ 0x0000000000000000UL,
|
||||
/* 0x0078, */ 0x0000000000000000UL,
|
||||
/* 0x0080, */ 0x0000000000000000UL,
|
||||
/* 0x0088, */ 0x0014041F0000FFF0UL,
|
||||
/* 0x0090, */ 0x0000000000000000UL,
|
||||
/* 0x0098, */ 0x0000000000000000UL,
|
||||
/* 0x00a0, */ 0x0000000000000000UL,
|
||||
/* 0x00a8, */ 0x0000000000000000UL,
|
||||
/* 0x00b0, */ 0x0000000000000000UL,
|
||||
/* 0x00b8, */ 0x0000000000000000UL,
|
||||
/* 0x00c0, */ 0x0000000000000000UL,
|
||||
/* 0x00c8, */ 0x0000000000000000UL,
|
||||
/* 0x00d0, */ 0x0000000000000000UL,
|
||||
/* 0x00d8, */ 0x0000000000000000UL,
|
||||
/* 0x00e0, */ 0x0000000000000000UL,
|
||||
/* 0x00e8, */ 0x0000000000000000UL,
|
||||
/* 0x00f0, */ 0x0000000000000000UL,
|
||||
/* 0x00f8, */ 0x0000000000000000UL,
|
||||
/* 0x0100, */ 0x0000000000000000UL,
|
||||
/* 0x0108, */ 0x0000000000000000UL,
|
||||
/* 0x0110, */ 0x0000000000000000UL,
|
||||
/* 0x0118, */ 0x0000000000000000UL,
|
||||
/* 0x0120, */ 0x0000000000000000UL,
|
||||
/* 0x0128, */ 0x0000000000000000UL,
|
||||
/* 0x0130, */ 0x0000000000000000UL,
|
||||
/* 0x0138, */ 0x0000000000000000UL,
|
||||
/* 0x0140, */ 0x0000000000000000UL,
|
||||
/* 0x0148, */ 0x0000000000000000UL,
|
||||
/* 0x0150, */ 0x0000000000000000UL,
|
||||
/* 0x0158, */ 0x0000000000000000UL,
|
||||
/* 0x0160, */ 0x0000000000000000UL,
|
||||
/* 0x0168, */ 0x0000000000000000UL,
|
||||
/* 0x0170, */ 0x0000000000000000UL,
|
||||
/* 0x0178, */ 0x0000000000000000UL,
|
||||
/* 0x0180, */ 0x0000000000000000UL,
|
||||
/* 0x0188, */ 0x0000000000000000UL,
|
||||
/* 0x0190, */ 0x0000000000000000UL,
|
||||
/* 0x0198, */ 0x0000000000000000UL,
|
||||
/* 0x01a0, */ 0x0000000000000000UL,
|
||||
/* 0x01a8, */ 0x0000000000000000UL,
|
||||
/* 0x01b0, */ 0x0000000000000000UL,
|
||||
/* 0x01b8, */ 0x0000000000000000UL,
|
||||
/* 0x01c0, */ 0x0000000000000000UL,
|
||||
/* 0x01c8, */ 0x0000000000000000UL,
|
||||
/* 0x01d0, */ 0x0000000000000000UL,
|
||||
/* 0x01d8, */ 0x0000000000000000UL,
|
||||
/* 0x01e0, */ 0x0000000000000000UL,
|
||||
/* 0x01e8, */ 0x0000000000000000UL,
|
||||
/* 0x01f0, */ 0x0000000000000000UL,
|
||||
/* 0x01f8, */ 0x0000000000000000UL,
|
||||
/* 0x0200, */ 0x0000000000000000UL,
|
||||
/* 0x0208, */ 0x0000000000000000UL,
|
||||
/* 0x0210, */ 0x0000000000000000UL,
|
||||
/* 0x0218, */ 0x0000000000000000UL,
|
||||
/* 0x0220, */ 0x0000000000000000UL,
|
||||
/* 0x0228, */ 0x0000000000000000UL,
|
||||
/* 0x0230, */ 0x0000000000000000UL,
|
||||
/* 0x0238, */ 0x0000000000000000UL,
|
||||
/* 0x0240, */ 0x0000000000000000UL,
|
||||
/* 0x0248, */ 0x0000000000000000UL,
|
||||
/* 0x0250, */ 0x0000000000000000UL,
|
||||
/* 0x0258, */ 0x0000000000000000UL,
|
||||
/* 0x0260, */ 0x000C08150000FFF0UL,
|
||||
/* 0x0268, */ 0x001408020000FFF0UL,
|
||||
/* 0x0270, */ 0x001404010000FFF0UL,
|
||||
/* 0x0278, */ 0x000C04090000FFF0UL,
|
||||
/* 0x0280, */ 0x0000000000000000UL,
|
||||
/* 0x0288, */ 0x0000000000000000UL,
|
||||
/* 0x0290, */ 0x001408020000FFF0UL,
|
||||
/* 0x0298, */ 0x001404010000FFF0UL,
|
||||
/* 0x02a0, */ 0x0000000000000000UL,
|
||||
/* 0x02a8, */ 0x0000000000000000UL,
|
||||
/* 0x02b0, */ 0x0000000000000000UL,
|
||||
/* 0x02b8, */ 0x0000000000000000UL,
|
||||
/* 0x02c0, */ 0x0000000000000000UL,
|
||||
/* 0x02c8, */ 0x0000000000000000UL,
|
||||
/* 0x02d0, */ 0x0000000000000000UL,
|
||||
/* 0x02d8, */ 0x0000000000000000UL,
|
||||
/* 0x02e0, */ 0x0000000000000000UL,
|
||||
/* 0x02e8, */ 0x0000000000000000UL,
|
||||
/* 0x02f0, */ 0x0000000000000000UL,
|
||||
/* 0x02f8, */ 0x0000000000000000UL,
|
||||
/* 0x0300, */ 0x0000000000000000UL,
|
||||
/* 0x0308, */ 0x0000000000000000UL,
|
||||
/* 0x0310, */ 0x0000000000000000UL,
|
||||
/* 0x0318, */ 0x0000000000000000UL,
|
||||
/* 0x0320, */ 0x0000000000000000UL,
|
||||
/* 0x0328, */ 0x0000000000000000UL,
|
||||
/* 0x0330, */ 0x0000000000000000UL,
|
||||
/* 0x0338, */ 0x0000000000000000UL,
|
||||
/* 0x0340, */ 0x0000000000000000UL,
|
||||
/* 0x0348, */ 0x0000000000000000UL,
|
||||
/* 0x0350, */ 0x0000000000000000UL,
|
||||
/* 0x0358, */ 0x0000000000000000UL,
|
||||
/* 0x0360, */ 0x0000000000000000UL,
|
||||
/* 0x0368, */ 0x0000000000000000UL,
|
||||
/* 0x0370, */ 0x0000000000000000UL,
|
||||
/* 0x0378, */ 0x0000000000000000UL,
|
||||
/* 0x0380, */ 0x0000000000000000UL,
|
||||
/* 0x0388, */ 0x0000000000000000UL,
|
||||
/* 0x0390, */ 0x0000000000000000UL,
|
||||
};
|
||||
|
||||
static uint64_t qoswt_be[] = {
|
||||
/* 0x0000, */ 0x0000000000000000UL,
|
||||
/* 0x0008, */ 0x0000000000000000UL,
|
||||
/* 0x0010, */ 0x0000000000000000UL,
|
||||
/* 0x0018, */ 0x0000000000000000UL,
|
||||
/* 0x0020, */ 0x0000000000000000UL,
|
||||
/* 0x0028, */ 0x0000000000000000UL,
|
||||
/* 0x0030, */ 0x0000000000000000UL,
|
||||
/* 0x0038, */ 0x0000000000000000UL,
|
||||
/* 0x0040, */ 0x0000000000000000UL,
|
||||
/* 0x0048, */ 0x0000000000000000UL,
|
||||
/* 0x0050, */ 0x0000000000000000UL,
|
||||
/* 0x0058, */ 0x0000000000000000UL,
|
||||
/* 0x0060, */ 0x0000000000000000UL,
|
||||
/* 0x0068, */ 0x0000000000000000UL,
|
||||
/* 0x0070, */ 0x0000000000000000UL,
|
||||
/* 0x0078, */ 0x0000000000000000UL,
|
||||
/* 0x0080, */ 0x0000000000000000UL,
|
||||
/* 0x0088, */ 0x0000000000000000UL,
|
||||
/* 0x0090, */ 0x0000000000000000UL,
|
||||
/* 0x0098, */ 0x0000000000000000UL,
|
||||
/* 0x00a0, */ 0x0000000000000000UL,
|
||||
/* 0x00a8, */ 0x0000000000000000UL,
|
||||
/* 0x00b0, */ 0x0000000000000000UL,
|
||||
/* 0x00b8, */ 0x0000000000000000UL,
|
||||
/* 0x00c0, */ 0x0000000000000000UL,
|
||||
/* 0x00c8, */ 0x0000000000000000UL,
|
||||
/* 0x00d0, */ 0x0000000000000000UL,
|
||||
/* 0x00d8, */ 0x0000000000000000UL,
|
||||
/* 0x00e0, */ 0x0000000000000000UL,
|
||||
/* 0x00e8, */ 0x0000000000000000UL,
|
||||
/* 0x00f0, */ 0x0000000000000000UL,
|
||||
/* 0x00f8, */ 0x0000000000000000UL,
|
||||
/* 0x0100, */ 0x0000000000000000UL,
|
||||
/* 0x0108, */ 0x0000000000000000UL,
|
||||
/* 0x0110, */ 0x0000000000000000UL,
|
||||
/* 0x0118, */ 0x0000000000000000UL,
|
||||
/* 0x0120, */ 0x0000000000000000UL,
|
||||
/* 0x0128, */ 0x0000000000000000UL,
|
||||
/* 0x0130, */ 0x0000000000000000UL,
|
||||
/* 0x0138, */ 0x0000000000000000UL,
|
||||
/* 0x0140, */ 0x0000000000000000UL,
|
||||
/* 0x0148, */ 0x0000000000000000UL,
|
||||
/* 0x0150, */ 0x0000000000000000UL,
|
||||
/* 0x0158, */ 0x0000000000000000UL,
|
||||
/* 0x0160, */ 0x0000000000000000UL,
|
||||
/* 0x0168, */ 0x0000000000000000UL,
|
||||
/* 0x0170, */ 0x0000000000000000UL,
|
||||
/* 0x0178, */ 0x0000000000000000UL,
|
||||
/* 0x0180, */ 0x0000000000000000UL,
|
||||
/* 0x0188, */ 0x0000000000000000UL,
|
||||
/* 0x0190, */ 0x0000000000000000UL,
|
||||
/* 0x0198, */ 0x0000000000000000UL,
|
||||
/* 0x01a0, */ 0x0000000000000000UL,
|
||||
/* 0x01a8, */ 0x0000000000000000UL,
|
||||
/* 0x01b0, */ 0x0000000000000000UL,
|
||||
/* 0x01b8, */ 0x0000000000000000UL,
|
||||
/* 0x01c0, */ 0x0000000000000000UL,
|
||||
/* 0x01c8, */ 0x0000000000000000UL,
|
||||
/* 0x01d0, */ 0x0000000000000000UL,
|
||||
/* 0x01d8, */ 0x0000000000000000UL,
|
||||
/* 0x01e0, */ 0x0000000000000000UL,
|
||||
/* 0x01e8, */ 0x0000000000000000UL,
|
||||
/* 0x01f0, */ 0x0000000000000000UL,
|
||||
/* 0x01f8, */ 0x0000000000000000UL,
|
||||
/* 0x0200, */ 0x0000000000000000UL,
|
||||
/* 0x0208, */ 0x0000000000000000UL,
|
||||
/* 0x0210, */ 0x0000000000000000UL,
|
||||
/* 0x0218, */ 0x0000000000000000UL,
|
||||
/* 0x0220, */ 0x0000000000000000UL,
|
||||
/* 0x0228, */ 0x0000000000000000UL,
|
||||
/* 0x0230, */ 0x0000000000000000UL,
|
||||
/* 0x0238, */ 0x0000000000000000UL,
|
||||
/* 0x0240, */ 0x0000000000000000UL,
|
||||
/* 0x0248, */ 0x0000000000000000UL,
|
||||
/* 0x0250, */ 0x0000000000000000UL,
|
||||
/* 0x0258, */ 0x0000000000000000UL,
|
||||
/* 0x0260, */ 0x0000000000000000UL,
|
||||
/* 0x0268, */ 0x0000000000000000UL,
|
||||
/* 0x0270, */ 0x0000000000000000UL,
|
||||
/* 0x0278, */ 0x0000000000000000UL,
|
||||
/* 0x0280, */ 0x0000000000000000UL,
|
||||
/* 0x0288, */ 0x0000000000000000UL,
|
||||
/* 0x0290, */ 0x0000000000000000UL,
|
||||
/* 0x0298, */ 0x0000000000000000UL,
|
||||
/* 0x02a0, */ 0x0000000000000000UL,
|
||||
/* 0x02a8, */ 0x0000000000000000UL,
|
||||
/* 0x02b0, */ 0x0000000000000000UL,
|
||||
/* 0x02b8, */ 0x0000000000000000UL,
|
||||
/* 0x02c0, */ 0x0000000000000000UL,
|
||||
/* 0x02c8, */ 0x0000000000000000UL,
|
||||
/* 0x02d0, */ 0x0000000000000000UL,
|
||||
/* 0x02d8, */ 0x0000000000000000UL,
|
||||
/* 0x02e0, */ 0x0000000000000000UL,
|
||||
/* 0x02e8, */ 0x0000000000000000UL,
|
||||
/* 0x02f0, */ 0x0000000000000000UL,
|
||||
/* 0x02f8, */ 0x0000000000000000UL,
|
||||
/* 0x0300, */ 0x0000000000000000UL,
|
||||
/* 0x0308, */ 0x0000000000000000UL,
|
||||
/* 0x0310, */ 0x0000000000000000UL,
|
||||
/* 0x0318, */ 0x0000000000000000UL,
|
||||
/* 0x0320, */ 0x0000000000000000UL,
|
||||
/* 0x0328, */ 0x0000000000000000UL,
|
||||
/* 0x0330, */ 0x0000000000000000UL,
|
||||
/* 0x0338, */ 0x0000000000000000UL,
|
||||
/* 0x0340, */ 0x0000000000000000UL,
|
||||
/* 0x0348, */ 0x0000000000000000UL,
|
||||
/* 0x0350, */ 0x0000000000000000UL,
|
||||
/* 0x0358, */ 0x0000000000000000UL,
|
||||
/* 0x0360, */ 0x0000000000000000UL,
|
||||
/* 0x0368, */ 0x0000000000000000UL,
|
||||
/* 0x0370, */ 0x0000000000000000UL,
|
||||
/* 0x0378, */ 0x0000000000000000UL,
|
||||
/* 0x0380, */ 0x0000000000000000UL,
|
||||
/* 0x0388, */ 0x0000000000000000UL,
|
||||
/* 0x0390, */ 0x0000000000000000UL,
|
||||
};
|
241
drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10_qoswt390.h
Normal file
241
drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10_qoswt390.h
Normal file
|
@ -0,0 +1,241 @@
|
|||
/*
|
||||
* Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
static uint64_t qoswt_fix[] = {
|
||||
/* 0x0000, */ 0x0000000000000000UL,
|
||||
/* 0x0008, */ 0x0000000000000000UL,
|
||||
/* 0x0010, */ 0x0000000000000000UL,
|
||||
/* 0x0018, */ 0x0000000000000000UL,
|
||||
/* 0x0020, */ 0x0000000000000000UL,
|
||||
/* 0x0028, */ 0x0000000000000000UL,
|
||||
/* 0x0030, */ 0x001008630000C010UL,
|
||||
/* 0x0038, */ 0x001008630000C010UL,
|
||||
/* 0x0040, */ 0x001418BA0000FFF0UL,
|
||||
/* 0x0048, */ 0x0000000000000000UL,
|
||||
/* 0x0050, */ 0x0000000000000000UL,
|
||||
/* 0x0058, */ 0x001415270000C010UL,
|
||||
/* 0x0060, */ 0x001415270000C010UL,
|
||||
/* 0x0068, */ 0x0000000000000000UL,
|
||||
/* 0x0070, */ 0x0000000000000000UL,
|
||||
/* 0x0078, */ 0x0000000000000000UL,
|
||||
/* 0x0080, */ 0x0000000000000000UL,
|
||||
/* 0x0088, */ 0x0014083E0000FFF0UL,
|
||||
/* 0x0090, */ 0x0000000000000000UL,
|
||||
/* 0x0098, */ 0x0000000000000000UL,
|
||||
/* 0x00a0, */ 0x0000000000000000UL,
|
||||
/* 0x00a8, */ 0x0000000000000000UL,
|
||||
/* 0x00b0, */ 0x0000000000000000UL,
|
||||
/* 0x00b8, */ 0x0000000000000000UL,
|
||||
/* 0x00c0, */ 0x0000000000000000UL,
|
||||
/* 0x00c8, */ 0x0000000000000000UL,
|
||||
/* 0x00d0, */ 0x0000000000000000UL,
|
||||
/* 0x00d8, */ 0x0000000000000000UL,
|
||||
/* 0x00e0, */ 0x0000000000000000UL,
|
||||
/* 0x00e8, */ 0x0000000000000000UL,
|
||||
/* 0x00f0, */ 0x0000000000000000UL,
|
||||
/* 0x00f8, */ 0x0000000000000000UL,
|
||||
/* 0x0100, */ 0x0000000000000000UL,
|
||||
/* 0x0108, */ 0x0000000000000000UL,
|
||||
/* 0x0110, */ 0x0000000000000000UL,
|
||||
/* 0x0118, */ 0x0000000000000000UL,
|
||||
/* 0x0120, */ 0x0000000000000000UL,
|
||||
/* 0x0128, */ 0x0000000000000000UL,
|
||||
/* 0x0130, */ 0x0000000000000000UL,
|
||||
/* 0x0138, */ 0x0000000000000000UL,
|
||||
/* 0x0140, */ 0x0000000000000000UL,
|
||||
/* 0x0148, */ 0x0000000000000000UL,
|
||||
/* 0x0150, */ 0x0000000000000000UL,
|
||||
/* 0x0158, */ 0x0000000000000000UL,
|
||||
/* 0x0160, */ 0x0000000000000000UL,
|
||||
/* 0x0168, */ 0x0000000000000000UL,
|
||||
/* 0x0170, */ 0x0000000000000000UL,
|
||||
/* 0x0178, */ 0x0000000000000000UL,
|
||||
/* 0x0180, */ 0x0000000000000000UL,
|
||||
/* 0x0188, */ 0x0000000000000000UL,
|
||||
/* 0x0190, */ 0x0000000000000000UL,
|
||||
/* 0x0198, */ 0x0000000000000000UL,
|
||||
/* 0x01a0, */ 0x0000000000000000UL,
|
||||
/* 0x01a8, */ 0x0000000000000000UL,
|
||||
/* 0x01b0, */ 0x0000000000000000UL,
|
||||
/* 0x01b8, */ 0x0000000000000000UL,
|
||||
/* 0x01c0, */ 0x0000000000000000UL,
|
||||
/* 0x01c8, */ 0x0000000000000000UL,
|
||||
/* 0x01d0, */ 0x0000000000000000UL,
|
||||
/* 0x01d8, */ 0x0000000000000000UL,
|
||||
/* 0x01e0, */ 0x0000000000000000UL,
|
||||
/* 0x01e8, */ 0x0000000000000000UL,
|
||||
/* 0x01f0, */ 0x0000000000000000UL,
|
||||
/* 0x01f8, */ 0x0000000000000000UL,
|
||||
/* 0x0200, */ 0x0000000000000000UL,
|
||||
/* 0x0208, */ 0x0000000000000000UL,
|
||||
/* 0x0210, */ 0x0000000000000000UL,
|
||||
/* 0x0218, */ 0x0000000000000000UL,
|
||||
/* 0x0220, */ 0x0000000000000000UL,
|
||||
/* 0x0228, */ 0x0000000000000000UL,
|
||||
/* 0x0230, */ 0x0000000000000000UL,
|
||||
/* 0x0238, */ 0x0000000000000000UL,
|
||||
/* 0x0240, */ 0x0000000000000000UL,
|
||||
/* 0x0248, */ 0x0000000000000000UL,
|
||||
/* 0x0250, */ 0x0000000000000000UL,
|
||||
/* 0x0258, */ 0x0000000000000000UL,
|
||||
/* 0x0260, */ 0x000C0C2A0000FFF0UL,
|
||||
/* 0x0268, */ 0x001410040000FFF0UL,
|
||||
/* 0x0270, */ 0x001404020000FFF0UL,
|
||||
/* 0x0278, */ 0x000C08110000FFF0UL,
|
||||
/* 0x0280, */ 0x0000000000000000UL,
|
||||
/* 0x0288, */ 0x0000000000000000UL,
|
||||
/* 0x0290, */ 0x001410040000FFF0UL,
|
||||
/* 0x0298, */ 0x001404020000FFF0UL,
|
||||
/* 0x02a0, */ 0x0000000000000000UL,
|
||||
/* 0x02a8, */ 0x0000000000000000UL,
|
||||
/* 0x02b0, */ 0x0000000000000000UL,
|
||||
/* 0x02b8, */ 0x0000000000000000UL,
|
||||
/* 0x02c0, */ 0x0000000000000000UL,
|
||||
/* 0x02c8, */ 0x0000000000000000UL,
|
||||
/* 0x02d0, */ 0x0000000000000000UL,
|
||||
/* 0x02d8, */ 0x0000000000000000UL,
|
||||
/* 0x02e0, */ 0x0000000000000000UL,
|
||||
/* 0x02e8, */ 0x0000000000000000UL,
|
||||
/* 0x02f0, */ 0x0000000000000000UL,
|
||||
/* 0x02f8, */ 0x0000000000000000UL,
|
||||
/* 0x0300, */ 0x0000000000000000UL,
|
||||
/* 0x0308, */ 0x0000000000000000UL,
|
||||
/* 0x0310, */ 0x0000000000000000UL,
|
||||
/* 0x0318, */ 0x0000000000000000UL,
|
||||
/* 0x0320, */ 0x0000000000000000UL,
|
||||
/* 0x0328, */ 0x0000000000000000UL,
|
||||
/* 0x0330, */ 0x0000000000000000UL,
|
||||
/* 0x0338, */ 0x0000000000000000UL,
|
||||
/* 0x0340, */ 0x0000000000000000UL,
|
||||
/* 0x0348, */ 0x0000000000000000UL,
|
||||
/* 0x0350, */ 0x0000000000000000UL,
|
||||
/* 0x0358, */ 0x0000000000000000UL,
|
||||
/* 0x0360, */ 0x0000000000000000UL,
|
||||
/* 0x0368, */ 0x0000000000000000UL,
|
||||
/* 0x0370, */ 0x0000000000000000UL,
|
||||
/* 0x0378, */ 0x0000000000000000UL,
|
||||
/* 0x0380, */ 0x0000000000000000UL,
|
||||
/* 0x0388, */ 0x0000000000000000UL,
|
||||
/* 0x0390, */ 0x0000000000000000UL,
|
||||
};
|
||||
|
||||
static uint64_t qoswt_be[] = {
|
||||
/* 0x0000, */ 0x0000000000000000UL,
|
||||
/* 0x0008, */ 0x0000000000000000UL,
|
||||
/* 0x0010, */ 0x0000000000000000UL,
|
||||
/* 0x0018, */ 0x0000000000000000UL,
|
||||
/* 0x0020, */ 0x0000000000000000UL,
|
||||
/* 0x0028, */ 0x0000000000000000UL,
|
||||
/* 0x0030, */ 0x0000000000000000UL,
|
||||
/* 0x0038, */ 0x0000000000000000UL,
|
||||
/* 0x0040, */ 0x0000000000000000UL,
|
||||
/* 0x0048, */ 0x0000000000000000UL,
|
||||
/* 0x0050, */ 0x0000000000000000UL,
|
||||
/* 0x0058, */ 0x0000000000000000UL,
|
||||
/* 0x0060, */ 0x0000000000000000UL,
|
||||
/* 0x0068, */ 0x0000000000000000UL,
|
||||
/* 0x0070, */ 0x0000000000000000UL,
|
||||
/* 0x0078, */ 0x0000000000000000UL,
|
||||
/* 0x0080, */ 0x0000000000000000UL,
|
||||
/* 0x0088, */ 0x0000000000000000UL,
|
||||
/* 0x0090, */ 0x0000000000000000UL,
|
||||
/* 0x0098, */ 0x0000000000000000UL,
|
||||
/* 0x00a0, */ 0x0000000000000000UL,
|
||||
/* 0x00a8, */ 0x0000000000000000UL,
|
||||
/* 0x00b0, */ 0x0000000000000000UL,
|
||||
/* 0x00b8, */ 0x0000000000000000UL,
|
||||
/* 0x00c0, */ 0x0000000000000000UL,
|
||||
/* 0x00c8, */ 0x0000000000000000UL,
|
||||
/* 0x00d0, */ 0x0000000000000000UL,
|
||||
/* 0x00d8, */ 0x0000000000000000UL,
|
||||
/* 0x00e0, */ 0x0000000000000000UL,
|
||||
/* 0x00e8, */ 0x0000000000000000UL,
|
||||
/* 0x00f0, */ 0x0000000000000000UL,
|
||||
/* 0x00f8, */ 0x0000000000000000UL,
|
||||
/* 0x0100, */ 0x0000000000000000UL,
|
||||
/* 0x0108, */ 0x0000000000000000UL,
|
||||
/* 0x0110, */ 0x0000000000000000UL,
|
||||
/* 0x0118, */ 0x0000000000000000UL,
|
||||
/* 0x0120, */ 0x0000000000000000UL,
|
||||
/* 0x0128, */ 0x0000000000000000UL,
|
||||
/* 0x0130, */ 0x0000000000000000UL,
|
||||
/* 0x0138, */ 0x0000000000000000UL,
|
||||
/* 0x0140, */ 0x0000000000000000UL,
|
||||
/* 0x0148, */ 0x0000000000000000UL,
|
||||
/* 0x0150, */ 0x0000000000000000UL,
|
||||
/* 0x0158, */ 0x0000000000000000UL,
|
||||
/* 0x0160, */ 0x0000000000000000UL,
|
||||
/* 0x0168, */ 0x0000000000000000UL,
|
||||
/* 0x0170, */ 0x0000000000000000UL,
|
||||
/* 0x0178, */ 0x0000000000000000UL,
|
||||
/* 0x0180, */ 0x0000000000000000UL,
|
||||
/* 0x0188, */ 0x0000000000000000UL,
|
||||
/* 0x0190, */ 0x0000000000000000UL,
|
||||
/* 0x0198, */ 0x0000000000000000UL,
|
||||
/* 0x01a0, */ 0x0000000000000000UL,
|
||||
/* 0x01a8, */ 0x0000000000000000UL,
|
||||
/* 0x01b0, */ 0x0000000000000000UL,
|
||||
/* 0x01b8, */ 0x0000000000000000UL,
|
||||
/* 0x01c0, */ 0x0000000000000000UL,
|
||||
/* 0x01c8, */ 0x0000000000000000UL,
|
||||
/* 0x01d0, */ 0x0000000000000000UL,
|
||||
/* 0x01d8, */ 0x0000000000000000UL,
|
||||
/* 0x01e0, */ 0x0000000000000000UL,
|
||||
/* 0x01e8, */ 0x0000000000000000UL,
|
||||
/* 0x01f0, */ 0x0000000000000000UL,
|
||||
/* 0x01f8, */ 0x0000000000000000UL,
|
||||
/* 0x0200, */ 0x0000000000000000UL,
|
||||
/* 0x0208, */ 0x0000000000000000UL,
|
||||
/* 0x0210, */ 0x0000000000000000UL,
|
||||
/* 0x0218, */ 0x0000000000000000UL,
|
||||
/* 0x0220, */ 0x0000000000000000UL,
|
||||
/* 0x0228, */ 0x0000000000000000UL,
|
||||
/* 0x0230, */ 0x0000000000000000UL,
|
||||
/* 0x0238, */ 0x0000000000000000UL,
|
||||
/* 0x0240, */ 0x0000000000000000UL,
|
||||
/* 0x0248, */ 0x0000000000000000UL,
|
||||
/* 0x0250, */ 0x0000000000000000UL,
|
||||
/* 0x0258, */ 0x0000000000000000UL,
|
||||
/* 0x0260, */ 0x0000000000000000UL,
|
||||
/* 0x0268, */ 0x0000000000000000UL,
|
||||
/* 0x0270, */ 0x0000000000000000UL,
|
||||
/* 0x0278, */ 0x0000000000000000UL,
|
||||
/* 0x0280, */ 0x0000000000000000UL,
|
||||
/* 0x0288, */ 0x0000000000000000UL,
|
||||
/* 0x0290, */ 0x0000000000000000UL,
|
||||
/* 0x0298, */ 0x0000000000000000UL,
|
||||
/* 0x02a0, */ 0x0000000000000000UL,
|
||||
/* 0x02a8, */ 0x0000000000000000UL,
|
||||
/* 0x02b0, */ 0x0000000000000000UL,
|
||||
/* 0x02b8, */ 0x0000000000000000UL,
|
||||
/* 0x02c0, */ 0x0000000000000000UL,
|
||||
/* 0x02c8, */ 0x0000000000000000UL,
|
||||
/* 0x02d0, */ 0x0000000000000000UL,
|
||||
/* 0x02d8, */ 0x0000000000000000UL,
|
||||
/* 0x02e0, */ 0x0000000000000000UL,
|
||||
/* 0x02e8, */ 0x0000000000000000UL,
|
||||
/* 0x02f0, */ 0x0000000000000000UL,
|
||||
/* 0x02f8, */ 0x0000000000000000UL,
|
||||
/* 0x0300, */ 0x0000000000000000UL,
|
||||
/* 0x0308, */ 0x0000000000000000UL,
|
||||
/* 0x0310, */ 0x0000000000000000UL,
|
||||
/* 0x0318, */ 0x0000000000000000UL,
|
||||
/* 0x0320, */ 0x0000000000000000UL,
|
||||
/* 0x0328, */ 0x0000000000000000UL,
|
||||
/* 0x0330, */ 0x0000000000000000UL,
|
||||
/* 0x0338, */ 0x0000000000000000UL,
|
||||
/* 0x0340, */ 0x0000000000000000UL,
|
||||
/* 0x0348, */ 0x0000000000000000UL,
|
||||
/* 0x0350, */ 0x0000000000000000UL,
|
||||
/* 0x0358, */ 0x0000000000000000UL,
|
||||
/* 0x0360, */ 0x0000000000000000UL,
|
||||
/* 0x0368, */ 0x0000000000000000UL,
|
||||
/* 0x0370, */ 0x0000000000000000UL,
|
||||
/* 0x0378, */ 0x0000000000000000UL,
|
||||
/* 0x0380, */ 0x0000000000000000UL,
|
||||
/* 0x0388, */ 0x0000000000000000UL,
|
||||
/* 0x0390, */ 0x0000000000000000UL,
|
||||
};
|
87
drivers/staging/renesas/rcar/qos/qos.mk
Normal file
87
drivers/staging/renesas/rcar/qos/qos.mk
Normal file
|
@ -0,0 +1,87 @@
|
|||
#
|
||||
# Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
|
||||
ifeq (${RCAR_LSI},${RCAR_AUTO})
|
||||
# E3, H3N not available for LSI_AUTO
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v10.c
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v11.c
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20.c
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30.c
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v10.c
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.c
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
|
||||
else ifdef RCAR_LSI_CUT_COMPAT
|
||||
ifeq (${RCAR_LSI},${RCAR_H3})
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v10.c
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v11.c
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20.c
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30.c
|
||||
endif
|
||||
ifeq (${RCAR_LSI},${RCAR_H3N})
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30.c
|
||||
endif
|
||||
ifeq (${RCAR_LSI},${RCAR_M3})
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v10.c
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.c
|
||||
endif
|
||||
ifeq (${RCAR_LSI},${RCAR_M3N})
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
|
||||
endif
|
||||
ifeq (${RCAR_LSI},${RCAR_E3})
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10.c
|
||||
endif
|
||||
else
|
||||
ifeq (${RCAR_LSI},${RCAR_H3})
|
||||
ifeq (${LSI_CUT},10)
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v10.c
|
||||
else ifeq (${LSI_CUT},11)
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v11.c
|
||||
else ifeq (${LSI_CUT},20)
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20.c
|
||||
else ifeq (${LSI_CUT},30)
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30.c
|
||||
else
|
||||
# LSI_CUT 30 or later
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30.c
|
||||
endif
|
||||
endif
|
||||
ifeq (${RCAR_LSI},${RCAR_H3N})
|
||||
ifeq (${LSI_CUT},30)
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30.c
|
||||
else
|
||||
# LSI_CUT 30 or later
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30.c
|
||||
endif
|
||||
endif
|
||||
ifeq (${RCAR_LSI},${RCAR_M3})
|
||||
ifeq (${LSI_CUT},10)
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v10.c
|
||||
else ifeq (${LSI_CUT},11)
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.c
|
||||
else
|
||||
# LSI_CUT 11 or later
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.c
|
||||
endif
|
||||
endif
|
||||
ifeq (${RCAR_LSI},${RCAR_M3N})
|
||||
ifeq (${LSI_CUT},10)
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
|
||||
else
|
||||
# LSI_CUT 10 or later
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
|
||||
endif
|
||||
endif
|
||||
ifeq (${RCAR_LSI},${RCAR_E3})
|
||||
ifeq (${LSI_CUT},10)
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10.c
|
||||
else
|
||||
# LSI_CUT 10 or later
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10.c
|
||||
endif
|
||||
endif
|
||||
endif
|
||||
|
||||
BL2_SOURCES += drivers/staging/renesas/rcar/qos/qos_init.c
|
113
drivers/staging/renesas/rcar/qos/qos_common.h
Normal file
113
drivers/staging/renesas/rcar/qos/qos_common.h
Normal file
|
@ -0,0 +1,113 @@
|
|||
/*
|
||||
* Copyright (c) 2017-2018, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef QOS_COMMON_H_
|
||||
#define QOS_COMMON_H_
|
||||
|
||||
#define RCAR_REF_DEFAULT (0U)
|
||||
|
||||
#if (RCAR_LSI == RCAR_E3)
|
||||
/* define used for E3 */
|
||||
#if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 3.9usec */
|
||||
#define SUB_SLOT_CYCLE_E3 (0xAFU) /* 175 */
|
||||
#else /* REF 7.8usec */
|
||||
#define SUB_SLOT_CYCLE_E3 (0x15EU) /* 350 */
|
||||
#endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
|
||||
|
||||
#define OPERATING_FREQ_E3 (266U) /* MHz */
|
||||
#define SL_INIT_SSLOTCLK_E3 (SUB_SLOT_CYCLE_E3 -1U)
|
||||
#define QOSWT_WTSET0_CYCLE_E3 ((SUB_SLOT_CYCLE_E3 * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ_E3) /* unit:ns */
|
||||
#endif
|
||||
|
||||
#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N)
|
||||
/* define used for M3N */
|
||||
#if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 1.95usec */
|
||||
#define SUB_SLOT_CYCLE_M3N (0x84U) /* 132 */
|
||||
#else /* REF 3.9usec */
|
||||
#define SUB_SLOT_CYCLE_M3N (0x108U) /* 264 */
|
||||
#endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
|
||||
|
||||
#define SL_INIT_SSLOTCLK_M3N (SUB_SLOT_CYCLE_M3N -1U)
|
||||
#define QOSWT_WTSET0_CYCLE_M3N ((SUB_SLOT_CYCLE_M3N * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ) /* unit:ns */
|
||||
#endif
|
||||
|
||||
#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_H3)
|
||||
/* define used for H3 */
|
||||
#if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 1.95usec */
|
||||
#define SUB_SLOT_CYCLE_H3_20 (0x84U) /* 132 */
|
||||
#else /* REF 3.9usec */
|
||||
#define SUB_SLOT_CYCLE_H3_20 (0x108U) /* 264 */
|
||||
#endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
|
||||
|
||||
#define SL_INIT_SSLOTCLK_H3_20 (SUB_SLOT_CYCLE_H3_20 -1U)
|
||||
#define QOSWT_WTSET0_CYCLE_H3_20 ((SUB_SLOT_CYCLE_H3_20 * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ) /* unit:ns */
|
||||
|
||||
/* define used for H3 Cut 30 */
|
||||
#define SUB_SLOT_CYCLE_H3_30 (SUB_SLOT_CYCLE_H3_20) /* same as H3 Cut 20 */
|
||||
#define SL_INIT_SSLOTCLK_H3_30 (SUB_SLOT_CYCLE_H3_30 -1U)
|
||||
#define QOSWT_WTSET0_CYCLE_H3_30 ((SUB_SLOT_CYCLE_H3_30 * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ) /* unit:ns */
|
||||
|
||||
#endif
|
||||
|
||||
#if (RCAR_LSI == RCAR_H3N)
|
||||
/* define used for H3N */
|
||||
#if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 1.95usec */
|
||||
#define SUB_SLOT_CYCLE_H3N (0x84U) /* 132 */
|
||||
#else /* REF 3.9usec */
|
||||
#define SUB_SLOT_CYCLE_H3N (0x108U) /* 264 */
|
||||
#endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
|
||||
|
||||
#define SL_INIT_SSLOTCLK_H3N (SUB_SLOT_CYCLE_H3N -1U)
|
||||
#define QOSWT_WTSET0_CYCLE_H3N ((SUB_SLOT_CYCLE_H3N * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ) /* unit:ns */
|
||||
|
||||
#endif
|
||||
|
||||
#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3)
|
||||
/* define used for M3 */
|
||||
#if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 1.95usec */
|
||||
#define SUB_SLOT_CYCLE_M3_11 (0x84U) /* 132 */
|
||||
#else /* REF 3.9usec */
|
||||
#define SUB_SLOT_CYCLE_M3_11 (0x108U) /* 264 */
|
||||
#endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
|
||||
|
||||
#define SL_INIT_SSLOTCLK_M3_11 (SUB_SLOT_CYCLE_M3_11 -1U)
|
||||
#define QOSWT_WTSET0_CYCLE_M3_11 ((SUB_SLOT_CYCLE_M3_11 * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ) /* unit:ns */
|
||||
#endif
|
||||
|
||||
#define OPERATING_FREQ (400U) /* MHz */
|
||||
#define BASE_SUB_SLOT_NUM (0x6U)
|
||||
#define SUB_SLOT_CYCLE (0x7EU) /* 126 */
|
||||
|
||||
#define QOSWT_WTSET0_CYCLE ((SUB_SLOT_CYCLE * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ) /* unit:ns */
|
||||
|
||||
#define SL_INIT_REFFSSLOT (0x3U << 24U)
|
||||
#define SL_INIT_SLOTSSLOT ((BASE_SUB_SLOT_NUM - 1U) << 16U)
|
||||
#define SL_INIT_SSLOTCLK (SUB_SLOT_CYCLE -1U)
|
||||
|
||||
static inline void io_write_32(uintptr_t addr, uint32_t value)
|
||||
{
|
||||
*(volatile uint32_t *)addr = value;
|
||||
}
|
||||
|
||||
static inline uint32_t io_read_32(uintptr_t addr)
|
||||
{
|
||||
return *(volatile uint32_t *)addr;
|
||||
}
|
||||
|
||||
static inline void io_write_64(uintptr_t addr, uint64_t value)
|
||||
{
|
||||
*(volatile uint64_t *)addr = value;
|
||||
}
|
||||
|
||||
typedef struct {
|
||||
uintptr_t addr;
|
||||
uint64_t value;
|
||||
} mstat_slot_t;
|
||||
|
||||
extern uint32_t qos_init_ddr_ch;
|
||||
extern uint8_t qos_init_ddr_phyvalid;
|
||||
|
||||
#endif /* QOS_COMMON_H_ */
|
327
drivers/staging/renesas/rcar/qos/qos_init.c
Normal file
327
drivers/staging/renesas/rcar/qos/qos_init.c
Normal file
|
@ -0,0 +1,327 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <debug.h>
|
||||
#include <mmio.h>
|
||||
#include "qos_init.h"
|
||||
#include "qos_common.h"
|
||||
#if RCAR_LSI == RCAR_AUTO
|
||||
#include "H3/qos_init_h3_v10.h"
|
||||
#include "H3/qos_init_h3_v11.h"
|
||||
#include "H3/qos_init_h3_v20.h"
|
||||
#include "H3/qos_init_h3_v30.h"
|
||||
#include "M3/qos_init_m3_v10.h"
|
||||
#include "M3/qos_init_m3_v11.h"
|
||||
#include "M3N/qos_init_m3n_v10.h"
|
||||
#endif
|
||||
#if RCAR_LSI == RCAR_H3 /* H3 */
|
||||
#include "H3/qos_init_h3_v10.h"
|
||||
#include "H3/qos_init_h3_v11.h"
|
||||
#include "H3/qos_init_h3_v20.h"
|
||||
#include "H3/qos_init_h3_v30.h"
|
||||
#endif
|
||||
#if RCAR_LSI == RCAR_H3N /* H3 */
|
||||
#include "H3/qos_init_h3n_v30.h"
|
||||
#endif
|
||||
#if RCAR_LSI == RCAR_M3 /* M3 */
|
||||
#include "M3/qos_init_m3_v10.h"
|
||||
#include "M3/qos_init_m3_v11.h"
|
||||
#endif
|
||||
#if RCAR_LSI == RCAR_M3N /* M3N */
|
||||
#include "M3N/qos_init_m3n_v10.h"
|
||||
#endif
|
||||
#if RCAR_LSI == RCAR_E3 /* E3 */
|
||||
#include "E3/qos_init_e3_v10.h"
|
||||
#endif
|
||||
|
||||
/* Product Register */
|
||||
#define PRR (0xFFF00044U)
|
||||
#define PRR_PRODUCT_MASK (0x00007F00U)
|
||||
#define PRR_CUT_MASK (0x000000FFU)
|
||||
#define PRR_PRODUCT_H3 (0x00004F00U) /* R-Car H3 */
|
||||
#define PRR_PRODUCT_M3 (0x00005200U) /* R-Car M3 */
|
||||
#define PRR_PRODUCT_M3N (0x00005500U) /* R-Car M3N */
|
||||
#define PRR_PRODUCT_E3 (0x00005700U) /* R-Car E3 */
|
||||
#define PRR_PRODUCT_10 (0x00U)
|
||||
#define PRR_PRODUCT_11 (0x01U)
|
||||
#define PRR_PRODUCT_20 (0x10U)
|
||||
#define PRR_PRODUCT_30 (0x20U)
|
||||
|
||||
#if !(RCAR_LSI == RCAR_E3)
|
||||
|
||||
#define DRAM_CH_CNT 0x04
|
||||
uint32_t qos_init_ddr_ch;
|
||||
uint8_t qos_init_ddr_phyvalid;
|
||||
|
||||
#endif
|
||||
|
||||
#define PRR_PRODUCT_ERR(reg) \
|
||||
do{ \
|
||||
ERROR("LSI Product ID(PRR=0x%x) QoS " \
|
||||
"initialize not supported.\n",reg); \
|
||||
panic(); \
|
||||
} while(0)
|
||||
|
||||
#define PRR_CUT_ERR(reg) \
|
||||
do{ \
|
||||
ERROR("LSI Cut ID(PRR=0x%x) QoS " \
|
||||
"initialize not supported.\n",reg); \
|
||||
panic(); \
|
||||
} while(0)
|
||||
|
||||
void rcar_qos_init(void)
|
||||
{
|
||||
uint32_t reg;
|
||||
#if !(RCAR_LSI == RCAR_E3)
|
||||
uint32_t i;
|
||||
|
||||
qos_init_ddr_ch = 0;
|
||||
qos_init_ddr_phyvalid = get_boardcnf_phyvalid();
|
||||
for (i = 0; i < DRAM_CH_CNT; i++) {
|
||||
if ((qos_init_ddr_phyvalid & (1 << i))) {
|
||||
qos_init_ddr_ch++;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
reg = mmio_read_32(PRR);
|
||||
#if (RCAR_LSI == RCAR_AUTO) || RCAR_LSI_CUT_COMPAT
|
||||
switch (reg & PRR_PRODUCT_MASK) {
|
||||
case PRR_PRODUCT_H3:
|
||||
#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_H3)
|
||||
switch (reg & PRR_CUT_MASK) {
|
||||
case PRR_PRODUCT_10:
|
||||
qos_init_h3_v10();
|
||||
break;
|
||||
case PRR_PRODUCT_11:
|
||||
qos_init_h3_v11();
|
||||
break;
|
||||
case PRR_PRODUCT_20:
|
||||
qos_init_h3_v20();
|
||||
break;
|
||||
case PRR_PRODUCT_30:
|
||||
default:
|
||||
qos_init_h3_v30();
|
||||
break;
|
||||
}
|
||||
#elif (RCAR_LSI == RCAR_H3N)
|
||||
switch (reg & PRR_CUT_MASK) {
|
||||
case PRR_PRODUCT_30:
|
||||
default:
|
||||
qos_init_h3n_v30();
|
||||
break;
|
||||
}
|
||||
#else
|
||||
PRR_PRODUCT_ERR(reg);
|
||||
#endif
|
||||
break;
|
||||
case PRR_PRODUCT_M3:
|
||||
#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3)
|
||||
switch (reg & PRR_CUT_MASK) {
|
||||
case PRR_PRODUCT_10:
|
||||
qos_init_m3_v10();
|
||||
break;
|
||||
case PRR_PRODUCT_20: /* M3 Cut 11 */
|
||||
default:
|
||||
qos_init_m3_v11();
|
||||
break;
|
||||
}
|
||||
#else
|
||||
PRR_PRODUCT_ERR(reg);
|
||||
#endif
|
||||
break;
|
||||
case PRR_PRODUCT_M3N:
|
||||
#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N)
|
||||
switch (reg & PRR_CUT_MASK) {
|
||||
case PRR_PRODUCT_10:
|
||||
default:
|
||||
qos_init_m3n_v10();
|
||||
break;
|
||||
}
|
||||
#else
|
||||
PRR_PRODUCT_ERR(reg);
|
||||
#endif
|
||||
break;
|
||||
case PRR_PRODUCT_E3:
|
||||
#if (RCAR_LSI == RCAR_E3)
|
||||
switch (reg & PRR_CUT_MASK) {
|
||||
case PRR_PRODUCT_10:
|
||||
default:
|
||||
qos_init_e3_v10();
|
||||
break;
|
||||
}
|
||||
#else
|
||||
PRR_PRODUCT_ERR(reg);
|
||||
#endif
|
||||
break;
|
||||
default:
|
||||
PRR_PRODUCT_ERR(reg);
|
||||
break;
|
||||
}
|
||||
#else
|
||||
#if RCAR_LSI == RCAR_H3 /* H3 */
|
||||
#if RCAR_LSI_CUT == RCAR_CUT_10
|
||||
/* H3 Cut 10 */
|
||||
if ((PRR_PRODUCT_H3 | PRR_PRODUCT_10)
|
||||
!= (reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK))) {
|
||||
PRR_PRODUCT_ERR(reg);
|
||||
}
|
||||
qos_init_h3_v10();
|
||||
#elif RCAR_LSI_CUT == RCAR_CUT_11
|
||||
/* H3 Cut 11 */
|
||||
if ((PRR_PRODUCT_H3 | PRR_PRODUCT_11)
|
||||
!= (reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK))) {
|
||||
PRR_PRODUCT_ERR(reg);
|
||||
}
|
||||
qos_init_h3_v11();
|
||||
#elif RCAR_LSI_CUT == RCAR_CUT_20
|
||||
/* H3 Cut 20 */
|
||||
if ((PRR_PRODUCT_H3 | PRR_PRODUCT_20)
|
||||
!= (reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK))) {
|
||||
PRR_PRODUCT_ERR(reg);
|
||||
}
|
||||
qos_init_h3_v20();
|
||||
#else
|
||||
/* H3 Cut 30 or later */
|
||||
if ((PRR_PRODUCT_H3)
|
||||
!= (reg & (PRR_PRODUCT_MASK))) {
|
||||
PRR_PRODUCT_ERR(reg);
|
||||
}
|
||||
qos_init_h3_v30();
|
||||
#endif
|
||||
#elif RCAR_LSI == RCAR_H3N /* H3 */
|
||||
/* H3N Cut 30 or later */
|
||||
if ((PRR_PRODUCT_H3)
|
||||
!= (reg & (PRR_PRODUCT_MASK))) {
|
||||
PRR_PRODUCT_ERR(reg);
|
||||
}
|
||||
qos_init_h3n_v30();
|
||||
#elif RCAR_LSI == RCAR_M3 /* M3 */
|
||||
#if RCAR_LSI_CUT == RCAR_CUT_10
|
||||
/* M3 Cut 10 */
|
||||
if ((PRR_PRODUCT_M3 | PRR_PRODUCT_10)
|
||||
!= (reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK))) {
|
||||
PRR_PRODUCT_ERR(reg);
|
||||
}
|
||||
qos_init_m3_v10();
|
||||
#else
|
||||
/* M3 Cut 11 or later */
|
||||
if ((PRR_PRODUCT_M3)
|
||||
!= (reg & (PRR_PRODUCT_MASK))) {
|
||||
PRR_PRODUCT_ERR(reg);
|
||||
}
|
||||
qos_init_m3_v11();
|
||||
#endif
|
||||
#elif RCAR_LSI == RCAR_M3N /* M3N */
|
||||
/* M3N Cut 10 or later */
|
||||
if ((PRR_PRODUCT_M3N)
|
||||
!= (reg & (PRR_PRODUCT_MASK))) {
|
||||
PRR_PRODUCT_ERR(reg);
|
||||
}
|
||||
qos_init_m3n_v10();
|
||||
#elif RCAR_LSI == RCAR_E3 /* E3 */
|
||||
/* E3 Cut 10 or later */
|
||||
if ((PRR_PRODUCT_E3)
|
||||
!= (reg & (PRR_PRODUCT_MASK))) {
|
||||
PRR_PRODUCT_ERR(reg);
|
||||
}
|
||||
qos_init_e3_v10();
|
||||
#else
|
||||
#error "Don't have QoS initialize routine(Unknown chip)."
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
|
||||
uint32_t get_refperiod(void)
|
||||
{
|
||||
uint32_t refperiod = QOSWT_WTSET0_CYCLE;
|
||||
|
||||
#if (RCAR_LSI == RCAR_AUTO) || RCAR_LSI_CUT_COMPAT
|
||||
uint32_t reg;
|
||||
|
||||
reg = mmio_read_32(PRR);
|
||||
switch (reg & PRR_PRODUCT_MASK) {
|
||||
#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_H3)
|
||||
case PRR_PRODUCT_H3:
|
||||
switch (reg & PRR_CUT_MASK) {
|
||||
case PRR_PRODUCT_10:
|
||||
case PRR_PRODUCT_11:
|
||||
break;
|
||||
case PRR_PRODUCT_20:
|
||||
refperiod = QOSWT_WTSET0_CYCLE_H3_20;
|
||||
break;
|
||||
case PRR_PRODUCT_30:
|
||||
default:
|
||||
refperiod = QOSWT_WTSET0_CYCLE_H3_30;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
#elif (RCAR_LSI == RCAR_H3N)
|
||||
case PRR_PRODUCT_H3:
|
||||
switch (reg & PRR_CUT_MASK) {
|
||||
case PRR_PRODUCT_30:
|
||||
default:
|
||||
refperiod = QOSWT_WTSET0_CYCLE_H3N;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
#endif
|
||||
#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3)
|
||||
case PRR_PRODUCT_M3:
|
||||
switch (reg & PRR_CUT_MASK) {
|
||||
case PRR_PRODUCT_10:
|
||||
break;
|
||||
case PRR_PRODUCT_20: /* M3 Cut 11 */
|
||||
default:
|
||||
refperiod = QOSWT_WTSET0_CYCLE_M3_11;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
#endif
|
||||
#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N)
|
||||
case PRR_PRODUCT_M3N:
|
||||
refperiod = QOSWT_WTSET0_CYCLE_M3N;
|
||||
break;
|
||||
#endif
|
||||
#if (RCAR_LSI == RCAR_E3)
|
||||
case PRR_PRODUCT_E3:
|
||||
refperiod = QOSWT_WTSET0_CYCLE_E3;
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
break;
|
||||
}
|
||||
#elif RCAR_LSI == RCAR_H3
|
||||
#if RCAR_LSI_CUT == RCAR_CUT_10
|
||||
/* H3 Cut 10 */
|
||||
#elif RCAR_LSI_CUT == RCAR_CUT_11
|
||||
/* H3 Cut 11 */
|
||||
#elif RCAR_LSI_CUT == RCAR_CUT_20
|
||||
/* H3 Cut 20 */
|
||||
refperiod = QOSWT_WTSET0_CYCLE_H3_20;
|
||||
#else
|
||||
/* H3 Cut 30 or later */
|
||||
refperiod = QOSWT_WTSET0_CYCLE_H3_30;
|
||||
#endif
|
||||
#elif RCAR_LSI == RCAR_H3N
|
||||
/* H3N Cut 30 or later */
|
||||
refperiod = QOSWT_WTSET0_CYCLE_H3N;
|
||||
#elif RCAR_LSI == RCAR_M3
|
||||
#if RCAR_LSI_CUT == RCAR_CUT_10
|
||||
/* M3 Cut 10 */
|
||||
#else
|
||||
/* M3 Cut 11 or later */
|
||||
refperiod = QOSWT_WTSET0_CYCLE_M3_11;
|
||||
#endif
|
||||
#elif RCAR_LSI == RCAR_M3N /* for M3N */
|
||||
refperiod = QOSWT_WTSET0_CYCLE_M3N;
|
||||
#elif RCAR_LSI == RCAR_E3 /* for E3 */
|
||||
refperiod = QOSWT_WTSET0_CYCLE_E3;
|
||||
#endif
|
||||
|
||||
return refperiod;
|
||||
}
|
13
drivers/staging/renesas/rcar/qos/qos_init.h
Normal file
13
drivers/staging/renesas/rcar/qos/qos_init.h
Normal file
|
@ -0,0 +1,13 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef QOS_INIT_H_
|
||||
#define QOS_INIT_H_
|
||||
|
||||
extern void rcar_qos_init(void);
|
||||
extern uint8_t get_boardcnf_phyvalid(void);
|
||||
|
||||
#endif /* QOS_INIT_H_ */
|
121
drivers/staging/renesas/rcar/qos/qos_reg.h
Normal file
121
drivers/staging/renesas/rcar/qos/qos_reg.h
Normal file
|
@ -0,0 +1,121 @@
|
|||
/*
|
||||
* Copyright (c) 2017-2018, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef QOS_REG_H_
|
||||
#define QOS_REG_H_
|
||||
|
||||
#define RCAR_QOS_NONE (3U)
|
||||
#define RCAR_QOS_TYPE_DEFAULT (0U)
|
||||
|
||||
#define RCAR_DRAM_SPLIT_LINEAR (0U)
|
||||
#define RCAR_DRAM_SPLIT_4CH (1U)
|
||||
#define RCAR_DRAM_SPLIT_2CH (2U)
|
||||
#define RCAR_DRAM_SPLIT_AUTO (3U)
|
||||
#define RST_BASE (0xE6160000U)
|
||||
#define RST_MODEMR (RST_BASE + 0x0060U)
|
||||
|
||||
#define DBSC_BASE (0xE6790000U)
|
||||
#define DBSC_DBSYSCNT0 (DBSC_BASE + 0x0100U)
|
||||
#define DBSC_DBCAM0CNF1 (DBSC_BASE + 0x0904U)
|
||||
#define DBSC_DBCAM0CNF2 (DBSC_BASE + 0x0908U)
|
||||
#define DBSC_DBCAM0CNF3 (DBSC_BASE + 0x090CU)
|
||||
#define DBSC_DBSCHCNT0 (DBSC_BASE + 0x1000U)
|
||||
#define DBSC_DBSCHSZ0 (DBSC_BASE + 0x1010U)
|
||||
#define DBSC_DBSCHRW0 (DBSC_BASE + 0x1020U)
|
||||
#define DBSC_DBSCHQOS00 (DBSC_BASE + 0x1030U)
|
||||
#define DBSC_DBSCHQOS01 (DBSC_BASE + 0x1034U)
|
||||
#define DBSC_DBSCHQOS02 (DBSC_BASE + 0x1038U)
|
||||
#define DBSC_DBSCHQOS03 (DBSC_BASE + 0x103CU)
|
||||
#define DBSC_DBSCHQOS40 (DBSC_BASE + 0x1070U)
|
||||
#define DBSC_DBSCHQOS41 (DBSC_BASE + 0x1074U)
|
||||
#define DBSC_DBSCHQOS42 (DBSC_BASE + 0x1078U)
|
||||
#define DBSC_DBSCHQOS43 (DBSC_BASE + 0x107CU)
|
||||
#define DBSC_DBSCHQOS90 (DBSC_BASE + 0x10C0U)
|
||||
#define DBSC_DBSCHQOS91 (DBSC_BASE + 0x10C4U)
|
||||
#define DBSC_DBSCHQOS92 (DBSC_BASE + 0x10C8U)
|
||||
#define DBSC_DBSCHQOS93 (DBSC_BASE + 0x10CCU)
|
||||
#define DBSC_DBSCHQOS120 (DBSC_BASE + 0x10F0U)
|
||||
#define DBSC_DBSCHQOS121 (DBSC_BASE + 0x10F4U)
|
||||
#define DBSC_DBSCHQOS122 (DBSC_BASE + 0x10F8U)
|
||||
#define DBSC_DBSCHQOS123 (DBSC_BASE + 0x10FCU)
|
||||
#define DBSC_DBSCHQOS130 (DBSC_BASE + 0x1100U)
|
||||
#define DBSC_DBSCHQOS131 (DBSC_BASE + 0x1104U)
|
||||
#define DBSC_DBSCHQOS132 (DBSC_BASE + 0x1108U)
|
||||
#define DBSC_DBSCHQOS133 (DBSC_BASE + 0x110CU)
|
||||
#define DBSC_DBSCHQOS140 (DBSC_BASE + 0x1110U)
|
||||
#define DBSC_DBSCHQOS141 (DBSC_BASE + 0x1114U)
|
||||
#define DBSC_DBSCHQOS142 (DBSC_BASE + 0x1118U)
|
||||
#define DBSC_DBSCHQOS143 (DBSC_BASE + 0x111CU)
|
||||
#define DBSC_DBSCHQOS150 (DBSC_BASE + 0x1120U)
|
||||
#define DBSC_DBSCHQOS151 (DBSC_BASE + 0x1124U)
|
||||
#define DBSC_DBSCHQOS152 (DBSC_BASE + 0x1128U)
|
||||
#define DBSC_DBSCHQOS153 (DBSC_BASE + 0x112CU)
|
||||
#define DBSC_SCFCTST2 (DBSC_BASE + 0x170CU)
|
||||
|
||||
#define AXI_BASE (0xE6784000U)
|
||||
#define AXI_ADSPLCR0 (AXI_BASE + 0x0008U)
|
||||
#define AXI_ADSPLCR1 (AXI_BASE + 0x000CU)
|
||||
#define AXI_ADSPLCR2 (AXI_BASE + 0x0010U)
|
||||
#define AXI_ADSPLCR3 (AXI_BASE + 0x0014U)
|
||||
#define AXI_MMCR (AXI_BASE + 0x0300U)
|
||||
#define ADSPLCR0_ADRMODE_DEFAULT ((uint32_t)0U << 31U)
|
||||
#define ADSPLCR0_ADRMODE_GEN2 ((uint32_t)1U << 31U)
|
||||
#define ADSPLCR0_SPLITSEL(x) ((uint32_t)(x) << 16U)
|
||||
#define ADSPLCR0_AREA(x) ((uint32_t)(x) << 8U)
|
||||
#define ADSPLCR0_SWP (0x0CU)
|
||||
|
||||
#define AXI_TR3CR (0xE67D100CU)
|
||||
#define AXI_TR4CR (0xE67D1014U)
|
||||
|
||||
#define QOS_BASE0 (0xE67E0000U)
|
||||
#define QOSBW_FIX_QOS_BANK0 (QOS_BASE0 + 0x0000U)
|
||||
#define QOSBW_FIX_QOS_BANK1 (QOS_BASE0 + 0x1000U)
|
||||
#define QOSBW_BE_QOS_BANK0 (QOS_BASE0 + 0x2000U)
|
||||
#define QOSBW_BE_QOS_BANK1 (QOS_BASE0 + 0x3000U)
|
||||
#define QOSCTRL_SL_INIT (QOS_BASE0 + 0x8000U)
|
||||
#define QOSCTRL_REF_ARS (QOS_BASE0 + 0x8004U)
|
||||
#define QOSCTRL_STATQC (QOS_BASE0 + 0x8008U)
|
||||
|
||||
#define QOS_BASE1 (0xE67F0000U)
|
||||
#define QOSCTRL_RAS (QOS_BASE1 + 0x0000U)
|
||||
#define QOSCTRL_RAEN (QOS_BASE1 + 0x0018U)
|
||||
#define QOSCTRL_DANN (QOS_BASE1 + 0x0030U)
|
||||
#define QOSCTRL_DANT (QOS_BASE1 + 0x0038U)
|
||||
#define QOSCTRL_INSFC (QOS_BASE1 + 0x0050U)
|
||||
#define QOSCTRL_RACNT0 (QOS_BASE1 + 0x0080U)
|
||||
#define QOSCTRL_STATGEN0 (QOS_BASE1 + 0x0088U)
|
||||
|
||||
#define GPU_ACT_GRD (0xFD820808U)
|
||||
#define GPU_ACT0 (0xFD820800U)
|
||||
#define GPU_ACT1 (0xFD821800U)
|
||||
#define GPU_ACT2 (0xFD822800U)
|
||||
#define GPU_ACT3 (0xFD823800U)
|
||||
#define GPU_ACT4 (0xFD824800U)
|
||||
#define GPU_ACT5 (0xFD825800U)
|
||||
#define GPU_ACT6 (0xFD826800U)
|
||||
#define GPU_ACT7 (0xFD827800U)
|
||||
|
||||
#define RT_ACT0 (0xFFC50800U)
|
||||
#define RT_ACT1 (0xFFC51800U)
|
||||
|
||||
#define CPU_ACT0 (0xF1300800U)
|
||||
#define CPU_ACT1 (0xF1340800U)
|
||||
#define CPU_ACT2 (0xF1380800U)
|
||||
#define CPU_ACT3 (0xF13C0800U)
|
||||
|
||||
#define RCAR_REWT_TRAINING_DISABLE (0U)
|
||||
#define RCAR_REWT_TRAINING_ENABLE (1U)
|
||||
|
||||
#define QOSWT_FIX_WTQOS_BANK0 (QOSBW_FIX_QOS_BANK0 + 0x0800U)
|
||||
#define QOSWT_FIX_WTQOS_BANK1 (QOSBW_FIX_QOS_BANK1 + 0x0800U)
|
||||
#define QOSWT_BE_WTQOS_BANK0 (QOSBW_BE_QOS_BANK0 + 0x0800U)
|
||||
#define QOSWT_BE_WTQOS_BANK1 (QOSBW_BE_QOS_BANK1 + 0x0800U)
|
||||
#define QOSWT_WTEN (QOS_BASE0 + 0x8030U)
|
||||
#define QOSWT_WTREF (QOS_BASE0 + 0x8034U)
|
||||
#define QOSWT_WTSET0 (QOS_BASE0 + 0x8038U)
|
||||
#define QOSWT_WTSET1 (QOS_BASE0 + 0x803CU)
|
||||
|
||||
#endif /* QOS_REG_H_ */
|
|
@ -293,11 +293,13 @@ ERRATA_A53_855873 := 1
|
|||
ERRATA_A57_859972 := 1
|
||||
ERRATA_A57_813419 := 1
|
||||
|
||||
include drivers/renesas/rcar/ddr/ddr.mk
|
||||
include drivers/renesas/rcar/qos/qos.mk
|
||||
include drivers/renesas/rcar/pfc/pfc.mk
|
||||
include drivers/staging/renesas/rcar/ddr/ddr.mk
|
||||
include drivers/staging/renesas/rcar/qos/qos.mk
|
||||
include drivers/staging/renesas/rcar/pfc/pfc.mk
|
||||
|
||||
PLAT_INCLUDES := -Iinclude/common/tbbr \
|
||||
-Idrivers/staging/renesas/rcar/ddr \
|
||||
-Idrivers/staging/renesas/rcar/qos \
|
||||
-Idrivers/renesas/rcar/iic_dvfs \
|
||||
-Idrivers/renesas/rcar/board \
|
||||
-Idrivers/renesas/rcar/avs \
|
||||
|
@ -307,8 +309,6 @@ PLAT_INCLUDES := -Iinclude/common/tbbr \
|
|||
-Idrivers/renesas/rcar/emmc \
|
||||
-Idrivers/renesas/rcar/pwrc \
|
||||
-Idrivers/renesas/rcar/io \
|
||||
-Idrivers/renesas/rcar/ddr \
|
||||
-Idrivers/renesas/rcar/qos \
|
||||
-Iplat/renesas/rcar/include/registers \
|
||||
-Iplat/renesas/rcar/include \
|
||||
-Iplat/renesas/rcar
|
||||
|
|
Loading…
Add table
Reference in a new issue