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corstone700: set UART clocks to 32MHz

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Adding support for 32MHz UART clock and selecting it as the
default UART clock

Change-Id: I9541eaff70424e85a3b5ee4820ca0e7efb040d2c
Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
This commit is contained in:
Vishnu Banavath 2019-08-07 10:49:05 +01:00 • committed by Abdellatif El Khlifi
parent 93cf1f6454
commit 6aa138ded5
2 changed files with 25 additions and 5 deletions
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17
fdts/corstone700.dts
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2019-2020, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -68,14 +68,21 @@
clock-output-names = "smclk";
};
uartclk: uartclk {
/* UART clock - 32MHz */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32000000>;
clock-output-names = "uartclk";
};
serial0: uart@1a510000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x1a510000 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 19 4>;
clocks = <&refclk100mhz>, <&smbclk>;
clock-names = "apb_pclk", "smclk";
clocks = <&uartclk>, <&refclk100mhz>;
clock-names = "uartclk", "apb_pclk";
};
serial1: uart@1a520000 {
@ -83,8 +90,8 @@
reg = <0x1a520000 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 20 4>;
clocks = <&refclk100mhz>, <&smbclk>;
clock-names = "apb_pclk", "smclk";
clocks = <&uartclk>, <&refclk100mhz>;
clock-names = "uartclk", "apb_pclk";
};
timer {

13
plat/arm/board/corstone700/include/platform_def.h
View file

@ -9,10 +9,23 @@
#include <lib/utils_def.h>
#include <lib/xlat_tables/xlat_tables_defs.h>
#include <plat/arm/board/common/v2m_def.h>
#include <plat/arm/common/arm_spm_def.h>
#include <plat/common/common_def.h>
/* PL011 UART related constants */
#ifdef V2M_IOFPGA_UART0_CLK_IN_HZ
#undef V2M_IOFPGA_UART0_CLK_IN_HZ
#endif
#ifdef V2M_IOFPGA_UART1_CLK_IN_HZ
#undef V2M_IOFPGA_UART1_CLK_IN_HZ
#endif
#define V2M_IOFPGA_UART0_CLK_IN_HZ 32000000
#define V2M_IOFPGA_UART1_CLK_IN_HZ 32000000
/* Core/Cluster/Thread counts for Corstone700 */
#define CORSTONE700_CLUSTER_COUNT U(1)
#define CORSTONE700_MAX_CPUS_PER_CLUSTER U(4)