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Merge "feat(cpufeat): initialize HFG*_EL2 registers" into integration
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commit
6a62ddff78
2 changed files with 40 additions and 0 deletions
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@ -1378,6 +1378,13 @@
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#define HCRX_EL2_EnAS0_BIT (UL(1) << 0)
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#define HCRX_EL2_INIT_VAL ULL(0x0)
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/*******************************************************************************
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* FEAT_FGT - Definitions for Fine-Grained Trap registers
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******************************************************************************/
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#define HFGITR_EL2_INIT_VAL ULL(0x180000000000000)
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#define HFGRTR_EL2_INIT_VAL ULL(0xC4000000000000)
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#define HFGWTR_EL2_INIT_VAL ULL(0xC4000000000000)
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/*******************************************************************************
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* FEAT_TCR2 - Extended Translation Control Register
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******************************************************************************/
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@ -279,6 +279,20 @@ static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *
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write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_HCRX_EL2,
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HCRX_EL2_INIT_VAL);
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}
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if (is_feat_fgt_supported()) {
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/*
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* Initialize HFG*_EL2 registers with a default value so legacy
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* systems unaware of FEAT_FGT do not get trapped due to their lack
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* of initialization for this feature.
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*/
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write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_HFGITR_EL2,
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HFGITR_EL2_INIT_VAL);
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write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_HFGRTR_EL2,
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HFGRTR_EL2_INIT_VAL);
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write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_HFGWTR_EL2,
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HFGWTR_EL2_INIT_VAL);
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}
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#endif /* CTX_INCLUDE_EL2_REGS */
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manage_extensions_nonsecure(ctx);
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@ -829,7 +843,26 @@ void cm_prepare_el3_exit(uint32_t security_state)
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if (is_feat_hcx_supported()) {
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write_hcrx_el2(HCRX_EL2_INIT_VAL);
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}
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/*
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* Initialize Fine-grained trap registers introduced
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* by FEAT_FGT so all traps are initially disabled when
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* switching to EL2 or a lower EL, preventing undesired
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* behavior.
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*/
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if (is_feat_fgt_supported()) {
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/*
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* Initialize HFG*_EL2 registers with a default
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* value so legacy systems unaware of FEAT_FGT
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* do not get trapped due to their lack of
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* initialization for this feature.
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*/
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write_hfgitr_el2(HFGITR_EL2_INIT_VAL);
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write_hfgrtr_el2(HFGRTR_EL2_INIT_VAL);
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write_hfgwtr_el2(HFGWTR_EL2_INIT_VAL);
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}
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}
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if ((scr_el3 & SCR_HCE_BIT) != 0U) {
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/* Use SCTLR_EL1.EE value to initialise sctlr_el2 */
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