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Merge "feat(cpufeat): initialize HFG*_EL2 registers" into integration

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Manish Pandey 2023-08-30 16:19:26 +02:00 • committed by TrustedFirmware Code Review
commit 6a62ddff78
2 changed files with 40 additions and 0 deletions
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7
include/arch/aarch64/arch.h
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@ -1378,6 +1378,13 @@
#define HCRX_EL2_EnAS0_BIT (UL(1) << 0) #define HCRX_EL2_EnAS0_BIT (UL(1) << 0)
#define HCRX_EL2_INIT_VAL ULL(0x0) #define HCRX_EL2_INIT_VAL ULL(0x0)
/*******************************************************************************
* FEAT_FGT - Definitions for Fine-Grained Trap registers
******************************************************************************/
#define HFGITR_EL2_INIT_VAL ULL(0x180000000000000)
#define HFGRTR_EL2_INIT_VAL ULL(0xC4000000000000)
#define HFGWTR_EL2_INIT_VAL ULL(0xC4000000000000)
/******************************************************************************* /*******************************************************************************
* FEAT_TCR2 - Extended Translation Control Register * FEAT_TCR2 - Extended Translation Control Register
******************************************************************************/ ******************************************************************************/

33
lib/el3_runtime/aarch64/context_mgmt.c
View file

@ -279,6 +279,20 @@ static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *
write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_HCRX_EL2, write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_HCRX_EL2,
HCRX_EL2_INIT_VAL); HCRX_EL2_INIT_VAL);
} }
if (is_feat_fgt_supported()) {
/*
* Initialize HFG*_EL2 registers with a default value so legacy
* systems unaware of FEAT_FGT do not get trapped due to their lack
* of initialization for this feature.
*/
write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_HFGITR_EL2,
HFGITR_EL2_INIT_VAL);
write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_HFGRTR_EL2,
HFGRTR_EL2_INIT_VAL);
write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_HFGWTR_EL2,
HFGWTR_EL2_INIT_VAL);
}
#endif /* CTX_INCLUDE_EL2_REGS */ #endif /* CTX_INCLUDE_EL2_REGS */
manage_extensions_nonsecure(ctx); manage_extensions_nonsecure(ctx);
@ -829,8 +843,27 @@ void cm_prepare_el3_exit(uint32_t security_state)
if (is_feat_hcx_supported()) { if (is_feat_hcx_supported()) {
write_hcrx_el2(HCRX_EL2_INIT_VAL); write_hcrx_el2(HCRX_EL2_INIT_VAL);
} }
/*
* Initialize Fine-grained trap registers introduced
* by FEAT_FGT so all traps are initially disabled when
* switching to EL2 or a lower EL, preventing undesired
* behavior.
*/
if (is_feat_fgt_supported()) {
/*
* Initialize HFG*_EL2 registers with a default
* value so legacy systems unaware of FEAT_FGT
* do not get trapped due to their lack of
* initialization for this feature.
*/
write_hfgitr_el2(HFGITR_EL2_INIT_VAL);
write_hfgrtr_el2(HFGRTR_EL2_INIT_VAL);
write_hfgwtr_el2(HFGWTR_EL2_INIT_VAL);
}
} }
if ((scr_el3 & SCR_HCE_BIT) != 0U) { if ((scr_el3 & SCR_HCE_BIT) != 0U) {
/* Use SCTLR_EL1.EE value to initialise sctlr_el2 */ /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */
sctlr_elx = read_ctx_reg(get_el1_sysregs_ctx(ctx), sctlr_elx = read_ctx_reg(get_el1_sysregs_ctx(ctx),