From c833ca66a6fecbc54e038164e466be677559ec4e Mon Sep 17 00:00:00 2001 From: Bipin Ravi Date: Wed, 10 Apr 2024 15:33:21 -0500 Subject: [PATCH] fix(cpus): workaround for Cortex-X4 erratum 2740089 Cortex-X4 erratum 2740089 is a Cat B erratum that applies to all revisions <=r0p1 and is fixed in r0p2. The workaround is to insert a dsb before the isb in the power down sequence. SDEN documentation: https://developer.arm.com/documentation/SDEN2432808/latest Change-Id: I1d0fa4dd383437044a4467591f65a4a8514cabdc Signed-off-by: Bipin Ravi --- docs/design/cpu-specific-build-macros.rst | 4 ++++ lib/cpus/aarch64/cortex_x4.S | 12 +++++++++++- lib/cpus/cpu-ops.mk | 4 ++++ 3 files changed, 19 insertions(+), 1 deletion(-) diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index f1553b2e0..a8e8d61ab 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -826,6 +826,10 @@ For Cortex-X4, the following errata build flags are defined : feature is enabled and can assist the Kernel in the process of mitigation of the erratum. +- ``ERRATA_X4_2740089``: This applies errata 2740089 workaround to Cortex-X4 + CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed + in r0p2. + For Cortex-A510, the following errata build flags are defined : - ``ERRATA_A510_1922240``: This applies errata 1922240 workaround to diff --git a/lib/cpus/aarch64/cortex_x4.S b/lib/cpus/aarch64/cortex_x4.S index 7619f9cf2..29c7a4a60 100644 --- a/lib/cpus/aarch64/cortex_x4.S +++ b/lib/cpus/aarch64/cortex_x4.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022-2023, Arm Limited. All rights reserved. + * Copyright (c) 2022-2024, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -26,6 +26,13 @@ wa_cve_2022_23960_bhb_vector_table CORTEX_X4_BHB_LOOP_COUNT, cortex_x4 #endif /* WORKAROUND_CVE_2022_23960 */ +workaround_runtime_start cortex_x4, ERRATUM(2740089), ERRATA_X4_2740089 + /* dsb before isb of power down sequence */ + dsb sy +workaround_runtime_end cortex_x4, ERRATUM(2740089) + +check_erratum_ls cortex_x4, ERRATUM(2740089), CPU_REV(0, 1) + workaround_reset_start cortex_x4, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 #if IMAGE_BL31 /* @@ -53,6 +60,9 @@ func cortex_x4_core_pwr_dwn * --------------------------------------------------- */ sysreg_bit_set CORTEX_X4_CPUPWRCTLR_EL1, CORTEX_X4_CPUPWRCTLR_EL1_CORE_PWRDN_BIT + + apply_erratum cortex_x4, ERRATUM(2740089), ERRATA_X4_2740089 + isb ret endfunc cortex_x4_core_pwr_dwn diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index b28d90d08..5478e57b8 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -823,6 +823,10 @@ CPU_FLAG_LIST += ERRATA_X3_2779509 # cpu and is fixed in r0p1. CPU_FLAG_LIST += ERRATA_X4_2701112 +# Flag to apply erratum 2740089 workaround during powerdown. This erratum +# applies to all revisions <= r0p1 of the Cortex-X4 cpu, it is fixed in r0p2. +CPU_FLAG_LIST += ERRATA_X4_2740089 + # Flag to apply erratum 1922240 workaround during reset. This erratum applies # to revision r0p0 of the Cortex-A510 cpu and is fixed in r0p1. CPU_FLAG_LIST += ERRATA_A510_1922240