mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-21 20:14:29 +00:00
stm32mp1: Add GPIO support
The management of pinctrl nodes of device tree is also added. Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Mathieu Belou <mathieu.belou@st.com> Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
This commit is contained in:
Yann Gautier
parent
7839a05090
commit
6a339a4952
5 changed files with 347 additions and 0 deletions
86
drivers/st/gpio/stm32_gpio.c
Normal file
86
drivers/st/gpio/stm32_gpio.c
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@ -0,0 +1,86 @@
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/*
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* Copyright (c) 2016-2018, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <bl_common.h>
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#include <debug.h>
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#include <mmio.h>
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#include <stdbool.h>
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#include <stm32_gpio.h>
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static bool check_gpio(uint32_t bank, uint32_t pin)
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{
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if (pin > GPIO_PIN_MAX) {
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ERROR("%s: wrong pin number (%d)\n", __func__, pin);
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return false;
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}
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if ((bank > GPIO_BANK_K) && (bank != GPIO_BANK_Z)) {
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ERROR("%s: wrong GPIO bank number (%d)\n", __func__, bank);
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return false;
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}
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return true;
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}
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void set_gpio(uint32_t bank, uint32_t pin, uint32_t mode, uint32_t speed,
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uint32_t pull, uint32_t alternate)
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{
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volatile uint32_t bank_address;
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if (!check_gpio(bank, pin)) {
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return;
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}
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if (bank == GPIO_BANK_Z) {
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bank_address = STM32_GPIOZ_BANK;
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} else {
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bank_address = STM32_GPIOA_BANK +
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(bank * STM32_GPIO_BANK_OFFSET);
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}
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mmio_clrbits_32(bank_address + GPIO_MODE_OFFSET,
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((uint32_t)GPIO_MODE_MASK << (pin << 1)));
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mmio_setbits_32(bank_address + GPIO_MODE_OFFSET,
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(mode & ~GPIO_OPEN_DRAIN) << (pin << 1));
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if ((mode & GPIO_OPEN_DRAIN) != 0U) {
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mmio_setbits_32(bank_address + GPIO_TYPE_OFFSET,
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BIT(pin));
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}
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mmio_clrbits_32(bank_address + GPIO_SPEED_OFFSET,
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((uint32_t)GPIO_SPEED_MASK << (pin << 1)));
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mmio_setbits_32(bank_address + GPIO_SPEED_OFFSET, speed << (pin << 1));
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mmio_clrbits_32(bank_address + GPIO_PUPD_OFFSET,
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((uint32_t)GPIO_PULL_MASK << (pin << 1)));
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mmio_setbits_32(bank_address + GPIO_PUPD_OFFSET, pull << (pin << 1));
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if (pin < GPIO_ALT_LOWER_LIMIT) {
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mmio_clrbits_32(bank_address + GPIO_AFRL_OFFSET,
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((uint32_t)GPIO_ALTERNATE_MASK << (pin << 2)));
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mmio_setbits_32(bank_address + GPIO_AFRL_OFFSET,
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alternate << (pin << 2));
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} else {
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mmio_clrbits_32(bank_address + GPIO_AFRH_OFFSET,
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((uint32_t)GPIO_ALTERNATE_MASK <<
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((pin - GPIO_ALT_LOWER_LIMIT) << 2)));
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mmio_setbits_32(bank_address + GPIO_AFRH_OFFSET,
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alternate << ((pin - GPIO_ALT_LOWER_LIMIT) <<
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2));
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}
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VERBOSE("GPIO %u mode set to 0x%x\n", bank,
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mmio_read_32(bank_address + GPIO_MODE_OFFSET));
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VERBOSE("GPIO %u speed set to 0x%x\n", bank,
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mmio_read_32(bank_address + GPIO_SPEED_OFFSET));
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VERBOSE("GPIO %u mode pull to 0x%x\n", bank,
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mmio_read_32(bank_address + GPIO_PUPD_OFFSET));
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VERBOSE("GPIO %u mode alternate low to 0x%x\n", bank,
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mmio_read_32(bank_address + GPIO_AFRL_OFFSET));
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VERBOSE("GPIO %u mode alternate high to 0x%x\n", bank,
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mmio_read_32(bank_address + GPIO_AFRH_OFFSET));
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}
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101
include/drivers/st/stm32_gpio.h
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101
include/drivers/st/stm32_gpio.h
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@ -0,0 +1,101 @@
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/*
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* Copyright (c) 2015-2018, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __PLAT_GPIO_H__
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#define __PLAT_GPIO_H__
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#include <utils_def.h>
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#define STM32_GPIOA_BANK U(0x50002000)
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#define STM32_GPIOZ_BANK U(0x54004000)
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#define STM32_GPIO_BANK_OFFSET U(0x1000)
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#define GPIO_MODE_OFFSET U(0x00)
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#define GPIO_TYPE_OFFSET U(0x04)
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#define GPIO_SPEED_OFFSET U(0x08)
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#define GPIO_PUPD_OFFSET U(0x0C)
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#define GPIO_BSRR_OFFSET U(0x18)
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#define GPIO_AFRL_OFFSET U(0x20)
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#define GPIO_AFRH_OFFSET U(0x24)
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#define GPIO_ALT_LOWER_LIMIT U(0x08)
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#define GPIO_BANK_A U(0x00)
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#define GPIO_BANK_B U(0x01)
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#define GPIO_BANK_C U(0x02)
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#define GPIO_BANK_D U(0x03)
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#define GPIO_BANK_E U(0x04)
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#define GPIO_BANK_F U(0x05)
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#define GPIO_BANK_G U(0x06)
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#define GPIO_BANK_H U(0x07)
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#define GPIO_BANK_I U(0x08)
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#define GPIO_BANK_J U(0x09)
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#define GPIO_BANK_K U(0x0A)
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#define GPIO_BANK_Z U(0x19)
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#define GPIO_PIN_0 U(0x00)
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#define GPIO_PIN_1 U(0x01)
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#define GPIO_PIN_2 U(0x02)
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#define GPIO_PIN_3 U(0x03)
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#define GPIO_PIN_4 U(0x04)
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#define GPIO_PIN_5 U(0x05)
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#define GPIO_PIN_6 U(0x06)
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#define GPIO_PIN_7 U(0x07)
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#define GPIO_PIN_8 U(0x08)
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#define GPIO_PIN_9 U(0x09)
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#define GPIO_PIN_10 U(0x0A)
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#define GPIO_PIN_11 U(0x0B)
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#define GPIO_PIN_12 U(0x0C)
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#define GPIO_PIN_13 U(0x0D)
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#define GPIO_PIN_14 U(0x0E)
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#define GPIO_PIN_15 U(0x0F)
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#define GPIO_PIN_MAX GPIO_PIN_15
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#define GPIO_ALTERNATE_0 0x00
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#define GPIO_ALTERNATE_1 0x01
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#define GPIO_ALTERNATE_2 0x02
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#define GPIO_ALTERNATE_3 0x03
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#define GPIO_ALTERNATE_4 0x04
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#define GPIO_ALTERNATE_5 0x05
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#define GPIO_ALTERNATE_6 0x06
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#define GPIO_ALTERNATE_7 0x07
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#define GPIO_ALTERNATE_8 0x08
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#define GPIO_ALTERNATE_9 0x09
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#define GPIO_ALTERNATE_10 0x0A
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#define GPIO_ALTERNATE_11 0x0B
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#define GPIO_ALTERNATE_12 0x0C
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#define GPIO_ALTERNATE_13 0x0D
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#define GPIO_ALTERNATE_14 0x0E
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#define GPIO_ALTERNATE_15 0x0F
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#define GPIO_ALTERNATE_MASK U(0x0F)
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#define GPIO_MODE_INPUT 0x00
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#define GPIO_MODE_OUTPUT 0x01
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#define GPIO_MODE_ALTERNATE 0x02
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#define GPIO_MODE_ANALOG 0x03
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#define GPIO_MODE_MASK U(0x03)
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#define GPIO_OPEN_DRAIN U(0x10)
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#define GPIO_SPEED_LOW 0x00
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#define GPIO_SPEED_MEDIUM 0x01
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#define GPIO_SPEED_FAST 0x02
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#define GPIO_SPEED_HIGH 0x03
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#define GPIO_SPEED_MASK U(0x03)
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#define GPIO_NO_PULL 0x00
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#define GPIO_PULL_UP 0x01
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#define GPIO_PULL_DOWN 0x02
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#define GPIO_PULL_MASK U(0x03)
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#ifndef __ASSEMBLY__
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#include <stdint.h>
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void set_gpio(uint32_t bank, uint32_t pin, uint32_t mode, uint32_t speed,
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uint32_t pull, uint32_t alternate);
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#endif /*__ASSEMBLY__*/
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#endif /*__PLAT_GPIO_H__*/
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@ -21,5 +21,6 @@ uint32_t fdt_read_uint32_default(int node, const char *prop_name,
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uint32_t dflt_value);
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int fdt_read_uint32_array(int node, const char *prop_name,
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uint32_t *array, uint32_t count);
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int dt_set_pinctrl_config(int node);
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#endif /* __STM32MP1_DT_H__ */
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@ -41,6 +41,7 @@ PLAT_BL_COMMON_SOURCES += ${LIBFDT_SRCS} \
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drivers/delay_timer/generic_delay_timer.c \
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drivers/st/clk/stm32mp1_clk.c \
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drivers/st/clk/stm32mp1_clkfunc.c \
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drivers/st/gpio/stm32_gpio.c \
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drivers/st/reset/stm32mp1_reset.c \
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plat/st/stm32mp1/stm32mp1_dt.c \
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plat/st/stm32mp1/stm32mp1_helper.S
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@ -8,6 +8,7 @@
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#include <debug.h>
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#include <libfdt.h>
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#include <platform_def.h>
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#include <stm32_gpio.h>
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#include <stm32mp1_clk.h>
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#include <stm32mp1_clkfunc.h>
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#include <stm32mp1_dt.h>
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@ -22,6 +23,120 @@ static int fdt_checked;
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static void *fdt = (void *)(uintptr_t)STM32MP1_DTB_BASE;
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/*******************************************************************************
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* This function gets the pin settings from DT information.
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* When analyze and parsing is done, set the GPIO registers.
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* Return 0 on success, else return a negative FDT_ERR_xxx error code.
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******************************************************************************/
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static int dt_set_gpio_config(int node)
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{
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const fdt32_t *cuint, *slewrate;
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int len, pinctrl_node, pinctrl_subnode;
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uint32_t i;
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uint32_t speed = GPIO_SPEED_LOW;
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uint32_t pull = GPIO_NO_PULL;
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cuint = fdt_getprop(fdt, node, "pinmux", &len);
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if (cuint == NULL) {
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return -FDT_ERR_NOTFOUND;
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}
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pinctrl_node = fdt_parent_offset(fdt, fdt_parent_offset(fdt, node));
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if (pinctrl_node < 0) {
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return -FDT_ERR_NOTFOUND;
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}
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slewrate = fdt_getprop(fdt, node, "slew-rate", NULL);
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if (slewrate != NULL) {
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speed = fdt32_to_cpu(*slewrate);
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}
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if (fdt_getprop(fdt, node, "bias-pull-up", NULL) != NULL) {
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pull = GPIO_PULL_UP;
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} else if (fdt_getprop(fdt, node, "bias-pull-down", NULL) != NULL) {
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pull = GPIO_PULL_DOWN;
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} else {
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VERBOSE("No bias configured in node %d\n", node);
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}
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for (i = 0; i < ((uint32_t)len / sizeof(uint32_t)); i++) {
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uint32_t pincfg;
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uint32_t bank;
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uint32_t pin;
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uint32_t mode;
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uint32_t alternate = GPIO_ALTERNATE_0;
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pincfg = fdt32_to_cpu(*cuint);
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cuint++;
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bank = (pincfg & DT_GPIO_BANK_MASK) >> DT_GPIO_BANK_SHIFT;
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pin = (pincfg & DT_GPIO_PIN_MASK) >> DT_GPIO_PIN_SHIFT;
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mode = pincfg & DT_GPIO_MODE_MASK;
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switch (mode) {
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case 0:
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mode = GPIO_MODE_INPUT;
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break;
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case 1 ... 16:
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alternate = mode - 1U;
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mode = GPIO_MODE_ALTERNATE;
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break;
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case 17:
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mode = GPIO_MODE_ANALOG;
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break;
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default:
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mode = GPIO_MODE_OUTPUT;
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break;
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}
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if (fdt_getprop(fdt, node, "drive-open-drain", NULL) != NULL) {
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mode |= GPIO_OPEN_DRAIN;
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}
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fdt_for_each_subnode(pinctrl_subnode, fdt, pinctrl_node) {
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uint32_t bank_offset;
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const fdt32_t *cuint2;
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if (fdt_getprop(fdt, pinctrl_subnode,
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"gpio-controller", NULL) == NULL) {
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continue;
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}
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cuint2 = fdt_getprop(fdt, pinctrl_subnode, "reg", NULL);
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if (cuint2 == NULL) {
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continue;
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}
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if (bank == GPIO_BANK_Z) {
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bank_offset = 0;
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} else {
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bank_offset = bank * STM32_GPIO_BANK_OFFSET;
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}
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if (fdt32_to_cpu(*cuint2) == bank_offset) {
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int clk_id = fdt_get_clock_id(pinctrl_subnode);
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if (clk_id < 0) {
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return -FDT_ERR_NOTFOUND;
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}
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if (stm32mp1_clk_enable((unsigned long)clk_id) <
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0) {
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return -FDT_ERR_BADVALUE;
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}
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break;
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}
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}
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set_gpio(bank, pin, mode, speed, pull, alternate);
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}
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return 0;
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}
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/*******************************************************************************
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* This function checks device tree file with its header.
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* Returns 0 if success, and a negative value else.
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@ -151,3 +266,46 @@ int fdt_read_uint32_array(int node, const char *prop_name, uint32_t *array,
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return 0;
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}
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/*******************************************************************************
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* This function gets the pin settings from DT information.
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* When analyze and parsing is done, set the GPIO registers.
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* Returns 0 if success, and a negative value else.
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******************************************************************************/
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int dt_set_pinctrl_config(int node)
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{
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const fdt32_t *cuint;
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int lenp = 0;
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uint32_t i;
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if (!fdt_check_status(node)) {
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return -FDT_ERR_NOTFOUND;
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}
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cuint = fdt_getprop(fdt, node, "pinctrl-0", &lenp);
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if (cuint == NULL) {
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return -FDT_ERR_NOTFOUND;
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}
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for (i = 0; i < ((uint32_t)lenp / 4U); i++) {
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int phandle_node, phandle_subnode;
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phandle_node =
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fdt_node_offset_by_phandle(fdt, fdt32_to_cpu(*cuint));
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if (phandle_node < 0) {
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return -FDT_ERR_NOTFOUND;
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}
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fdt_for_each_subnode(phandle_subnode, fdt, phandle_node) {
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int ret = dt_set_gpio_config(phandle_subnode);
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if (ret < 0) {
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return ret;
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}
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}
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cuint++;
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}
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return 0;
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}
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