From ab0450f34dec1635f2a548f8331e9b095082a419 Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Mon, 15 Apr 2024 09:05:34 +0100 Subject: [PATCH 01/11] refactor(tc): introduce a new macro ADDRESSIFY() Now some macros (e.g., MHU_RX_ADDR(0x), MHU_TX_ADDR(0x), etc) add the prefix '0x' at the beginning of the addresses for hexadecimal values. For better readability, this patch introduces a new macro ADDRESSIFY(), which explictly adds the prefix '0x' for hexadecimal values. With this new macro, address macros can drop the parameter and be simplified to hexadecimal address value. Change-Id: Idd1af0394f6ef8288fbff1fd4d86b1709d1c1d16 Signed-off-by: Leo Yan --- fdts/tc-common.dtsi | 9 +++++++++ fdts/tc.dts | 14 ++++++++------ fdts/tc_vers.dtsi | 14 +++++++------- 3 files changed, 24 insertions(+), 13 deletions(-) create mode 100644 fdts/tc-common.dtsi diff --git a/fdts/tc-common.dtsi b/fdts/tc-common.dtsi new file mode 100644 index 000000000..c3311930a --- /dev/null +++ b/fdts/tc-common.dtsi @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2023-2024, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#define PASTER(x, y) x ## y +#define EVALUATOR(x, y) PASTER(x, y) +#define ADDRESSIFY(addr) EVALUATOR(0x, addr) diff --git a/fdts/tc.dts b/fdts/tc.dts index 63f6c3dd7..032c45231 100644 --- a/fdts/tc.dts +++ b/fdts/tc.dts @@ -9,6 +9,8 @@ #include #include #include "platform_def.h" + +#include "tc-common.dtsi" #include "tc_vers.dtsi" #if TARGET_FLAVOUR_FVP #include "tc_fvp.dtsi" @@ -386,9 +388,9 @@ }; }; - mbox_db_rx: mhu@MHU_RX_ADDR() { + mbox_db_rx: mhu@MHU_RX_ADDR { compatible = "arm,mhuv2-rx","arm,primecell"; - reg = <0x0 MHU_RX_ADDR(0x) 0x0 0x1000>; + reg = <0x0 ADDRESSIFY(MHU_RX_ADDR) 0x0 0x1000>; clocks = <&soc_refclk>; clock-names = "apb_pclk"; #mbox-cells = <2>; @@ -398,9 +400,9 @@ arm,mhuv2-protocols = <0 1>; }; - mbox_db_tx: mhu@MHU_TX_ADDR() { + mbox_db_tx: mhu@MHU_TX_ADDR { compatible = "arm,mhuv2-tx","arm,primecell"; - reg = <0x0 MHU_TX_ADDR(0x) 0x0 0x1000>; + reg = <0x0 ADDRESSIFY(MHU_TX_ADDR) 0x0 0x1000>; clocks = <&soc_refclk>; clock-names = "apb_pclk"; #mbox-cells = <2>; @@ -606,11 +608,11 @@ }; #endif /* TC_IOMMU_EN */ - dp0: display@DPU_ADDR() { + dp0: display@DPU_ADDR { #address-cells = <1>; #size-cells = <0>; compatible = "arm,mali-d71"; - reg = ; + reg = ; interrupts = ; interrupt-names = "DPU"; DPU_CLK_ATTR1; diff --git a/fdts/tc_vers.dtsi b/fdts/tc_vers.dtsi index 43fafd536..aa3c89fa8 100644 --- a/fdts/tc_vers.dtsi +++ b/fdts/tc_vers.dtsi @@ -28,8 +28,8 @@ #endif /* TARGET_FLAVOUR_FPGA */ #define INT_MBOX_RX 317 -#define MHU_TX_ADDR(pref) pref##45000000 /* hex */ -#define MHU_RX_ADDR(pref) pref##45010000 /* hex */ +#define MHU_TX_ADDR 45000000 /* hex */ +#define MHU_RX_ADDR 45010000 /* hex */ #define MPAM_ADDR 0x1 0x00010000 /* 0x1_0001_0000 */ #define UARTCLK_FREQ 5000000 #elif TARGET_PLATFORM == 3 @@ -38,8 +38,8 @@ #define MID_CAPACITY 686 #define INT_MBOX_RX 300 -#define MHU_TX_ADDR(pref) pref##46040000 /* hex */ -#define MHU_RX_ADDR(pref) pref##46140000 /* hex */ +#define MHU_TX_ADDR 46040000 /* hex */ +#define MHU_RX_ADDR 46140000 /* hex */ #define MPAM_ADDR 0x0 0x5f010000 /* 0x5f01_0000 */ #define UARTCLK_FREQ 3750000 #endif /* TARGET_PLATFORM == 3 */ @@ -63,10 +63,10 @@ #define ETH_COMPATIBLE "smsc,lan91c111" #define MMC_REMOVABLE cd-gpios = <&sysreg 0 0> #if TARGET_PLATFORM <= 2 -#define DPU_ADDR(pref) pref##2cc00000 +#define DPU_ADDR 2cc00000 #define DPU_IRQ 69 #else /* TARGET_PLATFORM >= 3 */ -#define DPU_ADDR(pref) pref##4000000000 +#define DPU_ADDR 4000000000 #define DPU_IRQ 579 #endif /* TARGET_PLATFORM >= 3 */ @@ -90,7 +90,7 @@ vsync-len = <10> #define ETH_COMPATIBLE "smsc,lan9115" #define MMC_REMOVABLE non-removable -#define DPU_ADDR(pref) pref##2cc00000 +#define DPU_ADDR 2cc00000 #define DPU_IRQ 69 #endif /* TARGET_FLAVOUR_FPGA */ From 35028bd7dadf6e20fcb5ca0ece1f695ebc6c954b Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Sun, 14 Apr 2024 21:34:59 +0100 Subject: [PATCH 02/11] refactor(tc): rename 'tc_fvp.dtsi' to 'tc-fvp.dtsi' To follow up the DT naming convention, this patch renames the file 'tc_fvp.dtsi' to 'tc-fvp.dtsi'. Change-Id: Ib74cc38eb935d3daac87fbab6de4c004b1ceddcc Signed-off-by: Leo Yan --- fdts/{tc_fvp.dtsi => tc-fvp.dtsi} | 0 fdts/tc.dts | 2 +- 2 files changed, 1 insertion(+), 1 deletion(-) rename fdts/{tc_fvp.dtsi => tc-fvp.dtsi} (100%) diff --git a/fdts/tc_fvp.dtsi b/fdts/tc-fvp.dtsi similarity index 100% rename from fdts/tc_fvp.dtsi rename to fdts/tc-fvp.dtsi diff --git a/fdts/tc.dts b/fdts/tc.dts index 032c45231..58e70ba26 100644 --- a/fdts/tc.dts +++ b/fdts/tc.dts @@ -13,7 +13,7 @@ #include "tc-common.dtsi" #include "tc_vers.dtsi" #if TARGET_FLAVOUR_FVP -#include "tc_fvp.dtsi" +#include "tc-fvp.dtsi" #endif /* TARGET_FLAVOUR_FVP */ / { From b3a9737ce042b26fa7665630e2e32b259001bfff Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Sun, 14 Apr 2024 08:27:39 +0100 Subject: [PATCH 03/11] refactor(tc): add platform specific DT files Currently, the DT binding uses the file 'tc.dts' as a central place for all TC platforms. And the variables (for different platforms, or FVP vs FPGA, etc.) are maintained in 'tc_vers.dtsi'. This patch renames 'tc.dts' to 'tc-base.dtsi' and creates an individual .dts file for every platform. The purpose is to use 'tc-base.dtsi' for maintaining common DT binding and every platform's specific definitions will be moved into its own .dts file. This is a preparation for sequential refactoring. It changes to include the header files in platform DTS files but not in the 'tc-base.dtsi'. This can allow 'tc-base.dtsi' is general enough and platform DTS files covers platform specific defintions. Change-Id: I034fb3f8836bcea36e8ad8ae01de41127693b0c6 Signed-off-by: Leo Yan --- fdts/{tc.dts => tc-base.dtsi} | 10 ---------- fdts/tc2.dts | 16 ++++++++++++++++ fdts/tc3.dts | 17 +++++++++++++++++ plat/arm/board/tc/platform.mk | 2 +- 4 files changed, 34 insertions(+), 11 deletions(-) rename fdts/{tc.dts => tc-base.dtsi} (98%) create mode 100644 fdts/tc2.dts create mode 100644 fdts/tc3.dts diff --git a/fdts/tc.dts b/fdts/tc-base.dtsi similarity index 98% rename from fdts/tc.dts rename to fdts/tc-base.dtsi index 58e70ba26..09809f06f 100644 --- a/fdts/tc.dts +++ b/fdts/tc-base.dtsi @@ -4,17 +4,7 @@ * SPDX-License-Identifier: BSD-3-Clause */ -/dts-v1/; - -#include -#include -#include "platform_def.h" - -#include "tc-common.dtsi" #include "tc_vers.dtsi" -#if TARGET_FLAVOUR_FVP -#include "tc-fvp.dtsi" -#endif /* TARGET_FLAVOUR_FVP */ / { compatible = "arm,tc"; diff --git a/fdts/tc2.dts b/fdts/tc2.dts new file mode 100644 index 000000000..42328c409 --- /dev/null +++ b/fdts/tc2.dts @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2020-2024, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +/dts-v1/; + +#include +#include +#include + +#include "tc-common.dtsi" +#if TARGET_FLAVOUR_FVP +#include "tc-fvp.dtsi" +#endif /* TARGET_FLAVOUR_FVP */ +#include "tc-base.dtsi" diff --git a/fdts/tc3.dts b/fdts/tc3.dts new file mode 100644 index 000000000..288e39dc8 --- /dev/null +++ b/fdts/tc3.dts @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2020-2024, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/dts-v1/; + +#include +#include +#include + +#include "tc-common.dtsi" +#if TARGET_FLAVOUR_FVP +#include "tc-fvp.dtsi" +#endif /* TARGET_FLAVOUR_FVP */ +#include "tc-base.dtsi" diff --git a/plat/arm/board/tc/platform.mk b/plat/arm/board/tc/platform.mk index 8756f3195..4acac9e64 100644 --- a/plat/arm/board/tc/platform.mk +++ b/plat/arm/board/tc/platform.mk @@ -162,7 +162,7 @@ $(eval $(call TOOL_ADD_PAYLOAD,${TC_TOS_FW_CONFIG},--tos-fw-config,${TC_TOS_FW_C endif #Device tree -TC_HW_CONFIG_DTS := fdts/tc.dts +TC_HW_CONFIG_DTS := fdts/${PLAT}${TARGET_PLATFORM}.dts TC_HW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}.dtb FDT_SOURCES += ${TC_HW_CONFIG_DTS} $(eval TC_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(TC_HW_CONFIG_DTS))) From defcfb2b6369c8b5ab0f166b6a145cf499ab5d51 Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Wed, 24 Apr 2024 09:53:21 +0100 Subject: [PATCH 04/11] refactor(tc): move out platform specific code from tc_vers.dtsi Since now every TC board has its own dts file, this patch moves out the platform specific code from tc_vers.dtsi to the corresponding platform dts file. Change-Id: I62e0872eddb2ae18e666a3f8dc0118a539651a9c Signed-off-by: Leo Yan --- fdts/tc2.dts | 28 +++++++++++++++++++++++++++ fdts/tc3.dts | 18 ++++++++++++++++++ fdts/tc_vers.dtsi | 48 ----------------------------------------------- 3 files changed, 46 insertions(+), 48 deletions(-) diff --git a/fdts/tc2.dts b/fdts/tc2.dts index 42328c409..bff3f1ac4 100644 --- a/fdts/tc2.dts +++ b/fdts/tc2.dts @@ -9,8 +9,36 @@ #include #include +#if TARGET_FLAVOUR_FVP +#define LIT_CAPACITY 406 +#define MID_CAPACITY 912 +#else /* TARGET_FLAVOUR_FPGA */ +#define LIT_CAPACITY 280 +#define MID_CAPACITY 775 +/* this is an area optimized configuration of the big core */ +#define BIG2_CAPACITY 930 +#endif /* TARGET_FLAVOUR_FPGA */ +#define BIG_CAPACITY 1024 + +#define INT_MBOX_RX 317 +#define MHU_TX_ADDR 45000000 /* hex */ +#define MHU_RX_ADDR 45010000 /* hex */ +#define MPAM_ADDR 0x1 0x00010000 /* 0x1_0001_0000 */ +#define UARTCLK_FREQ 5000000 + +#define DPU_ADDR 2cc00000 +#define DPU_IRQ 69 + #include "tc-common.dtsi" #if TARGET_FLAVOUR_FVP #include "tc-fvp.dtsi" #endif /* TARGET_FLAVOUR_FVP */ #include "tc-base.dtsi" + +/ { + cmn-pmu { + compatible = "arm,ci-700"; + reg = <0x0 0x50000000 0x0 0x10000000>; + interrupts = ; + }; +}; diff --git a/fdts/tc3.dts b/fdts/tc3.dts index 288e39dc8..2432b8187 100644 --- a/fdts/tc3.dts +++ b/fdts/tc3.dts @@ -10,6 +10,24 @@ #include #include +#define LIT_CAPACITY 239 +#define MID_CAPACITY 686 +#define BIG_CAPACITY 1024 + +#define INT_MBOX_RX 300 +#define MHU_TX_ADDR 46040000 /* hex */ +#define MHU_RX_ADDR 46140000 /* hex */ +#define MPAM_ADDR 0x0 0x5f010000 /* 0x5f01_0000 */ +#define UARTCLK_FREQ 3750000 + +#if TARGET_FLAVOUR_FVP +#define DPU_ADDR 4000000000 +#define DPU_IRQ 579 +#elif TARGET_FLAVOUR_FPGA +#define DPU_ADDR 2cc00000 +#define DPU_IRQ 69 +#endif + #include "tc-common.dtsi" #if TARGET_FLAVOUR_FVP #include "tc-fvp.dtsi" diff --git a/fdts/tc_vers.dtsi b/fdts/tc_vers.dtsi index aa3c89fa8..14bc8205d 100644 --- a/fdts/tc_vers.dtsi +++ b/fdts/tc_vers.dtsi @@ -13,37 +13,6 @@ #define DPU_SCMI_PD_IDX (PLAT_MAX_CPUS_PER_CLUSTER + 2) #endif /* TC_SCMI_PD_CTRL_EN */ -/* All perf is normalized against the big core */ -#define BIG_CAPACITY 1024 - -#if TARGET_PLATFORM <= 2 -#if TARGET_FLAVOUR_FVP -#define LIT_CAPACITY 406 -#define MID_CAPACITY 912 -#else /* TARGET_FLAVOUR_FPGA */ -#define LIT_CAPACITY 280 -#define MID_CAPACITY 775 -/* this is an area optimized configuration of the big core */ -#define BIG2_CAPACITY 930 -#endif /* TARGET_FLAVOUR_FPGA */ - -#define INT_MBOX_RX 317 -#define MHU_TX_ADDR 45000000 /* hex */ -#define MHU_RX_ADDR 45010000 /* hex */ -#define MPAM_ADDR 0x1 0x00010000 /* 0x1_0001_0000 */ -#define UARTCLK_FREQ 5000000 -#elif TARGET_PLATFORM == 3 - -#define LIT_CAPACITY 239 -#define MID_CAPACITY 686 - -#define INT_MBOX_RX 300 -#define MHU_TX_ADDR 46040000 /* hex */ -#define MHU_RX_ADDR 46140000 /* hex */ -#define MPAM_ADDR 0x0 0x5f010000 /* 0x5f01_0000 */ -#define UARTCLK_FREQ 3750000 -#endif /* TARGET_PLATFORM == 3 */ - #if TARGET_FLAVOUR_FVP #define STDOUT_PATH "serial0:115200n8" #define GIC_CTRL_ADDR 2c010000 @@ -62,13 +31,6 @@ vsync-len = <2> #define ETH_COMPATIBLE "smsc,lan91c111" #define MMC_REMOVABLE cd-gpios = <&sysreg 0 0> -#if TARGET_PLATFORM <= 2 -#define DPU_ADDR 2cc00000 -#define DPU_IRQ 69 -#else /* TARGET_PLATFORM >= 3 */ -#define DPU_ADDR 4000000000 -#define DPU_IRQ 579 -#endif /* TARGET_PLATFORM >= 3 */ #else /* TARGET_FLAVOUR_FPGA */ @@ -90,8 +52,6 @@ vsync-len = <10> #define ETH_COMPATIBLE "smsc,lan9115" #define MMC_REMOVABLE non-removable -#define DPU_ADDR 2cc00000 -#define DPU_IRQ 69 #endif /* TARGET_FLAVOUR_FPGA */ /* Use SCMI controlled clocks */ @@ -121,14 +81,6 @@ #endif /* !TC_DPU_USE_SCMI_CLK */ / { -#if TARGET_PLATFORM <= 2 - cmn-pmu { - compatible = "arm,ci-700"; - reg = <0x0 0x50000000 0x0 0x10000000>; - interrupts = ; - }; -#endif /* TARGET_PLATFORM <= 2 */ - #if !TC_DPU_USE_SCMI_CLK dpu_aclk: dpu_aclk { compatible = "fixed-clock"; From f9565b2af1a866577f3045070275c8fc3b376729 Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Sun, 14 Apr 2024 22:09:34 +0100 Subject: [PATCH 05/11] refactor(tc): move out platform specific DT binding from tc-base.dtsi The main purpose of 'tc-base.dtsi' is for common DT bindings, however, it contains bindings for platform specific. This patch moves out these plaform specific bindings to 'tc2.dts' and 'tc3.dts' respectively. Change-Id: I9355eeff539a3f2940190aef399b4fb4828cbbac Signed-off-by: Leo Yan --- fdts/tc-base.dtsi | 158 -------------------------------------------- fdts/tc2.dts | 165 ++++++++++++++++++++++++++++++++++++++++++++++ fdts/tc3.dts | 29 ++++++++ 3 files changed, 194 insertions(+), 158 deletions(-) diff --git a/fdts/tc-base.dtsi b/fdts/tc-base.dtsi index 09809f06f..7d5a8dd14 100644 --- a/fdts/tc-base.dtsi +++ b/fdts/tc-base.dtsi @@ -62,26 +62,6 @@ core7 { cpu = <&CPU7>; }; -#if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 - core8 { - cpu = <&CPU8>; - }; - core9 { - cpu = <&CPU9>; - }; - core10 { - cpu = <&CPU10>; - }; - core11 { - cpu = <&CPU11>; - }; - core12 { - cpu = <&CPU12>; - }; - core13 { - cpu = <&CPU13>; - }; -#endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 */ }; }; @@ -162,13 +142,6 @@ reg = <0x200>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; -#if TARGET_PLATFORM <= 2 - clocks = <&scmi_dvfs 0>; - capacity-dmips-mhz = ; -#elif TARGET_PLATFORM == 3 - clocks = <&scmi_dvfs 1>; - capacity-dmips-mhz = ; -#endif /* TARGET_PLATFORM == 3 */ amu = <&amu>; supports-mpmm; }; @@ -179,13 +152,6 @@ reg = <0x300>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; -#if TARGET_PLATFORM <= 2 - clocks = <&scmi_dvfs 0>; - capacity-dmips-mhz = ; -#elif TARGET_PLATFORM == 3 - clocks = <&scmi_dvfs 1>; - capacity-dmips-mhz = ; -#endif /* TARGET_PLATFORM == 3 */ amu = <&amu>; supports-mpmm; }; @@ -220,13 +186,6 @@ reg = <0x600>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; -#if TARGET_PLATFORM <= 2 - clocks = <&scmi_dvfs 1>; - capacity-dmips-mhz = ; -#elif TARGET_PLATFORM == 3 - clocks = <&scmi_dvfs 2>; - capacity-dmips-mhz = ; -#endif /* TARGET_PLATFORM == 3 */ amu = <&amu>; supports-mpmm; }; @@ -237,84 +196,9 @@ reg = <0x700>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; -#if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 - clocks = <&scmi_dvfs 1>; - capacity-dmips-mhz = ; -#else - clocks = <&scmi_dvfs 2>; - capacity-dmips-mhz = ; -#endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 */ amu = <&amu>; supports-mpmm; }; - -#if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 - CPU8:cpu@800 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x800>; - enable-method = "psci"; - clocks = <&scmi_dvfs 1>; - capacity-dmips-mhz = ; - amu = <&amu>; - supports-mpmm; - }; - - CPU9:cpu@900 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x900>; - enable-method = "psci"; - clocks = <&scmi_dvfs 2>; - capacity-dmips-mhz = ; - amu = <&amu>; - supports-mpmm; - }; - - CPU10:cpu@A00 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0xA00>; - enable-method = "psci"; - clocks = <&scmi_dvfs 2>; - capacity-dmips-mhz = ; - amu = <&amu>; - supports-mpmm; - }; - - CPU11:cpu@B00 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0xB00>; - enable-method = "psci"; - clocks = <&scmi_dvfs 2>; - capacity-dmips-mhz = ; - amu = <&amu>; - supports-mpmm; - }; - - CPU12:cpu@C00 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0xC00>; - enable-method = "psci"; - clocks = <&scmi_dvfs 3>; - capacity-dmips-mhz = ; - amu = <&amu>; - supports-mpmm; - }; - - CPU13:cpu@D00 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0xD00>; - enable-method = "psci"; - clocks = <&scmi_dvfs 3>; - capacity-dmips-mhz = ; - amu = <&amu>; - supports-mpmm; - }; -#endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 */ }; reserved-memory { @@ -355,13 +239,6 @@ cpu-pmu { compatible = "arm,armv8-pmuv3"; interrupts = ; - interrupt-affinity = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>, - <&CPU4>, <&CPU5>, <&CPU6>, <&CPU7> -#if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 - ,<&CPU8>, <&CPU9>, <&CPU10>, <&CPU11>, - <&CPU12>, <&CPU13> -#endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 */ - ; }; sram: sram@6000000 { @@ -609,9 +486,6 @@ #if TC_IOMMU_EN iommus = <&smmu_700 0x100>; #endif /* TC_IOMMU_EN */ -#if TC_SCMI_PD_CTRL_EN && (TARGET_PLATFORM != 3) - power-domains = <&scmi_devpd DPU_SCMI_PD_IDX>; -#endif /* TC_SCMI_PD_CTRL_EN && (TARGET_PLATFORM != 3) */ pl0: pipeline@0 { reg = <0>; @@ -692,38 +566,6 @@ cpu = <&CPU7>; }; -#if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 - ete8 { - compatible = "arm,embedded-trace-extension"; - cpu = <&CPU8>; - }; - - ete9 { - compatible = "arm,embedded-trace-extension"; - cpu = <&CPU9>; - }; - - ete10 { - compatible = "arm,embedded-trace-extension"; - cpu = <&CPU10>; - }; - - ete11 { - compatible = "arm,embedded-trace-extension"; - cpu = <&CPU11>; - }; - - ete12 { - compatible = "arm,embedded-trace-extension"; - cpu = <&CPU12>; - }; - - ete13 { - compatible = "arm,embedded-trace-extension"; - cpu = <&CPU13>; - }; -#endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 */ - trbe { compatible = "arm,trace-buffer-extension"; interrupts = ; diff --git a/fdts/tc2.dts b/fdts/tc2.dts index bff3f1ac4..b6acdaa18 100644 --- a/fdts/tc2.dts +++ b/fdts/tc2.dts @@ -36,9 +36,174 @@ #include "tc-base.dtsi" / { + cpus { +#if TARGET_FLAVOUR_FPGA + cpu-map { + cluster0 { + core8 { + cpu = <&CPU8>; + }; + core9 { + cpu = <&CPU9>; + }; + core10 { + cpu = <&CPU10>; + }; + core11 { + cpu = <&CPU11>; + }; + core12 { + cpu = <&CPU12>; + }; + core13 { + cpu = <&CPU13>; + }; + }; + }; +#endif + + CPU2:cpu@200 { + clocks = <&scmi_dvfs 0>; + capacity-dmips-mhz = ; + }; + + CPU3:cpu@300 { + clocks = <&scmi_dvfs 0>; + capacity-dmips-mhz = ; + }; + + CPU6:cpu@600 { + clocks = <&scmi_dvfs 1>; + capacity-dmips-mhz = ; + }; + + CPU7:cpu@700 { + clocks = <&scmi_dvfs 1>; + capacity-dmips-mhz = ; + }; + +#if TARGET_FLAVOUR_FPGA + CPU8:cpu@800 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x800>; + enable-method = "psci"; + clocks = <&scmi_dvfs 1>; + capacity-dmips-mhz = ; + amu = <&amu>; + supports-mpmm; + }; + + CPU9:cpu@900 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x900>; + enable-method = "psci"; + clocks = <&scmi_dvfs 2>; + capacity-dmips-mhz = ; + amu = <&amu>; + supports-mpmm; + }; + + CPU10:cpu@A00 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0xA00>; + enable-method = "psci"; + clocks = <&scmi_dvfs 2>; + capacity-dmips-mhz = ; + amu = <&amu>; + supports-mpmm; + }; + + CPU11:cpu@B00 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0xB00>; + enable-method = "psci"; + clocks = <&scmi_dvfs 2>; + capacity-dmips-mhz = ; + amu = <&amu>; + supports-mpmm; + }; + + CPU12:cpu@C00 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0xC00>; + enable-method = "psci"; + clocks = <&scmi_dvfs 3>; + capacity-dmips-mhz = ; + amu = <&amu>; + supports-mpmm; + }; + + CPU13:cpu@D00 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0xD00>; + enable-method = "psci"; + clocks = <&scmi_dvfs 3>; + capacity-dmips-mhz = ; + amu = <&amu>; + supports-mpmm; + }; +#endif + }; + +#if TARGET_FLAVOUR_FPGA + ete8 { + compatible = "arm,embedded-trace-extension"; + cpu = <&CPU8>; + }; + + ete9 { + compatible = "arm,embedded-trace-extension"; + cpu = <&CPU9>; + }; + + ete10 { + compatible = "arm,embedded-trace-extension"; + cpu = <&CPU10>; + }; + + ete11 { + compatible = "arm,embedded-trace-extension"; + cpu = <&CPU11>; + }; + + ete12 { + compatible = "arm,embedded-trace-extension"; + cpu = <&CPU12>; + }; + + ete13 { + compatible = "arm,embedded-trace-extension"; + cpu = <&CPU13>; + }; +#endif /* TARGET_FLAVOUR_FPGA */ + + cpu-pmu { +#if TARGET_FLAVOUR_FPGA + interrupt-affinity = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>, + <&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>, + <&CPU8>, <&CPU9>, <&CPU10>, <&CPU11>, + <&CPU12>, <&CPU13>; +#else + interrupt-affinity = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>, + <&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>; +#endif + }; + cmn-pmu { compatible = "arm,ci-700"; reg = <0x0 0x50000000 0x0 0x10000000>; interrupts = ; }; + + dp0: display@DPU_ADDR { +#if TC_SCMI_PD_CTRL_EN + power-domains = <&scmi_devpd (PLAT_MAX_CPUS_PER_CLUSTER + 2)>; +#endif + }; }; diff --git a/fdts/tc3.dts b/fdts/tc3.dts index 2432b8187..5522210d7 100644 --- a/fdts/tc3.dts +++ b/fdts/tc3.dts @@ -33,3 +33,32 @@ #include "tc-fvp.dtsi" #endif /* TARGET_FLAVOUR_FVP */ #include "tc-base.dtsi" + +/ { + cpus { + CPU2:cpu@200 { + clocks = <&scmi_dvfs 1>; + capacity-dmips-mhz = ; + }; + + CPU3:cpu@300 { + clocks = <&scmi_dvfs 1>; + capacity-dmips-mhz = ; + }; + + CPU6:cpu@600 { + clocks = <&scmi_dvfs 2>; + capacity-dmips-mhz = ; + }; + + CPU7:cpu@700 { + clocks = <&scmi_dvfs 2>; + capacity-dmips-mhz = ; + }; + }; + + cpu-pmu { + interrupt-affinity = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>, + <&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>; + }; +}; From 4e772e6ba3b04f4d18e4f1e3341f86a49b1cfcc8 Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Wed, 24 Apr 2024 09:57:28 +0100 Subject: [PATCH 06/11] refactor(tc): introduce a new file tc-fpga.dtsi A Total Compute platform supports FVP and FPGA target. And it's possible that these two targets have different hardware components. For this reason, this patch introduces a new file tc-fpga.dtsi for FPGA related DT binding. As a result, this patch moves out FVP and FPGA specific macros into tc-fvp.dtsi and tc-fpga.dtsi respectively. Change-Id: I48d7d30d0c500cec5500f1a2a680e8b3a276ea99 Signed-off-by: Leo Yan --- fdts/tc-fpga.dtsi | 24 ++++++++++++++++++++++++ fdts/tc-fvp.dtsi | 18 ++++++++++++++++++ fdts/tc2.dts | 2 ++ fdts/tc3.dts | 2 ++ fdts/tc_vers.dtsi | 41 ----------------------------------------- 5 files changed, 46 insertions(+), 41 deletions(-) create mode 100644 fdts/tc-fpga.dtsi diff --git a/fdts/tc-fpga.dtsi b/fdts/tc-fpga.dtsi new file mode 100644 index 000000000..f5bda29df --- /dev/null +++ b/fdts/tc-fpga.dtsi @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2023-2024, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#define STDOUT_PATH "serial0:38400n8" +#define GIC_CTRL_ADDR 30000000 +#define GIC_GICR_OFFSET 0x1000000 +#define UART_OFFSET 0x10000 +/* 1440x3200@120 framebuffer */ +#define VENCODER_TIMING_CLK 836000000 +#define VENCODER_TIMING \ + clock-frequency = ; \ + hactive = <1440>; \ + vactive = <3200>; \ + hfront-porch = <136>; \ + hback-porch = <296>; \ + hsync-len = <160>; \ + vfront-porch = <3>; \ + vback-porch = <217>; \ + vsync-len = <10> +#define ETH_COMPATIBLE "smsc,lan9115" +#define MMC_REMOVABLE non-removable diff --git a/fdts/tc-fvp.dtsi b/fdts/tc-fvp.dtsi index 42f38180e..22a4f5311 100644 --- a/fdts/tc-fvp.dtsi +++ b/fdts/tc-fvp.dtsi @@ -4,6 +4,24 @@ * SPDX-License-Identifier: BSD-3-Clause */ +#define STDOUT_PATH "serial0:115200n8" +#define GIC_CTRL_ADDR 2c010000 +#define GIC_GICR_OFFSET 0x200000 +#define UART_OFFSET 0x1000 +#define VENCODER_TIMING_CLK 25175000 +#define VENCODER_TIMING \ + clock-frequency = ; \ + hactive = <640>; \ + vactive = <480>; \ + hfront-porch = <16>; \ + hback-porch = <48>; \ + hsync-len = <96>; \ + vfront-porch = <10>; \ + vback-porch = <33>; \ + vsync-len = <2> +#define ETH_COMPATIBLE "smsc,lan91c111" +#define MMC_REMOVABLE cd-gpios = <&sysreg 0 0> + / { rtc@1c170000 { compatible = "arm,pl031", "arm,primecell"; diff --git a/fdts/tc2.dts b/fdts/tc2.dts index b6acdaa18..d1343e581 100644 --- a/fdts/tc2.dts +++ b/fdts/tc2.dts @@ -32,6 +32,8 @@ #include "tc-common.dtsi" #if TARGET_FLAVOUR_FVP #include "tc-fvp.dtsi" +#else +#include "tc-fpga.dtsi" #endif /* TARGET_FLAVOUR_FVP */ #include "tc-base.dtsi" diff --git a/fdts/tc3.dts b/fdts/tc3.dts index 5522210d7..52b0856f6 100644 --- a/fdts/tc3.dts +++ b/fdts/tc3.dts @@ -31,6 +31,8 @@ #include "tc-common.dtsi" #if TARGET_FLAVOUR_FVP #include "tc-fvp.dtsi" +#else +#include "tc-fpga.dtsi" #endif /* TARGET_FLAVOUR_FVP */ #include "tc-base.dtsi" diff --git a/fdts/tc_vers.dtsi b/fdts/tc_vers.dtsi index 14bc8205d..2b8675e6e 100644 --- a/fdts/tc_vers.dtsi +++ b/fdts/tc_vers.dtsi @@ -13,47 +13,6 @@ #define DPU_SCMI_PD_IDX (PLAT_MAX_CPUS_PER_CLUSTER + 2) #endif /* TC_SCMI_PD_CTRL_EN */ -#if TARGET_FLAVOUR_FVP -#define STDOUT_PATH "serial0:115200n8" -#define GIC_CTRL_ADDR 2c010000 -#define GIC_GICR_OFFSET 0x200000 -#define UART_OFFSET 0x1000 -#define VENCODER_TIMING_CLK 25175000 -#define VENCODER_TIMING \ - clock-frequency = ; \ - hactive = <640>; \ - vactive = <480>; \ - hfront-porch = <16>; \ - hback-porch = <48>; \ - hsync-len = <96>; \ - vfront-porch = <10>; \ - vback-porch = <33>; \ - vsync-len = <2> -#define ETH_COMPATIBLE "smsc,lan91c111" -#define MMC_REMOVABLE cd-gpios = <&sysreg 0 0> - -#else /* TARGET_FLAVOUR_FPGA */ - -#define STDOUT_PATH "serial0:38400n8" -#define GIC_CTRL_ADDR 30000000 -#define GIC_GICR_OFFSET 0x1000000 -#define UART_OFFSET 0x10000 -/* 1440x3200@120 framebuffer */ -#define VENCODER_TIMING_CLK 836000000 -#define VENCODER_TIMING \ - clock-frequency = ; \ - hactive = <1440>; \ - vactive = <3200>; \ - hfront-porch = <136>; \ - hback-porch = <296>; \ - hsync-len = <160>; \ - vfront-porch = <3>; \ - vback-porch = <217>; \ - vsync-len = <10> -#define ETH_COMPATIBLE "smsc,lan9115" -#define MMC_REMOVABLE non-removable -#endif /* TARGET_FLAVOUR_FPGA */ - /* Use SCMI controlled clocks */ #if TC_DPU_USE_SCMI_CLK #define DPU_CLK_ATTR1 \ From 79c6ede09a21ea599bbfee23e4de64bada513e97 Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Wed, 24 Apr 2024 10:03:50 +0100 Subject: [PATCH 07/11] refactor(tc): move SCMI clock DT binding into tc-base.dtsi As SCMI clock DT bindings are common for TC platforms, move them into 'tc-base.dtsi'. As a result, the file 'tc_vers.dtsi' is empty, so removes it. Change-Id: Iaa7219bbbde8458dcfe01de7ad6c277a960357c5 Signed-off-by: Leo Yan --- fdts/tc-base.dtsi | 48 ++++++++++++++++++++++++++++++++++++++- fdts/tc_vers.dtsi | 58 ----------------------------------------------- 2 files changed, 47 insertions(+), 59 deletions(-) delete mode 100644 fdts/tc_vers.dtsi diff --git a/fdts/tc-base.dtsi b/fdts/tc-base.dtsi index 7d5a8dd14..15e4a002e 100644 --- a/fdts/tc-base.dtsi +++ b/fdts/tc-base.dtsi @@ -4,7 +4,37 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#include "tc_vers.dtsi" +/* If SCMI power domain control is enabled */ +#if TC_SCMI_PD_CTRL_EN +#define GPU_SCMI_PD_IDX (PLAT_MAX_CPUS_PER_CLUSTER + 1) +#define DPU_SCMI_PD_IDX (PLAT_MAX_CPUS_PER_CLUSTER + 2) +#endif /* TC_SCMI_PD_CTRL_EN */ + +/* Use SCMI controlled clocks */ +#if TC_DPU_USE_SCMI_CLK +#define DPU_CLK_ATTR1 \ + clocks = <&scmi_clk 0>; \ + clock-names = "aclk" + +#define DPU_CLK_ATTR2 \ + clocks = <&scmi_clk 1>; \ + clock-names = "pxclk" + +#define DPU_CLK_ATTR3 \ + clocks = <&scmi_clk 2>; \ + clock-names = "pxclk" \ +/* Use fixed clocks */ +#else /* !TC_DPU_USE_SCMI_CLK */ +#define DPU_CLK_ATTR1 \ + clocks = <&dpu_aclk>; \ + clock-names = "aclk" + +#define DPU_CLK_ATTR2 \ + clocks = <&dpu_pixel_clk>, <&dpu_aclk>; \ + clock-names = "pxclk", "aclk" + +#define DPU_CLK_ATTR3 DPU_CLK_ATTR2 +#endif /* !TC_DPU_USE_SCMI_CLK */ / { compatible = "arm,tc"; @@ -355,6 +385,22 @@ status = "okay"; }; +#if !TC_DPU_USE_SCMI_CLK + dpu_aclk: dpu_aclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = ; + clock-output-names = "fpga:dpu_aclk"; + }; + + dpu_pixel_clk: dpu-pixel-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = ; + clock-output-names = "pxclk"; + }; +#endif /* !TC_DPU_USE_SCMI_CLK */ + vencoder { compatible = "drm,virtual-encoder"; port { diff --git a/fdts/tc_vers.dtsi b/fdts/tc_vers.dtsi deleted file mode 100644 index 2b8675e6e..000000000 --- a/fdts/tc_vers.dtsi +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright (c) 2023-2024, Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include - -/* If SCMI power domain control is enabled */ -#if TC_SCMI_PD_CTRL_EN -#define GPU_SCMI_PD_IDX (PLAT_MAX_CPUS_PER_CLUSTER + 1) -#define DPU_SCMI_PD_IDX (PLAT_MAX_CPUS_PER_CLUSTER + 2) -#endif /* TC_SCMI_PD_CTRL_EN */ - -/* Use SCMI controlled clocks */ -#if TC_DPU_USE_SCMI_CLK -#define DPU_CLK_ATTR1 \ - clocks = <&scmi_clk 0>; \ - clock-names = "aclk" - -#define DPU_CLK_ATTR2 \ - clocks = <&scmi_clk 1>; \ - clock-names = "pxclk" - -#define DPU_CLK_ATTR3 \ - clocks = <&scmi_clk 2>; \ - clock-names = "pxclk" \ -/* Use fixed clocks */ -#else /* !TC_DPU_USE_SCMI_CLK */ -#define DPU_CLK_ATTR1 \ - clocks = <&dpu_aclk>; \ - clock-names = "aclk" - -#define DPU_CLK_ATTR2 \ - clocks = <&dpu_pixel_clk>, <&dpu_aclk>; \ - clock-names = "pxclk", "aclk" - -#define DPU_CLK_ATTR3 DPU_CLK_ATTR2 -#endif /* !TC_DPU_USE_SCMI_CLK */ - -/ { -#if !TC_DPU_USE_SCMI_CLK - dpu_aclk: dpu_aclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = ; - clock-output-names = "fpga:dpu_aclk"; - }; - - dpu_pixel_clk: dpu-pixel-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = ; - clock-output-names = "pxclk"; - }; -#endif /* !TC_DPU_USE_SCMI_CLK */ -}; From e6ef3ef0f637b52f60aa383bdea9a59bfc03c8e5 Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Mon, 15 Apr 2024 11:35:15 +0100 Subject: [PATCH 08/11] refactor(tc): append properties in DT bindings This patch appends properties in DT bindings to differentiate between FVP and FPGA. The related macros are no longer used, so they are removed. This patch contains minor improvement for adding labels in device nodes. Change-Id: I8d708bb7a8a9a0ed32b806abcb4e7651daadf5e6 Signed-off-by: Leo Yan --- fdts/tc-base.dtsi | 9 ++------- fdts/tc-fpga.dtsi | 18 +++++++++++++++--- fdts/tc-fvp.dtsi | 15 ++++++++++++--- 3 files changed, 29 insertions(+), 13 deletions(-) diff --git a/fdts/tc-base.dtsi b/fdts/tc-base.dtsi index 15e4a002e..79f266677 100644 --- a/fdts/tc-base.dtsi +++ b/fdts/tc-base.dtsi @@ -47,7 +47,6 @@ }; chosen { - stdout-path = STDOUT_PATH; /* * Add some dummy entropy for Linux so it * doesn't delay the boot waiting for it. @@ -417,13 +416,10 @@ }; - ethernet@18000000 { - compatible = ETH_COMPATIBLE; + ethernet: ethernet@18000000 { reg = <0x0 0x18000000 0x0 0x10000>; interrupts = ; - /* FPGA only but will work on FVP. Keep for simplicity */ - phy-mode = "mii"; reg-io-width = <2>; smsc,irq-push-pull; }; @@ -451,12 +447,11 @@ regulator-always-on; }; - mmci@1c050000 { + mmci: mmci@1c050000 { compatible = "arm,pl180", "arm,primecell"; reg = <0x0 0x001c050000 0x0 0x1000>; interrupts = , ; - MMC_REMOVABLE; wp-gpios = <&sysreg 1 0>; bus-width = <4>; max-frequency = <25000000>; diff --git a/fdts/tc-fpga.dtsi b/fdts/tc-fpga.dtsi index f5bda29df..73f47431f 100644 --- a/fdts/tc-fpga.dtsi +++ b/fdts/tc-fpga.dtsi @@ -4,7 +4,6 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#define STDOUT_PATH "serial0:38400n8" #define GIC_CTRL_ADDR 30000000 #define GIC_GICR_OFFSET 0x1000000 #define UART_OFFSET 0x10000 @@ -20,5 +19,18 @@ vfront-porch = <3>; \ vback-porch = <217>; \ vsync-len = <10> -#define ETH_COMPATIBLE "smsc,lan9115" -#define MMC_REMOVABLE non-removable + +/ { + chosen { + stdout-path = "serial0:38400n8"; + }; + + ethernet: ethernet@18000000 { + compatible = "smsc,lan9115"; + phy-mode = "mii"; + }; + + mmci: mmci@1c050000 { + non-removable; + }; +}; diff --git a/fdts/tc-fvp.dtsi b/fdts/tc-fvp.dtsi index 22a4f5311..46b0e81ce 100644 --- a/fdts/tc-fvp.dtsi +++ b/fdts/tc-fvp.dtsi @@ -4,7 +4,6 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#define STDOUT_PATH "serial0:115200n8" #define GIC_CTRL_ADDR 2c010000 #define GIC_GICR_OFFSET 0x200000 #define UART_OFFSET 0x1000 @@ -19,10 +18,20 @@ vfront-porch = <10>; \ vback-porch = <33>; \ vsync-len = <2> -#define ETH_COMPATIBLE "smsc,lan91c111" -#define MMC_REMOVABLE cd-gpios = <&sysreg 0 0> / { + chosen { + stdout-path = "serial0:115200n8"; + }; + + ethernet: ethernet@18000000 { + compatible = "smsc,lan91c111"; + }; + + mmci: mmci@1c050000 { + cd-gpios = <&sysreg 0 0>; + }; + rtc@1c170000 { compatible = "arm,pl031", "arm,primecell"; reg = <0x0 0x1C170000 0x0 0x1000>; From 75400dd5dea935cb082ea948fc32d5a34af7547a Mon Sep 17 00:00:00 2001 From: Boyan Karatotev Date: Wed, 17 Apr 2024 17:12:18 +0100 Subject: [PATCH 09/11] refactor(tc): drop the 'mhu-protocol' property in DT binding As the 'mhu-protocol' property is not used in mhu node, drop it. Change-Id: I2f7320f668451ce44601dfa48bf47103334c39ed Signed-off-by: Boyan Karatotev Signed-off-by: Leo Yan --- fdts/tc-base.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/fdts/tc-base.dtsi b/fdts/tc-base.dtsi index 79f266677..e416bcaef 100644 --- a/fdts/tc-base.dtsi +++ b/fdts/tc-base.dtsi @@ -292,7 +292,6 @@ #mbox-cells = <2>; interrupts = ; interrupt-names = "mhu_rx"; - mhu-protocol = "doorbell"; arm,mhuv2-protocols = <0 1>; }; @@ -303,7 +302,6 @@ clock-names = "apb_pclk"; #mbox-cells = <2>; interrupt-names = "mhu_tx"; - mhu-protocol = "doorbell"; arm,mhuv2-protocols = <0 1>; }; From c33a39367591e596adc5fdb21fe858544693cd8b Mon Sep 17 00:00:00 2001 From: Boyan Karatotev Date: Fri, 19 Apr 2024 12:00:49 +0100 Subject: [PATCH 10/11] refactor(tc): move MHUv2 property to tc2.dts As only TC2 uses MHUv2, move the protocol property to tc2.dts. Change-Id: I39dd57311e1058a6aabd4cbd5028511f704dd234 Signed-off-by: Boyan Karatotev Signed-off-by: Leo Yan --- fdts/tc-base.dtsi | 2 -- fdts/tc2.dts | 8 ++++++++ 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/fdts/tc-base.dtsi b/fdts/tc-base.dtsi index e416bcaef..568d5fd2a 100644 --- a/fdts/tc-base.dtsi +++ b/fdts/tc-base.dtsi @@ -292,7 +292,6 @@ #mbox-cells = <2>; interrupts = ; interrupt-names = "mhu_rx"; - arm,mhuv2-protocols = <0 1>; }; mbox_db_tx: mhu@MHU_TX_ADDR { @@ -302,7 +301,6 @@ clock-names = "apb_pclk"; #mbox-cells = <2>; interrupt-names = "mhu_tx"; - arm,mhuv2-protocols = <0 1>; }; scmi { diff --git a/fdts/tc2.dts b/fdts/tc2.dts index d1343e581..288b40f02 100644 --- a/fdts/tc2.dts +++ b/fdts/tc2.dts @@ -203,6 +203,14 @@ interrupts = ; }; + mbox_db_rx: mhu@MHU_RX_ADDR { + arm,mhuv2-protocols = <0 1>; + }; + + mbox_db_tx: mhu@MHU_TX_ADDR { + arm,mhuv2-protocols = <0 1>; + }; + dp0: display@DPU_ADDR { #if TC_SCMI_PD_CTRL_EN power-domains = <&scmi_devpd (PLAT_MAX_CPUS_PER_CLUSTER + 2)>; From d42987c34a0cb6fcc8faefb2da91a8173bc9d46d Mon Sep 17 00:00:00 2001 From: Boyan Karatotev Date: Fri, 19 Apr 2024 13:59:11 +0100 Subject: [PATCH 11/11] refactor(tc): move SCMI nodes into the 'firmware' node As Linux 6.1 and later kernels require the SCMI nodes must be placed in a firmware node, this patch adds the 'firmware' node and puts SCMI nodes under it. Change-Id: I37855095b8b0e5051c5de6e8db30e43f6220f9de Signed-off-by: Boyan Karatotev Signed-off-by: Leo Yan --- fdts/tc-base.dtsi | 38 ++++++++++++++++++++------------------ 1 file changed, 20 insertions(+), 18 deletions(-) diff --git a/fdts/tc-base.dtsi b/fdts/tc-base.dtsi index 568d5fd2a..e32d21521 100644 --- a/fdts/tc-base.dtsi +++ b/fdts/tc-base.dtsi @@ -303,29 +303,31 @@ interrupt-names = "mhu_tx"; }; - scmi { - compatible = "arm,scmi"; - mbox-names = "tx", "rx"; - mboxes = <&mbox_db_tx 0 0 &mbox_db_rx 0 0 >; - shmem = <&cpu_scp_scmi_mem &cpu_scp_scmi_mem>; - #address-cells = <1>; - #size-cells = <0>; + firmware { + scmi { + compatible = "arm,scmi"; + mbox-names = "tx", "rx"; + mboxes = <&mbox_db_tx 0 0 &mbox_db_rx 0 0 >; + shmem = <&cpu_scp_scmi_mem &cpu_scp_scmi_mem>; + #address-cells = <1>; + #size-cells = <0>; #if TC_SCMI_PD_CTRL_EN - scmi_devpd: protocol@11 { - reg = <0x11>; - #power-domain-cells = <1>; - }; + scmi_devpd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; #endif /* TC_SCMI_PD_CTRL_EN */ - scmi_dvfs: protocol@13 { - reg = <0x13>; - #clock-cells = <1>; - }; + scmi_dvfs: protocol@13 { + reg = <0x13>; + #clock-cells = <1>; + }; - scmi_clk: protocol@14 { - reg = <0x14>; - #clock-cells = <1>; + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; }; };