diff --git a/fdts/tc.dts b/fdts/tc-base.dtsi similarity index 70% rename from fdts/tc.dts rename to fdts/tc-base.dtsi index 63f6c3dd7..e32d21521 100644 --- a/fdts/tc.dts +++ b/fdts/tc-base.dtsi @@ -4,15 +4,37 @@ * SPDX-License-Identifier: BSD-3-Clause */ -/dts-v1/; +/* If SCMI power domain control is enabled */ +#if TC_SCMI_PD_CTRL_EN +#define GPU_SCMI_PD_IDX (PLAT_MAX_CPUS_PER_CLUSTER + 1) +#define DPU_SCMI_PD_IDX (PLAT_MAX_CPUS_PER_CLUSTER + 2) +#endif /* TC_SCMI_PD_CTRL_EN */ -#include -#include -#include "platform_def.h" -#include "tc_vers.dtsi" -#if TARGET_FLAVOUR_FVP -#include "tc_fvp.dtsi" -#endif /* TARGET_FLAVOUR_FVP */ +/* Use SCMI controlled clocks */ +#if TC_DPU_USE_SCMI_CLK +#define DPU_CLK_ATTR1 \ + clocks = <&scmi_clk 0>; \ + clock-names = "aclk" + +#define DPU_CLK_ATTR2 \ + clocks = <&scmi_clk 1>; \ + clock-names = "pxclk" + +#define DPU_CLK_ATTR3 \ + clocks = <&scmi_clk 2>; \ + clock-names = "pxclk" \ +/* Use fixed clocks */ +#else /* !TC_DPU_USE_SCMI_CLK */ +#define DPU_CLK_ATTR1 \ + clocks = <&dpu_aclk>; \ + clock-names = "aclk" + +#define DPU_CLK_ATTR2 \ + clocks = <&dpu_pixel_clk>, <&dpu_aclk>; \ + clock-names = "pxclk", "aclk" + +#define DPU_CLK_ATTR3 DPU_CLK_ATTR2 +#endif /* !TC_DPU_USE_SCMI_CLK */ / { compatible = "arm,tc"; @@ -25,7 +47,6 @@ }; chosen { - stdout-path = STDOUT_PATH; /* * Add some dummy entropy for Linux so it * doesn't delay the boot waiting for it. @@ -70,26 +91,6 @@ core7 { cpu = <&CPU7>; }; -#if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 - core8 { - cpu = <&CPU8>; - }; - core9 { - cpu = <&CPU9>; - }; - core10 { - cpu = <&CPU10>; - }; - core11 { - cpu = <&CPU11>; - }; - core12 { - cpu = <&CPU12>; - }; - core13 { - cpu = <&CPU13>; - }; -#endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 */ }; }; @@ -170,13 +171,6 @@ reg = <0x200>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; -#if TARGET_PLATFORM <= 2 - clocks = <&scmi_dvfs 0>; - capacity-dmips-mhz = ; -#elif TARGET_PLATFORM == 3 - clocks = <&scmi_dvfs 1>; - capacity-dmips-mhz = ; -#endif /* TARGET_PLATFORM == 3 */ amu = <&amu>; supports-mpmm; }; @@ -187,13 +181,6 @@ reg = <0x300>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; -#if TARGET_PLATFORM <= 2 - clocks = <&scmi_dvfs 0>; - capacity-dmips-mhz = ; -#elif TARGET_PLATFORM == 3 - clocks = <&scmi_dvfs 1>; - capacity-dmips-mhz = ; -#endif /* TARGET_PLATFORM == 3 */ amu = <&amu>; supports-mpmm; }; @@ -228,13 +215,6 @@ reg = <0x600>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; -#if TARGET_PLATFORM <= 2 - clocks = <&scmi_dvfs 1>; - capacity-dmips-mhz = ; -#elif TARGET_PLATFORM == 3 - clocks = <&scmi_dvfs 2>; - capacity-dmips-mhz = ; -#endif /* TARGET_PLATFORM == 3 */ amu = <&amu>; supports-mpmm; }; @@ -245,84 +225,9 @@ reg = <0x700>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; -#if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 - clocks = <&scmi_dvfs 1>; - capacity-dmips-mhz = ; -#else - clocks = <&scmi_dvfs 2>; - capacity-dmips-mhz = ; -#endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 */ amu = <&amu>; supports-mpmm; }; - -#if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 - CPU8:cpu@800 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x800>; - enable-method = "psci"; - clocks = <&scmi_dvfs 1>; - capacity-dmips-mhz = ; - amu = <&amu>; - supports-mpmm; - }; - - CPU9:cpu@900 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x900>; - enable-method = "psci"; - clocks = <&scmi_dvfs 2>; - capacity-dmips-mhz = ; - amu = <&amu>; - supports-mpmm; - }; - - CPU10:cpu@A00 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0xA00>; - enable-method = "psci"; - clocks = <&scmi_dvfs 2>; - capacity-dmips-mhz = ; - amu = <&amu>; - supports-mpmm; - }; - - CPU11:cpu@B00 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0xB00>; - enable-method = "psci"; - clocks = <&scmi_dvfs 2>; - capacity-dmips-mhz = ; - amu = <&amu>; - supports-mpmm; - }; - - CPU12:cpu@C00 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0xC00>; - enable-method = "psci"; - clocks = <&scmi_dvfs 3>; - capacity-dmips-mhz = ; - amu = <&amu>; - supports-mpmm; - }; - - CPU13:cpu@D00 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0xD00>; - enable-method = "psci"; - clocks = <&scmi_dvfs 3>; - capacity-dmips-mhz = ; - amu = <&amu>; - supports-mpmm; - }; -#endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 */ }; reserved-memory { @@ -363,13 +268,6 @@ cpu-pmu { compatible = "arm,armv8-pmuv3"; interrupts = ; - interrupt-affinity = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>, - <&CPU4>, <&CPU5>, <&CPU6>, <&CPU7> -#if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 - ,<&CPU8>, <&CPU9>, <&CPU10>, <&CPU11>, - <&CPU12>, <&CPU13> -#endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 */ - ; }; sram: sram@6000000 { @@ -386,52 +284,50 @@ }; }; - mbox_db_rx: mhu@MHU_RX_ADDR() { + mbox_db_rx: mhu@MHU_RX_ADDR { compatible = "arm,mhuv2-rx","arm,primecell"; - reg = <0x0 MHU_RX_ADDR(0x) 0x0 0x1000>; + reg = <0x0 ADDRESSIFY(MHU_RX_ADDR) 0x0 0x1000>; clocks = <&soc_refclk>; clock-names = "apb_pclk"; #mbox-cells = <2>; interrupts = ; interrupt-names = "mhu_rx"; - mhu-protocol = "doorbell"; - arm,mhuv2-protocols = <0 1>; }; - mbox_db_tx: mhu@MHU_TX_ADDR() { + mbox_db_tx: mhu@MHU_TX_ADDR { compatible = "arm,mhuv2-tx","arm,primecell"; - reg = <0x0 MHU_TX_ADDR(0x) 0x0 0x1000>; + reg = <0x0 ADDRESSIFY(MHU_TX_ADDR) 0x0 0x1000>; clocks = <&soc_refclk>; clock-names = "apb_pclk"; #mbox-cells = <2>; interrupt-names = "mhu_tx"; - mhu-protocol = "doorbell"; - arm,mhuv2-protocols = <0 1>; }; - scmi { - compatible = "arm,scmi"; - mbox-names = "tx", "rx"; - mboxes = <&mbox_db_tx 0 0 &mbox_db_rx 0 0 >; - shmem = <&cpu_scp_scmi_mem &cpu_scp_scmi_mem>; - #address-cells = <1>; - #size-cells = <0>; + firmware { + scmi { + compatible = "arm,scmi"; + mbox-names = "tx", "rx"; + mboxes = <&mbox_db_tx 0 0 &mbox_db_rx 0 0 >; + shmem = <&cpu_scp_scmi_mem &cpu_scp_scmi_mem>; + #address-cells = <1>; + #size-cells = <0>; #if TC_SCMI_PD_CTRL_EN - scmi_devpd: protocol@11 { - reg = <0x11>; - #power-domain-cells = <1>; - }; + scmi_devpd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; #endif /* TC_SCMI_PD_CTRL_EN */ - scmi_dvfs: protocol@13 { - reg = <0x13>; - #clock-cells = <1>; - }; + scmi_dvfs: protocol@13 { + reg = <0x13>; + #clock-cells = <1>; + }; - scmi_clk: protocol@14 { - reg = <0x14>; - #clock-cells = <1>; + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; }; }; @@ -486,6 +382,22 @@ status = "okay"; }; +#if !TC_DPU_USE_SCMI_CLK + dpu_aclk: dpu_aclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = ; + clock-output-names = "fpga:dpu_aclk"; + }; + + dpu_pixel_clk: dpu-pixel-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = ; + clock-output-names = "pxclk"; + }; +#endif /* !TC_DPU_USE_SCMI_CLK */ + vencoder { compatible = "drm,virtual-encoder"; port { @@ -502,13 +414,10 @@ }; - ethernet@18000000 { - compatible = ETH_COMPATIBLE; + ethernet: ethernet@18000000 { reg = <0x0 0x18000000 0x0 0x10000>; interrupts = ; - /* FPGA only but will work on FVP. Keep for simplicity */ - phy-mode = "mii"; reg-io-width = <2>; smsc,irq-push-pull; }; @@ -536,12 +445,11 @@ regulator-always-on; }; - mmci@1c050000 { + mmci: mmci@1c050000 { compatible = "arm,pl180", "arm,primecell"; reg = <0x0 0x001c050000 0x0 0x1000>; interrupts = , ; - MMC_REMOVABLE; wp-gpios = <&sysreg 1 0>; bus-width = <4>; max-frequency = <25000000>; @@ -606,20 +514,17 @@ }; #endif /* TC_IOMMU_EN */ - dp0: display@DPU_ADDR() { + dp0: display@DPU_ADDR { #address-cells = <1>; #size-cells = <0>; compatible = "arm,mali-d71"; - reg = ; + reg = ; interrupts = ; interrupt-names = "DPU"; DPU_CLK_ATTR1; #if TC_IOMMU_EN iommus = <&smmu_700 0x100>; #endif /* TC_IOMMU_EN */ -#if TC_SCMI_PD_CTRL_EN && (TARGET_PLATFORM != 3) - power-domains = <&scmi_devpd DPU_SCMI_PD_IDX>; -#endif /* TC_SCMI_PD_CTRL_EN && (TARGET_PLATFORM != 3) */ pl0: pipeline@0 { reg = <0>; @@ -700,38 +605,6 @@ cpu = <&CPU7>; }; -#if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 - ete8 { - compatible = "arm,embedded-trace-extension"; - cpu = <&CPU8>; - }; - - ete9 { - compatible = "arm,embedded-trace-extension"; - cpu = <&CPU9>; - }; - - ete10 { - compatible = "arm,embedded-trace-extension"; - cpu = <&CPU10>; - }; - - ete11 { - compatible = "arm,embedded-trace-extension"; - cpu = <&CPU11>; - }; - - ete12 { - compatible = "arm,embedded-trace-extension"; - cpu = <&CPU12>; - }; - - ete13 { - compatible = "arm,embedded-trace-extension"; - cpu = <&CPU13>; - }; -#endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 */ - trbe { compatible = "arm,trace-buffer-extension"; interrupts = ; diff --git a/fdts/tc-common.dtsi b/fdts/tc-common.dtsi new file mode 100644 index 000000000..c3311930a --- /dev/null +++ b/fdts/tc-common.dtsi @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2023-2024, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#define PASTER(x, y) x ## y +#define EVALUATOR(x, y) PASTER(x, y) +#define ADDRESSIFY(addr) EVALUATOR(0x, addr) diff --git a/fdts/tc-fpga.dtsi b/fdts/tc-fpga.dtsi new file mode 100644 index 000000000..73f47431f --- /dev/null +++ b/fdts/tc-fpga.dtsi @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2023-2024, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#define GIC_CTRL_ADDR 30000000 +#define GIC_GICR_OFFSET 0x1000000 +#define UART_OFFSET 0x10000 +/* 1440x3200@120 framebuffer */ +#define VENCODER_TIMING_CLK 836000000 +#define VENCODER_TIMING \ + clock-frequency = ; \ + hactive = <1440>; \ + vactive = <3200>; \ + hfront-porch = <136>; \ + hback-porch = <296>; \ + hsync-len = <160>; \ + vfront-porch = <3>; \ + vback-porch = <217>; \ + vsync-len = <10> + +/ { + chosen { + stdout-path = "serial0:38400n8"; + }; + + ethernet: ethernet@18000000 { + compatible = "smsc,lan9115"; + phy-mode = "mii"; + }; + + mmci: mmci@1c050000 { + non-removable; + }; +}; diff --git a/fdts/tc_fvp.dtsi b/fdts/tc-fvp.dtsi similarity index 62% rename from fdts/tc_fvp.dtsi rename to fdts/tc-fvp.dtsi index 42f38180e..46b0e81ce 100644 --- a/fdts/tc_fvp.dtsi +++ b/fdts/tc-fvp.dtsi @@ -4,7 +4,34 @@ * SPDX-License-Identifier: BSD-3-Clause */ +#define GIC_CTRL_ADDR 2c010000 +#define GIC_GICR_OFFSET 0x200000 +#define UART_OFFSET 0x1000 +#define VENCODER_TIMING_CLK 25175000 +#define VENCODER_TIMING \ + clock-frequency = ; \ + hactive = <640>; \ + vactive = <480>; \ + hfront-porch = <16>; \ + hback-porch = <48>; \ + hsync-len = <96>; \ + vfront-porch = <10>; \ + vback-porch = <33>; \ + vsync-len = <2> + / { + chosen { + stdout-path = "serial0:115200n8"; + }; + + ethernet: ethernet@18000000 { + compatible = "smsc,lan91c111"; + }; + + mmci: mmci@1c050000 { + cd-gpios = <&sysreg 0 0>; + }; + rtc@1c170000 { compatible = "arm,pl031", "arm,primecell"; reg = <0x0 0x1C170000 0x0 0x1000>; diff --git a/fdts/tc2.dts b/fdts/tc2.dts new file mode 100644 index 000000000..288b40f02 --- /dev/null +++ b/fdts/tc2.dts @@ -0,0 +1,219 @@ +/* + * Copyright (c) 2020-2024, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +/dts-v1/; + +#include +#include +#include + +#if TARGET_FLAVOUR_FVP +#define LIT_CAPACITY 406 +#define MID_CAPACITY 912 +#else /* TARGET_FLAVOUR_FPGA */ +#define LIT_CAPACITY 280 +#define MID_CAPACITY 775 +/* this is an area optimized configuration of the big core */ +#define BIG2_CAPACITY 930 +#endif /* TARGET_FLAVOUR_FPGA */ +#define BIG_CAPACITY 1024 + +#define INT_MBOX_RX 317 +#define MHU_TX_ADDR 45000000 /* hex */ +#define MHU_RX_ADDR 45010000 /* hex */ +#define MPAM_ADDR 0x1 0x00010000 /* 0x1_0001_0000 */ +#define UARTCLK_FREQ 5000000 + +#define DPU_ADDR 2cc00000 +#define DPU_IRQ 69 + +#include "tc-common.dtsi" +#if TARGET_FLAVOUR_FVP +#include "tc-fvp.dtsi" +#else +#include "tc-fpga.dtsi" +#endif /* TARGET_FLAVOUR_FVP */ +#include "tc-base.dtsi" + +/ { + cpus { +#if TARGET_FLAVOUR_FPGA + cpu-map { + cluster0 { + core8 { + cpu = <&CPU8>; + }; + core9 { + cpu = <&CPU9>; + }; + core10 { + cpu = <&CPU10>; + }; + core11 { + cpu = <&CPU11>; + }; + core12 { + cpu = <&CPU12>; + }; + core13 { + cpu = <&CPU13>; + }; + }; + }; +#endif + + CPU2:cpu@200 { + clocks = <&scmi_dvfs 0>; + capacity-dmips-mhz = ; + }; + + CPU3:cpu@300 { + clocks = <&scmi_dvfs 0>; + capacity-dmips-mhz = ; + }; + + CPU6:cpu@600 { + clocks = <&scmi_dvfs 1>; + capacity-dmips-mhz = ; + }; + + CPU7:cpu@700 { + clocks = <&scmi_dvfs 1>; + capacity-dmips-mhz = ; + }; + +#if TARGET_FLAVOUR_FPGA + CPU8:cpu@800 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x800>; + enable-method = "psci"; + clocks = <&scmi_dvfs 1>; + capacity-dmips-mhz = ; + amu = <&amu>; + supports-mpmm; + }; + + CPU9:cpu@900 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x900>; + enable-method = "psci"; + clocks = <&scmi_dvfs 2>; + capacity-dmips-mhz = ; + amu = <&amu>; + supports-mpmm; + }; + + CPU10:cpu@A00 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0xA00>; + enable-method = "psci"; + clocks = <&scmi_dvfs 2>; + capacity-dmips-mhz = ; + amu = <&amu>; + supports-mpmm; + }; + + CPU11:cpu@B00 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0xB00>; + enable-method = "psci"; + clocks = <&scmi_dvfs 2>; + capacity-dmips-mhz = ; + amu = <&amu>; + supports-mpmm; + }; + + CPU12:cpu@C00 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0xC00>; + enable-method = "psci"; + clocks = <&scmi_dvfs 3>; + capacity-dmips-mhz = ; + amu = <&amu>; + supports-mpmm; + }; + + CPU13:cpu@D00 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0xD00>; + enable-method = "psci"; + clocks = <&scmi_dvfs 3>; + capacity-dmips-mhz = ; + amu = <&amu>; + supports-mpmm; + }; +#endif + }; + +#if TARGET_FLAVOUR_FPGA + ete8 { + compatible = "arm,embedded-trace-extension"; + cpu = <&CPU8>; + }; + + ete9 { + compatible = "arm,embedded-trace-extension"; + cpu = <&CPU9>; + }; + + ete10 { + compatible = "arm,embedded-trace-extension"; + cpu = <&CPU10>; + }; + + ete11 { + compatible = "arm,embedded-trace-extension"; + cpu = <&CPU11>; + }; + + ete12 { + compatible = "arm,embedded-trace-extension"; + cpu = <&CPU12>; + }; + + ete13 { + compatible = "arm,embedded-trace-extension"; + cpu = <&CPU13>; + }; +#endif /* TARGET_FLAVOUR_FPGA */ + + cpu-pmu { +#if TARGET_FLAVOUR_FPGA + interrupt-affinity = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>, + <&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>, + <&CPU8>, <&CPU9>, <&CPU10>, <&CPU11>, + <&CPU12>, <&CPU13>; +#else + interrupt-affinity = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>, + <&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>; +#endif + }; + + cmn-pmu { + compatible = "arm,ci-700"; + reg = <0x0 0x50000000 0x0 0x10000000>; + interrupts = ; + }; + + mbox_db_rx: mhu@MHU_RX_ADDR { + arm,mhuv2-protocols = <0 1>; + }; + + mbox_db_tx: mhu@MHU_TX_ADDR { + arm,mhuv2-protocols = <0 1>; + }; + + dp0: display@DPU_ADDR { +#if TC_SCMI_PD_CTRL_EN + power-domains = <&scmi_devpd (PLAT_MAX_CPUS_PER_CLUSTER + 2)>; +#endif + }; +}; diff --git a/fdts/tc3.dts b/fdts/tc3.dts new file mode 100644 index 000000000..52b0856f6 --- /dev/null +++ b/fdts/tc3.dts @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2020-2024, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/dts-v1/; + +#include +#include +#include + +#define LIT_CAPACITY 239 +#define MID_CAPACITY 686 +#define BIG_CAPACITY 1024 + +#define INT_MBOX_RX 300 +#define MHU_TX_ADDR 46040000 /* hex */ +#define MHU_RX_ADDR 46140000 /* hex */ +#define MPAM_ADDR 0x0 0x5f010000 /* 0x5f01_0000 */ +#define UARTCLK_FREQ 3750000 + +#if TARGET_FLAVOUR_FVP +#define DPU_ADDR 4000000000 +#define DPU_IRQ 579 +#elif TARGET_FLAVOUR_FPGA +#define DPU_ADDR 2cc00000 +#define DPU_IRQ 69 +#endif + +#include "tc-common.dtsi" +#if TARGET_FLAVOUR_FVP +#include "tc-fvp.dtsi" +#else +#include "tc-fpga.dtsi" +#endif /* TARGET_FLAVOUR_FVP */ +#include "tc-base.dtsi" + +/ { + cpus { + CPU2:cpu@200 { + clocks = <&scmi_dvfs 1>; + capacity-dmips-mhz = ; + }; + + CPU3:cpu@300 { + clocks = <&scmi_dvfs 1>; + capacity-dmips-mhz = ; + }; + + CPU6:cpu@600 { + clocks = <&scmi_dvfs 2>; + capacity-dmips-mhz = ; + }; + + CPU7:cpu@700 { + clocks = <&scmi_dvfs 2>; + capacity-dmips-mhz = ; + }; + }; + + cpu-pmu { + interrupt-affinity = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>, + <&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>; + }; +}; diff --git a/fdts/tc_vers.dtsi b/fdts/tc_vers.dtsi deleted file mode 100644 index 43fafd536..000000000 --- a/fdts/tc_vers.dtsi +++ /dev/null @@ -1,147 +0,0 @@ -/* - * Copyright (c) 2023-2024, Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include - -/* If SCMI power domain control is enabled */ -#if TC_SCMI_PD_CTRL_EN -#define GPU_SCMI_PD_IDX (PLAT_MAX_CPUS_PER_CLUSTER + 1) -#define DPU_SCMI_PD_IDX (PLAT_MAX_CPUS_PER_CLUSTER + 2) -#endif /* TC_SCMI_PD_CTRL_EN */ - -/* All perf is normalized against the big core */ -#define BIG_CAPACITY 1024 - -#if TARGET_PLATFORM <= 2 -#if TARGET_FLAVOUR_FVP -#define LIT_CAPACITY 406 -#define MID_CAPACITY 912 -#else /* TARGET_FLAVOUR_FPGA */ -#define LIT_CAPACITY 280 -#define MID_CAPACITY 775 -/* this is an area optimized configuration of the big core */ -#define BIG2_CAPACITY 930 -#endif /* TARGET_FLAVOUR_FPGA */ - -#define INT_MBOX_RX 317 -#define MHU_TX_ADDR(pref) pref##45000000 /* hex */ -#define MHU_RX_ADDR(pref) pref##45010000 /* hex */ -#define MPAM_ADDR 0x1 0x00010000 /* 0x1_0001_0000 */ -#define UARTCLK_FREQ 5000000 -#elif TARGET_PLATFORM == 3 - -#define LIT_CAPACITY 239 -#define MID_CAPACITY 686 - -#define INT_MBOX_RX 300 -#define MHU_TX_ADDR(pref) pref##46040000 /* hex */ -#define MHU_RX_ADDR(pref) pref##46140000 /* hex */ -#define MPAM_ADDR 0x0 0x5f010000 /* 0x5f01_0000 */ -#define UARTCLK_FREQ 3750000 -#endif /* TARGET_PLATFORM == 3 */ - -#if TARGET_FLAVOUR_FVP -#define STDOUT_PATH "serial0:115200n8" -#define GIC_CTRL_ADDR 2c010000 -#define GIC_GICR_OFFSET 0x200000 -#define UART_OFFSET 0x1000 -#define VENCODER_TIMING_CLK 25175000 -#define VENCODER_TIMING \ - clock-frequency = ; \ - hactive = <640>; \ - vactive = <480>; \ - hfront-porch = <16>; \ - hback-porch = <48>; \ - hsync-len = <96>; \ - vfront-porch = <10>; \ - vback-porch = <33>; \ - vsync-len = <2> -#define ETH_COMPATIBLE "smsc,lan91c111" -#define MMC_REMOVABLE cd-gpios = <&sysreg 0 0> -#if TARGET_PLATFORM <= 2 -#define DPU_ADDR(pref) pref##2cc00000 -#define DPU_IRQ 69 -#else /* TARGET_PLATFORM >= 3 */ -#define DPU_ADDR(pref) pref##4000000000 -#define DPU_IRQ 579 -#endif /* TARGET_PLATFORM >= 3 */ - -#else /* TARGET_FLAVOUR_FPGA */ - -#define STDOUT_PATH "serial0:38400n8" -#define GIC_CTRL_ADDR 30000000 -#define GIC_GICR_OFFSET 0x1000000 -#define UART_OFFSET 0x10000 -/* 1440x3200@120 framebuffer */ -#define VENCODER_TIMING_CLK 836000000 -#define VENCODER_TIMING \ - clock-frequency = ; \ - hactive = <1440>; \ - vactive = <3200>; \ - hfront-porch = <136>; \ - hback-porch = <296>; \ - hsync-len = <160>; \ - vfront-porch = <3>; \ - vback-porch = <217>; \ - vsync-len = <10> -#define ETH_COMPATIBLE "smsc,lan9115" -#define MMC_REMOVABLE non-removable -#define DPU_ADDR(pref) pref##2cc00000 -#define DPU_IRQ 69 -#endif /* TARGET_FLAVOUR_FPGA */ - -/* Use SCMI controlled clocks */ -#if TC_DPU_USE_SCMI_CLK -#define DPU_CLK_ATTR1 \ - clocks = <&scmi_clk 0>; \ - clock-names = "aclk" - -#define DPU_CLK_ATTR2 \ - clocks = <&scmi_clk 1>; \ - clock-names = "pxclk" - -#define DPU_CLK_ATTR3 \ - clocks = <&scmi_clk 2>; \ - clock-names = "pxclk" \ -/* Use fixed clocks */ -#else /* !TC_DPU_USE_SCMI_CLK */ -#define DPU_CLK_ATTR1 \ - clocks = <&dpu_aclk>; \ - clock-names = "aclk" - -#define DPU_CLK_ATTR2 \ - clocks = <&dpu_pixel_clk>, <&dpu_aclk>; \ - clock-names = "pxclk", "aclk" - -#define DPU_CLK_ATTR3 DPU_CLK_ATTR2 -#endif /* !TC_DPU_USE_SCMI_CLK */ - -/ { -#if TARGET_PLATFORM <= 2 - cmn-pmu { - compatible = "arm,ci-700"; - reg = <0x0 0x50000000 0x0 0x10000000>; - interrupts = ; - }; -#endif /* TARGET_PLATFORM <= 2 */ - -#if !TC_DPU_USE_SCMI_CLK - dpu_aclk: dpu_aclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = ; - clock-output-names = "fpga:dpu_aclk"; - }; - - dpu_pixel_clk: dpu-pixel-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = ; - clock-output-names = "pxclk"; - }; -#endif /* !TC_DPU_USE_SCMI_CLK */ -}; diff --git a/plat/arm/board/tc/platform.mk b/plat/arm/board/tc/platform.mk index a2bc9c228..93e26d1d7 100644 --- a/plat/arm/board/tc/platform.mk +++ b/plat/arm/board/tc/platform.mk @@ -163,7 +163,7 @@ $(eval $(call TOOL_ADD_PAYLOAD,${TC_TOS_FW_CONFIG},--tos-fw-config,${TC_TOS_FW_C endif #Device tree -TC_HW_CONFIG_DTS := fdts/tc.dts +TC_HW_CONFIG_DTS := fdts/${PLAT}${TARGET_PLATFORM}.dts TC_HW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}.dtb FDT_SOURCES += ${TC_HW_CONFIG_DTS} $(eval TC_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(TC_HW_CONFIG_DTS)))