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fix(imx8ulp): fix suspend/resume issue when DBD owner is s400 only
After resume from APD power down, XRDC is initialized by S400 but the PAC2 and MSC0-2 are not configured, so only DBD owner can access the resources. We have to move GPIO restore after TFA XRDC reinit and configure PDAC for PCC5 before enabling eDMA2 MP clock Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: I82748de080151b0bdf1cace092b7892a1e402a27
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d159c00532
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2 changed files with 6 additions and 2 deletions
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@ -558,12 +558,13 @@ void imx_apd_ctx_restore(unsigned int proc_num)
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iomuxc_restore();
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iomuxc_restore();
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gpio_restore(apd_gpio_ctx, APD_GPIO_CTRL_NUM);
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tpm5_restore();
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tpm5_restore();
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xrdc_reinit();
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xrdc_reinit();
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/* Restore GPIO after xrdc_reinit, otherwise MSCs are invalid */
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gpio_restore(apd_gpio_ctx, APD_GPIO_CTRL_NUM);
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/* restore the gic config */
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/* restore the gic config */
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plat_gic_restore(proc_num, &imx_gicv3_ctx);
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plat_gic_restore(proc_num, &imx_gicv3_ctx);
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@ -303,6 +303,9 @@ static int xrdc_apply_config(xrdc_check_func check_func)
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int xrdc_apply_lpav_config(void)
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int xrdc_apply_lpav_config(void)
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{
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{
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/* Configure PAC2 to allow to access PCC5 */
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xrdc_config_pac(2, 39, 0xe00000);
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/* Enable the eDMA2 MP clock for MDA16 access */
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/* Enable the eDMA2 MP clock for MDA16 access */
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mmio_write_32(IMX_PCC5_BASE + 0x0, 0xc0000000);
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mmio_write_32(IMX_PCC5_BASE + 0x0, 0xc0000000);
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return xrdc_apply_config(xrdc_check_lpav);
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return xrdc_apply_config(xrdc_check_lpav);
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