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feat(intel): update hand-off data to include agilex5 params

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Update hand-off data structure to include agilex5
platform specific parameters.

Change-Id: Ic610e2d8da7488e49462293d13293e26520579e2
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
This commit is contained in:
Girisha Dengi 2024-04-04 15:52:37 +08:00 • committed by Tang Sieu Mun
parent 3eab6c920c
commit 6875d823ed
2 changed files with 18 additions and 17 deletions
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1
plat/intel/soc/agilex5/include/socfpga_plat_def.h
View file

@ -11,6 +11,7 @@
#include "agilex5_memory_controller.h" #include "agilex5_memory_controller.h"
#include "agilex5_system_manager.h" #include "agilex5_system_manager.h"
#include <platform_def.h> #include <platform_def.h>
/* Platform Setting */ /* Platform Setting */

26
plat/intel/soc/common/include/socfpga_handoff.h
View file

@ -127,6 +127,8 @@ typedef struct handoff_t {
uint32_t clock_magic; uint32_t clock_magic;
uint32_t clock_length; uint32_t clock_length;
uint32_t _pad_0x588_0x590[2]; uint32_t _pad_0x588_0x590[2];
/* main group PLL */
uint32_t main_pll_nocclk; uint32_t main_pll_nocclk;
uint32_t main_pll_nocdiv; uint32_t main_pll_nocdiv;
uint32_t main_pll_pllglob; uint32_t main_pll_pllglob;
@ -136,6 +138,8 @@ typedef struct handoff_t {
uint32_t main_pll_pllc2; uint32_t main_pll_pllc2;
uint32_t main_pll_pllc3; uint32_t main_pll_pllc3;
uint32_t main_pll_pllm; uint32_t main_pll_pllm;
/* peripheral group PLL */
uint32_t per_pll_emacctl; uint32_t per_pll_emacctl;
uint32_t per_pll_gpiodiv; uint32_t per_pll_gpiodiv;
uint32_t per_pll_pllglob; uint32_t per_pll_pllglob;
@ -145,29 +149,25 @@ typedef struct handoff_t {
uint32_t per_pll_pllc2; uint32_t per_pll_pllc2;
uint32_t per_pll_pllc3; uint32_t per_pll_pllc3;
uint32_t per_pll_pllm; uint32_t per_pll_pllm;
/* control group */
uint32_t alt_emacactr; uint32_t alt_emacactr;
uint32_t alt_emacbctr; uint32_t alt_emacbctr;
uint32_t alt_emacptpctr; uint32_t alt_emacptpctr;
uint32_t alt_gpiodbctr; uint32_t alt_gpiodbctr;
uint32_t alt_sdmmcctr;
uint32_t alt_s2fuser0ctr; uint32_t alt_s2fuser0ctr;
uint32_t alt_s2fuser1ctr; uint32_t alt_s2fuser1ctr;
uint32_t alt_psirefctr; uint32_t alt_psirefctr;
/* TODO: Temp added for clk manager. */ uint32_t alt_usb31ctr;
uint32_t qspi_clk_khz; uint32_t alt_dsuctr;
uint32_t alt_core01ctr;
uint32_t alt_core23ctr;
uint32_t alt_core2ctr;
uint32_t alt_core3ctr;
uint32_t hps_osc_clk_hz; uint32_t hps_osc_clk_hz;
uint32_t fpga_clk_hz; uint32_t fpga_clk_hz;
/* TODO: Temp added for clk manager. */ uint32_t _pad_0x604_0x610[3];
uint32_t ddr_reset_type;
/* TODO: Temp added for clk manager. */
uint32_t hps_status_coldreset;
/* TODO: Temp remove due to add in extra handoff data */
//uint32_t _pad_0x604_0x610[3];
#endif #endif
/* misc configuration */
uint32_t misc_magic;
uint32_t misc_length;
uint32_t _pad_0x618_0x620[2];
#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
/* peripheral configuration - select */ /* peripheral configuration - select */