From 672eb21e26a41657b8146372d4283e794b430c5f Mon Sep 17 00:00:00 2001 From: Bipin Ravi Date: Tue, 14 Mar 2023 10:04:23 -0500 Subject: [PATCH] fix(cpus): workaround for Cortex-A78C erratum 1827430 Cortex-A78C erratum 1827430 is a Cat B erratum that applies to revision r0p0 and is fixed in r0p1. The workaround is to set the CPUECTLR_EL1[53] to 1, which disables allocation of splintered pages in the L2 TLB. SDEN documentation: https://developer.arm.com/documentation/SDEN1707916/latest Signed-off-by: Bipin Ravi Change-Id: Ie68771bdd3bddeff54d06b6a456dad4a7fc27426 --- docs/design/cpu-specific-build-macros.rst | 4 +++ include/lib/cpus/aarch64/cortex_a78c.h | 1 + lib/cpus/aarch64/cortex_a78c.S | 33 +++++++++++++++++++++++ lib/cpus/cpu-ops.mk | 4 +++ 4 files changed, 42 insertions(+) diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index 8a201862c..73c7ac552 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -349,6 +349,10 @@ For Cortex-A78 AE, the following errata build flags are defined : For Cortex-A78C, the following errata build flags are defined : +- ``ERRATA_A78C_1827430`` : This applies errata 1827430 workaround to + Cortex-A78C CPU. This needs to be enabled for revision r0p0. The erratum is + fixed in r0p1. + - ``ERRATA_A78C_2132064`` : This applies errata 2132064 workaround to Cortex-A78C CPU. This needs to be enabled for revisions r0p1, r0p2 and it is still open. diff --git a/include/lib/cpus/aarch64/cortex_a78c.h b/include/lib/cpus/aarch64/cortex_a78c.h index 18cba2c0b..301be69a4 100644 --- a/include/lib/cpus/aarch64/cortex_a78c.h +++ b/include/lib/cpus/aarch64/cortex_a78c.h @@ -26,6 +26,7 @@ #define CORTEX_A78C_CPUECTLR_EL1 S3_0_C15_C1_4 #define CORTEX_A78C_CPUECTLR_EL1_BIT_6 (ULL(1) << 6) #define CORTEX_A78C_CPUECTLR_EL1_BIT_7 (ULL(1) << 7) +#define CORTEX_A78C_CPUECTLR_EL1_MM_ASP_EN (ULL(1) << 53) /******************************************************************************* * CPU Power Control register specific definitions diff --git a/lib/cpus/aarch64/cortex_a78c.S b/lib/cpus/aarch64/cortex_a78c.S index 71f07258b..88bd29184 100644 --- a/lib/cpus/aarch64/cortex_a78c.S +++ b/lib/cpus/aarch64/cortex_a78c.S @@ -17,6 +17,33 @@ #error "cortex_a78c must be compiled with HW_ASSISTED_COHERENCY enabled" #endif +/* -------------------------------------------------- + * Errata Workaround for A78C Erratum 1827430. + * This applies to revision r0p0 of the Cortex A78C + * processor and is fixed in r0p1. + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * -------------------------------------------------- + */ +func errata_a78c_1827430_wa + mov x17, x30 + bl check_errata_1827430 + cbz x0, 1f + + /* Disable allocation of splintered pages in the L2 TLB */ + mrs x1, CORTEX_A78C_CPUECTLR_EL1 + orr x1, x1, CORTEX_A78C_CPUECTLR_EL1_MM_ASP_EN + msr CORTEX_A78C_CPUECTLR_EL1, x1 +1: + ret x17 +endfunc errata_a78c_1827430_wa + +func check_errata_1827430 + /* Applies to revision r0p0 only */ + mov x1, #0x00 + b cpu_rev_var_ls +endfunc check_errata_1827430 + /* -------------------------------------------------- * Errata Workaround for Cortex A78C Erratum 2376749. * This applies to revision r0p1 and r0p2 of the A78C @@ -225,6 +252,11 @@ func cortex_a78c_reset_func bl cpu_get_rev_var mov x18, x0 +#if ERRATA_A78C_1827430 + mov x0, x18 + bl errata_a78c_1827430_wa +#endif + #if ERRATA_A78C_2132064 mov x0, x18 bl errata_a78c_2132064_wa @@ -299,6 +331,7 @@ func cortex_a78c_errata_report * Report all errata. The revision-variant information is passed to * checking functions of each errata. */ + report_errata ERRATA_A78C_1827430, cortex_a78c, 1827430 report_errata ERRATA_A78C_2132064, cortex_a78c, 2132064 report_errata ERRATA_A78C_2242638, cortex_a78c, 2242638 report_errata ERRATA_A78C_2376749, cortex_a78c, 2376749 diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index e26548fdd..13cf50864 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -354,6 +354,10 @@ CPU_FLAG_LIST += ERRATA_A78_AE_2376748 # to revisions r0p0 and r0p1 of the A78 AE cpu. It is still open. CPU_FLAG_LIST += ERRATA_A78_AE_2395408 +# Flag to apply erratum 1827430 workaround during reset. This erratum applies +# to revision r0p0 of the A78C cpu. It is fixed in r0p1. +CPU_FLAG_LIST += ERRATA_A78C_1827430 + # Flag to apply erratum 2132064 workaround during reset. This erratum applies # to revisions r0p1 and r0p2 of the A78C cpu. It is still open. CPU_FLAG_LIST += ERRATA_A78C_2132064