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drivers: marvell: misc-dfx: extend dfx whitelist

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Linux cpu clk driver requires access to some dfx registers. By adding
these registers to the white list, we enable access to them from
non-secure world.

Change-Id: Ic05c96b375121c025bfb41c2ac9474a530720155
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-on: https://sj1git1.cavium.com/25187
Tested-by: Kostya Porotchkin <kostap@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
This commit is contained in:
Grzegorz Jaszczyk 2020-03-18 18:07:37 +01:00 • committed by Manish Pandey
parent 81c2a044e2
commit 667893adb6
1 changed files with 36 additions and 0 deletions
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36
drivers/marvell/secure_dfx_access/misc_dfx.c
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@ -29,6 +29,31 @@
#define EFUSE_HD_BASE (MVEBU_REGS_BASE + 0x6F9000)
#define EFUSE_HD_SIZE 0x3F8
/* AP806 CPU DFS register mapping*/
#define AP806_CA72MP2_0_PLL_CR_0_BASE (MVEBU_REGS_BASE + 0x6F8278)
#define AP806_CA72MP2_0_PLL_CR_1_BASE (MVEBU_REGS_BASE + 0x6F8280)
#define AP806_CA72MP2_0_PLL_CR_2_BASE (MVEBU_REGS_BASE + 0x6F8284)
#define AP806_CA72MP2_0_PLL_SR_BASE (MVEBU_REGS_BASE + 0x6F8C94)
/* AP807 CPU DFS register mapping */
#define AP807_DEVICE_GENERAL_CR_10_BASE (MVEBU_REGS_BASE + 0x6F8278)
#define AP807_DEVICE_GENERAL_CR_11_BASE (MVEBU_REGS_BASE + 0x6F827C)
#define AP807_DEVICE_GENERAL_STATUS_6_BASE (MVEBU_REGS_BASE + 0x6F8C98)
#ifdef MVEBU_SOC_AP807
#define CLUSTER_OFFSET 0x8
#define CLK_DIVIDER_REG AP807_DEVICE_GENERAL_CR_10_BASE
#define CLK_FORCE_REG AP807_DEVICE_GENERAL_CR_11_BASE
#define CLK_RATIO_REG AP807_DEVICE_GENERAL_CR_11_BASE
#define CLK_RATIO_STATE_REG AP807_DEVICE_GENERAL_STATUS_6_BASE
#else
#define CLUSTER_OFFSET 0x14
#define CLK_DIVIDER_REG AP806_CA72MP2_0_PLL_CR_0_BASE
#define CLK_FORCE_REG AP806_CA72MP2_0_PLL_CR_1_BASE
#define CLK_RATIO_REG AP806_CA72MP2_0_PLL_CR_2_BASE
#define CLK_RATIO_STATE_REG AP806_CA72MP2_0_PLL_SR_BASE
#endif /* MVEBU_SOC_AP807 */
static _Bool is_valid(u_register_t addr)
{
switch (addr) {
@ -38,6 +63,17 @@ static _Bool is_valid(u_register_t addr)
case EFUSE_LD_BASE ... (EFUSE_LD_BASE + EFUSE_LD_SIZE):
case EFUSE_HD_BASE ... (EFUSE_HD_BASE + EFUSE_HD_SIZE):
case EFUSE_CTRL:
/* cpu-clk related registers */
case CLK_DIVIDER_REG:
case CLK_DIVIDER_REG + CLUSTER_OFFSET:
case CLK_FORCE_REG:
case CLK_FORCE_REG + CLUSTER_OFFSET:
#ifndef MVEBU_SOC_AP807
case CLK_RATIO_REG:
case CLK_RATIO_REG + CLUSTER_OFFSET:
#endif
case CLK_RATIO_STATE_REG:
case CLK_RATIO_STATE_REG + CLUSTER_OFFSET:
return true;
default:
return false;