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fix(gicv3): wait rwp when gicr_ctrl.enablelpis from 1 to 0

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Per GIC architecture version 3 and version 4, Where the GICR_CTRL.EnableLPIs
remains programmable:
- Software must observe GICR_CTLR.RWP==0 after clearing GICR_CTLR.EnableLPIs
  from 1 to 0 before writing GICR_PENDBASER or GICR_PROPBASER, otherwise
  behavior is UNPREDICTABLE.
- Software must observe GICR_CTLR.RWP==0 after clearing GICR_CTLR.EnableLPIs
  from 1 to 0 before setting GICR_CTLR.EnableLPIs to 1, otherwise behavior is
  UNPREDICTABLE.

After changing EnableLPIs from 1 to 0, wait RWP got cleared, otherwise
setting EnableLPIs from 0 to 1 may fail.

Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Tested-by: Clark Wang <xiaoning.wang@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Change-Id: I6aaf96dc9984376de9399d0dac8a8504ba095149
This commit is contained in:
Peng Fan 2024-05-28 14:27:54 +08:00
parent d2d1da5fdf
commit 66668c77cb
1 changed files with 2 additions and 0 deletions
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2
drivers/arm/gic/v3/gicv3_main.c
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@ -686,6 +686,8 @@ void gicv3_rdistif_init_restore(unsigned int proc_num,
gicr_write_ctlr(gicr_base,
rdist_ctx->gicr_ctlr & ~(GICR_CTLR_EN_LPIS_BIT));
gicr_wait_for_pending_write(gicr_base);
/* Restore registers' content */
gicr_write_propbaser(gicr_base, rdist_ctx->gicr_propbaser);
gicr_write_pendbaser(gicr_base, rdist_ctx->gicr_pendbaser);