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ti: k3: common: Use coherent memory for shared data

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HW_ASSISTED_COHERENCY implies something stronger than just hardware
coherent interconnect, specifically a DynamIQ capable ARM core.

For K3, lets use WARMBOOT_ENABLE_DCACHE_EARLY to enable caches early
and then let the caches get shut off on powerdown, to prevent data
corruption we also need to USE_COHERENT_MEM so that any accesses to
shared memory after this point is only to memory that is set as
non-cached for all cores.

Change-Id: Ib9337f012df0e0388237942607c501b6f3e2a949
Signed-off-by: Andrew F. Davis <afd@ti.com>
This commit is contained in:
Andrew F. Davis 2019-04-25 14:02:33 -04:00 • committed by John Tsichritzis
parent 49d969bbb3
commit 65f7b81728
1 changed files with 2 additions and 2 deletions
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4
plat/ti/k3/common/plat_common.mk
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@ -12,8 +12,8 @@ COLD_BOOT_SINGLE_CPU := 1
PROGRAMMABLE_RESET_ADDRESS:= 1 PROGRAMMABLE_RESET_ADDRESS:= 1
# System coherency is managed in hardware # System coherency is managed in hardware
HW_ASSISTED_COHERENCY := 1 WARMBOOT_ENABLE_DCACHE_EARLY := 1
USE_COHERENT_MEM := 0 USE_COHERENT_MEM := 1
# A53 erratum for SoC. (enable them all) # A53 erratum for SoC. (enable them all)
ERRATA_A53_826319 := 1 ERRATA_A53_826319 := 1