Djam/arm-trusted-firmware
1
0
Fork 0
mirror of https://github.com/ARM-software/arm-trusted-firmware.git synced 2025-04-16 09:34:18 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

ARMv7: GICv2 driver can manage GICv1 with security extension

Browse source 
Some SoCs integrate a GIC in version 1 that is currently not supported
by the trusted firmware. This change hijacks GICv2 driver to handle the
GICv1 as GICv1 is compatible enough with GICv2 as far as the platform
does not attempt to play with virtualization support or some GICv2
specific power features.

Note that current trusted firmware does not use these GICv2 features
that are not available in GICv1 Security Extension.

Change-Id: Ic2cb3055f1319a83455571d6d918661da583f179
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
This commit is contained in:
Etienne Carriere 2017-11-05 22:57:38 +01:00
parent 634e4d2be6
commit 64deed19e4
2 changed files with 15 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

14
drivers/arm/gic/v2/gicv2_main.c
View file

@ -167,7 +167,19 @@ void gicv2_driver_init(const gicv2_driver_data_t *plat_driver_data)
gic_version = gicd_read_pidr2(plat_driver_data->gicd_base);
gic_version = (gic_version >> PIDR2_ARCH_REV_SHIFT)
& PIDR2_ARCH_REV_MASK;
assert(gic_version == ARCH_REV_GICV2);
/*
* GICv1 with security extension complies with trusted firmware
* GICv2 driver as far as virtualization and few tricky power
* features are not used. GICv2 features that are not supported
* by GICv1 with Security Extensions are:
* - virtual interrupt support.
* - wake up events.
* - writeable GIC state register (for power sequences)
* - interrupt priority drop.
* - interrupt signal bypass.
*/
assert(gic_version == ARCH_REV_GICV2 || gic_version == ARCH_REV_GICV1);
driver_data = plat_driver_data;

2
include/drivers/arm/gic_common.h
View file

@ -72,6 +72,8 @@
#define ARCH_REV_GICV3 0x3
/* GICv2 revision as reported by the PIDR2 register */
#define ARCH_REV_GICV2 0x2
/* GICv1 revision as reported by the PIDR2 register */
#define ARCH_REV_GICV1 0x1
#define IGROUPR_SHIFT 5
#define ISENABLER_SHIFT 5