From 23647bd52c805594050c5cd0e387389760778492 Mon Sep 17 00:00:00 2001 From: Boerge Struempfel Date: Mon, 27 Jan 2025 20:31:37 +0100 Subject: [PATCH] fix(stm32mp2): correct early/crash console init The previous code used 64-bit registers as the target and source for load and store operations on 32-bit hardware registers. In certain cases (e.g., when using USART1 as the debug console), this could result in deadlocks where the A35 gets stuck in a permanent loop due to test conditions that are never fulfilled. To resolve this issue, 32-bit registers are now used for these operations. Change-Id: Id2c03a1df26738fe815079da042cc2dd989f4f8e Signed-off-by: Boerge Struempfel --- plat/st/stm32mp2/aarch64/stm32mp2_helper.S | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/plat/st/stm32mp2/aarch64/stm32mp2_helper.S b/plat/st/stm32mp2/aarch64/stm32mp2_helper.S index 0df3e088d..6f50cb92f 100644 --- a/plat/st/stm32mp2/aarch64/stm32mp2_helper.S +++ b/plat/st/stm32mp2/aarch64/stm32mp2_helper.S @@ -90,19 +90,19 @@ endfunc plat_my_core_pos func plat_crash_console_init /* Reset UART peripheral */ mov_imm x1, (RCC_BASE + DEBUG_UART_RST_REG) - ldr x2, =DEBUG_UART_RST_BIT - ldr x0, [x1] - orr x0, x0, x2 - str x0, [x1] + ldr w2, =DEBUG_UART_RST_BIT + ldr w0, [x1] + orr w0, w0, w2 + str w0, [x1] 1: - ldr x0, [x1] - tst x0, #DEBUG_UART_RST_BIT + ldr w0, [x1] + tst w0, #DEBUG_UART_RST_BIT beq 1b - bic x0, x0, #DEBUG_UART_RST_BIT - str x0, [x1] + bic w0, w0, #DEBUG_UART_RST_BIT + str w0, [x1] 2: - ldr x0, [x1] - tst x0, #DEBUG_UART_RST_BIT + ldr w0, [x1] + tst w0, #DEBUG_UART_RST_BIT bne 2b /* Enable GPIOs for UART TX */ mov_imm x1, (RCC_BASE + DEBUG_UART_TX_GPIO_BANK_CLK_REG)