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docs(build-options): add build macros for features FGT,AMUv1 and ECV

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This patch adds macros explicit to the features - FEAT_FGT,FEAT_AMUv1
and FEAT_ECV respectively. It assists in controlled access to the set
of registers (HDFGRTR_EL2, HAFGRTR_EL2 and CNTPOFF_EL2) under the
influence of these features during context save and restore routines.

Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: I5082ea6687a686d8c5af3fe8bf769957cf3078b0
This commit is contained in:
Jayanth Dodderi Chidanand 2021-12-05 19:21:14 +00:00
parent f74cb0be8a
commit 6401776747
1 changed files with 18 additions and 0 deletions
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18
docs/getting_started/build-options.rst
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@ -246,6 +246,24 @@ Common build options
builds, but this behaviour can be overridden in each platform's Makefile or builds, but this behaviour can be overridden in each platform's Makefile or
in the build command line. in the build command line.
- ``ENABLE_FEAT_AMUv1``: Boolean option to enable access to the HAFGRTR_EL2
(Hypervisor Activity Monitors Fine-Grained Read Trap Register) during EL2
to EL3 context save/restore operations. It is an optional feature available
on v8.4 and onwards and must be set to 1 alongside ``ENABLE_FEAT_FGT``, to
access the HAFGRTR_EL2 register. Defaults to ``0``.
- ``ENABLE_FEAT_ECV``: Boolean option to enable support for the Enhanced Counter
Virtualization feature, allowing for access to the CNTPOFF_EL2 (Counter-timer
Physical Offset register) during EL2 to EL3 context save/restore operations.
Its a mandatory architectural feature in Armv8.6 and defaults to ``1`` for
v8.6 or later CPUs.
- ``ENABLE_FEAT_FGT``: Boolean option to enable support for FGT (Fine Grain Traps)
feature allowing for access to the HDFGRTR_EL2 (Hypervisor Debug Fine-Grained
Read Trap Register) during EL2 to EL3 context save/restore operations.
Its a mandatory architectural feature in Armv8.6 and defaults to ``1`` for
v8.6 or later CPUs.
- ``ENABLE_FEAT_HCX``: This option sets the bit SCR_EL3.HXEn in EL3 to allow - ``ENABLE_FEAT_HCX``: This option sets the bit SCR_EL3.HXEn in EL3 to allow
access to HCRX_EL2 (extended hypervisor control register) from EL2 as well as access to HCRX_EL2 (extended hypervisor control register) from EL2 as well as
adding HCRX_EL2 to the EL2 context save/restore operations. adding HCRX_EL2 to the EL2 context save/restore operations.