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feat(nxp-clk): add clock objects for CGM dividers
The CGM dividers are controllable dividers attached to a CGM mux. Its divison factor can be controlled through the MC_CGM's registers. Change-Id: Id2786a46c5a1d389ca32a4839c7158949aec3b0a Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
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parent
29f8a952cb
commit
63d536fe18
2 changed files with 27 additions and 2 deletions
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@ -1136,7 +1136,7 @@ static int enable_module(struct s32cc_clk_obj *module,
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unsigned int depth)
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{
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struct s32cc_clk_obj *parent = get_module_parent(module);
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static const enable_clk_t enable_clbs[12] = {
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static const enable_clk_t enable_clbs[13] = {
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[s32cc_clk_t] = no_enable,
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[s32cc_osc_t] = enable_osc,
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[s32cc_pll_t] = enable_pll,
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@ -1867,7 +1867,7 @@ typedef struct s32cc_clk_obj *(*get_parent_clb_t)(const struct s32cc_clk_obj *cl
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static struct s32cc_clk_obj *get_module_parent(const struct s32cc_clk_obj *module)
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{
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static const get_parent_clb_t parents_clbs[12] = {
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static const get_parent_clb_t parents_clbs[13] = {
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[s32cc_clk_t] = get_clk_parent,
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[s32cc_osc_t] = get_no_parent,
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[s32cc_pll_t] = get_pll_parent,
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@ -19,6 +19,7 @@ enum s32cc_clkm_type {
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s32cc_pll_out_div_t,
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s32cc_dfs_t,
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s32cc_dfs_div_t,
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s32cc_cgm_div_t,
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s32cc_clkmux_t,
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s32cc_shared_clkmux_t,
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s32cc_fixed_div_t,
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@ -288,6 +289,22 @@ struct s32cc_part_block_link {
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.block = (BLOCK), \
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}
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struct s32cc_cgm_div {
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struct s32cc_clk_obj desc;
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struct s32cc_clk_obj *parent;
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unsigned long freq;
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uint32_t index;
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};
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#define S32CC_CGM_DIV_INIT(PARENT, INDEX) \
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{ \
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.desc = { \
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.type = s32cc_cgm_div_t, \
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}, \
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.parent = &(PARENT).desc, \
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.index = (INDEX), \
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}
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static inline struct s32cc_osc *s32cc_obj2osc(const struct s32cc_clk_obj *mod)
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{
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uintptr_t osc_addr;
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@ -400,4 +417,12 @@ s32cc_obj2partblocklink(const struct s32cc_clk_obj *mod)
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return (struct s32cc_part_block_link *)blk_link;
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}
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static inline struct s32cc_cgm_div *s32cc_obj2cgmdiv(const struct s32cc_clk_obj *mod)
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{
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uintptr_t cgm_div_addr;
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cgm_div_addr = ((uintptr_t)mod) - offsetof(struct s32cc_cgm_div, desc);
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return (struct s32cc_cgm_div *)cgm_div_addr;
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}
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#endif /* S32CC_CLK_MODULES_H */
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