From a1e07b399b5724e0d8f68a2e6ba6ce3102c2c424 Mon Sep 17 00:00:00 2001 From: Ghennadi Procopciuc Date: Tue, 26 Nov 2024 16:32:26 +0200 Subject: [PATCH 1/9] feat(s32g274a): add console mapping Add on-demand mapping of the console registers. Change-Id: I146af2306f167602710c57b637deb1845fd95aff Signed-off-by: Ghennadi Procopciuc --- plat/nxp/s32/s32g274ardb2/plat_console.c | 7 +++++++ plat/nxp/s32/s32g274ardb2/platform.mk | 4 ++++ 2 files changed, 11 insertions(+) diff --git a/plat/nxp/s32/s32g274ardb2/plat_console.c b/plat/nxp/s32/s32g274ardb2/plat_console.c index 542fa7bef..e65e43953 100644 --- a/plat/nxp/s32/s32g274ardb2/plat_console.c +++ b/plat/nxp/s32/s32g274ardb2/plat_console.c @@ -5,6 +5,7 @@ */ #include +#include #include #include #include @@ -17,6 +18,12 @@ void console_s32g2_register(void) }; int ret; + ret = mmap_add_dynamic_region(UART_BASE, UART_BASE, PAGE_SIZE, + MT_DEVICE | MT_RW | MT_SECURE); + if (ret != 0) { + panic(); + } + ret = console_linflex_register(UART_BASE, UART_CLOCK_HZ, UART_BAUDRATE, &s32g2_console); if (ret == 0) { diff --git a/plat/nxp/s32/s32g274ardb2/platform.mk b/plat/nxp/s32/s32g274ardb2/platform.mk index 7d6e960a1..e9e24181a 100644 --- a/plat/nxp/s32/s32g274ardb2/platform.mk +++ b/plat/nxp/s32/s32g274ardb2/platform.mk @@ -38,6 +38,9 @@ ERRATA_A53_1530924 := 1 ERRATA_SPECULATIVE_AT := 1 ERRATA_S32_051700 := 1 +PLAT_XLAT_TABLES_DYNAMIC := 1 +$(eval $(call add_define,PLAT_XLAT_TABLES_DYNAMIC)) + # Selecting Drivers for SoC $(eval $(call SET_NXP_MAKE_FLAG,CONSOLE_NEEDED,BL_COMM)) $(eval $(call SET_NXP_MAKE_FLAG,CLK_NEEDED,BL_COMM)) @@ -47,6 +50,7 @@ include ${PLAT_DRIVERS_PATH}/drivers.mk BL_COMMON_SOURCES += \ ${PLAT_S32G274ARDB2}/plat_console.c \ ${PLAT_S32G274ARDB2}/plat_helpers.S \ + ${XLAT_TABLES_LIB_SRCS} \ BL2_SOURCES += \ ${BL_COMMON_SOURCES} \ From 008925861f3d6b30722895bc9701b85ec3d81215 Mon Sep 17 00:00:00 2001 From: Ghennadi Procopciuc Date: Tue, 26 Nov 2024 16:42:17 +0200 Subject: [PATCH 2/9] feat(s32g274a): increase the number of MMU regions Increase the maximum number of regions allocated by the translation table library to accommodate the entries added in the next commits. Change-Id: Ib0dd2d0dbc9b4a574367141a7c96d76dd08e2c7f Signed-off-by: Ghennadi Procopciuc --- plat/nxp/s32/s32g274ardb2/include/platform_def.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/plat/nxp/s32/s32g274ardb2/include/platform_def.h b/plat/nxp/s32/s32g274ardb2/include/platform_def.h index 1a4c495aa..cb166581d 100644 --- a/plat/nxp/s32/s32g274ardb2/include/platform_def.h +++ b/plat/nxp/s32/s32g274ardb2/include/platform_def.h @@ -48,7 +48,7 @@ /* We'll be doing a 1:1 mapping anyway */ #define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 36) -#define MAX_MMAP_REGIONS U(8) +#define MAX_MMAP_REGIONS U(18) #define MAX_XLAT_TABLES U(32) /* Console settings */ From 514c738045b5c2de0f8e99b68830322af88dad4d Mon Sep 17 00:00:00 2001 From: Ghennadi Procopciuc Date: Tue, 26 Nov 2024 16:39:41 +0200 Subject: [PATCH 3/9] feat(nxp-clk): dynamic map of the clock modules Add all clock modules as entries in MMU using dynamic regions. Change-Id: I56f724ced4bd024554c7b38afd14ea420de80cc6 Signed-off-by: Ghennadi Procopciuc --- drivers/nxp/clk/s32cc/s32cc_clk_drv.c | 43 ++++++++++++++++++- drivers/nxp/clk/s32cc/s32cc_early_clks.c | 5 ++- .../drivers/nxp/clk/s32cc/s32cc-clk-utils.h | 2 +- 3 files changed, 47 insertions(+), 3 deletions(-) diff --git a/drivers/nxp/clk/s32cc/s32cc_clk_drv.c b/drivers/nxp/clk/s32cc/s32cc_clk_drv.c index 9b5760753..ed331bf1c 100644 --- a/drivers/nxp/clk/s32cc/s32cc_clk_drv.c +++ b/drivers/nxp/clk/s32cc/s32cc_clk_drv.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -1464,7 +1465,39 @@ static int s32cc_clk_set_parent(unsigned long id, unsigned long parent_id) return 0; } -void s32cc_clk_register_drv(void) +static int s32cc_clk_mmap_regs(const struct s32cc_clk_drv *drv) +{ + const uintptr_t base_addrs[11] = { + drv->fxosc_base, + drv->armpll_base, + drv->periphpll_base, + drv->armdfs_base, + drv->cgm0_base, + drv->cgm1_base, + drv->cgm5_base, + drv->ddrpll_base, + drv->mc_me, + drv->mc_rgm, + drv->rdc, + }; + size_t i; + int ret; + + for (i = 0U; i < ARRAY_SIZE(base_addrs); i++) { + ret = mmap_add_dynamic_region(base_addrs[i], base_addrs[i], + PAGE_SIZE, + MT_DEVICE | MT_RW | MT_SECURE); + if (ret != 0) { + ERROR("Failed to map clock module 0x%" PRIuPTR "\n", + base_addrs[i]); + return ret; + } + } + + return 0; +} + +int s32cc_clk_register_drv(void) { static const struct clk_ops s32cc_clk_ops = { .enable = s32cc_clk_enable, @@ -1475,7 +1508,15 @@ void s32cc_clk_register_drv(void) .get_parent = s32cc_clk_get_parent, .set_parent = s32cc_clk_set_parent, }; + const struct s32cc_clk_drv *drv; clk_register(&s32cc_clk_ops); + + drv = get_drv(); + if (drv == NULL) { + return -EINVAL; + } + + return s32cc_clk_mmap_regs(drv); } diff --git a/drivers/nxp/clk/s32cc/s32cc_early_clks.c b/drivers/nxp/clk/s32cc/s32cc_early_clks.c index 02b9df93c..06936a573 100644 --- a/drivers/nxp/clk/s32cc/s32cc_early_clks.c +++ b/drivers/nxp/clk/s32cc/s32cc_early_clks.c @@ -184,7 +184,10 @@ int s32cc_init_early_clks(void) { int ret; - s32cc_clk_register_drv(); + ret = s32cc_clk_register_drv(); + if (ret != 0) { + return ret; + } ret = setup_fxosc(); if (ret != 0) { diff --git a/include/drivers/nxp/clk/s32cc/s32cc-clk-utils.h b/include/drivers/nxp/clk/s32cc/s32cc-clk-utils.h index e6adeccd7..1d08f736b 100644 --- a/include/drivers/nxp/clk/s32cc/s32cc-clk-utils.h +++ b/include/drivers/nxp/clk/s32cc/s32cc-clk-utils.h @@ -18,6 +18,6 @@ int s32cc_get_id_from_table(const struct s32cc_clk_array *const *clk_arr, struct s32cc_clk *s32cc_get_arch_clk(unsigned long id); int s32cc_get_clk_id(const struct s32cc_clk *clk, unsigned long *id); -void s32cc_clk_register_drv(void); +int s32cc_clk_register_drv(void); #endif /* S32CC_CLK_UTILS_H */ From 34fb2b35b9996d2afe40ad52f3a004bb90bf95f2 Mon Sep 17 00:00:00 2001 From: Ghennadi Procopciuc Date: Tue, 26 Nov 2024 16:45:36 +0200 Subject: [PATCH 4/9] feat(s32g274a): map each image before its loading The regions used by the stages loaded by BL2 must be mapped before they can be used. Change-Id: Ia70f8c5f35d7930e2b20f1a26be0ad2cdfea2b1a Signed-off-by: Khristine Andreea Barbulescu Signed-off-by: Ghennadi Procopciuc --- .../nxp/s32/s32g274ardb2/plat_bl2_el3_setup.c | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/plat/nxp/s32/s32g274ardb2/plat_bl2_el3_setup.c b/plat/nxp/s32/s32g274ardb2/plat_bl2_el3_setup.c index 4645f01ed..7977a031d 100644 --- a/plat/nxp/s32/s32g274ardb2/plat_bl2_el3_setup.c +++ b/plat/nxp/s32/s32g274ardb2/plat_bl2_el3_setup.c @@ -4,9 +4,11 @@ * SPDX-License-Identifier: BSD-3-Clause */ +#include #include #include #include +#include #include #include #include @@ -78,3 +80,26 @@ void bl2_el3_plat_arch_setup(void) { } +int bl2_plat_handle_pre_image_load(unsigned int image_id) +{ + const struct bl_mem_params_node *desc = get_bl_mem_params_node(image_id); + const struct image_info *img_info; + size_t size; + + if (desc == NULL) { + return -EINVAL; + } + + img_info = &desc->image_info; + + if ((img_info == NULL) || (img_info->image_max_size == 0U)) { + return -EINVAL; + } + + size = page_align(img_info->image_max_size, UP); + + return mmap_add_dynamic_region(img_info->image_base, + img_info->image_base, + size, + MT_MEMORY | MT_RW | MT_SECURE); +} From 507ce7ed6f5c2c34a94f18c6d66db27b163e0f2a Mon Sep 17 00:00:00 2001 From: Ghennadi Procopciuc Date: Tue, 26 Nov 2024 16:54:48 +0200 Subject: [PATCH 5/9] feat(s32g274a): dynamically map siul2 and fip img Dynamically map the remaining regions part of the BL2 stages using dynamic regions. Change-Id: Ia81666920b941218ddaa7d3244dfa5212525c75d Signed-off-by: Ghennadi Procopciuc --- .../nxp/s32/s32g274ardb2/plat_bl2_el3_setup.c | 36 ++++++++++++++----- 1 file changed, 28 insertions(+), 8 deletions(-) diff --git a/plat/nxp/s32/s32g274ardb2/plat_bl2_el3_setup.c b/plat/nxp/s32/s32g274ardb2/plat_bl2_el3_setup.c index 7977a031d..a8c283108 100644 --- a/plat/nxp/s32/s32g274ardb2/plat_bl2_el3_setup.c +++ b/plat/nxp/s32/s32g274ardb2/plat_bl2_el3_setup.c @@ -15,6 +15,7 @@ #include #include +#define SIUL20_BASE UL(0x4009C000) #define SIUL2_PC09_MSCR UL(0x4009C2E4) #define SIUL2_PC10_MSCR UL(0x4009C2E8) #define SIUL2_PC10_LIN0_IMCR UL(0x4009CA40) @@ -40,6 +41,20 @@ void plat_flush_next_bl_params(void) void bl2_platform_setup(void) { + int ret; + + ret = mmap_add_dynamic_region(S32G_FIP_BASE, S32G_FIP_BASE, + S32G_FIP_SIZE, + MT_MEMORY | MT_RW | MT_SECURE); + if (ret != 0) { + panic(); + } +} + +static int s32g_mmap_siul2(void) +{ + return mmap_add_dynamic_region(SIUL20_BASE, SIUL20_BASE, PAGE_SIZE, + MT_DEVICE | MT_RW | MT_SECURE); } static void linflex_config_pinctrl(void) @@ -57,14 +72,6 @@ void bl2_el3_early_platform_setup(u_register_t arg0, u_register_t arg1, { int ret; - ret = s32cc_init_early_clks(); - if (ret != 0) { - panic(); - } - - linflex_config_pinctrl(); - console_s32g2_register(); - /* Restore (clear) the CAIUTC[IsolEn] bit for the primary cluster, which * we have manually set during early BL2 boot. */ @@ -73,6 +80,19 @@ void bl2_el3_early_platform_setup(u_register_t arg0, u_register_t arg1, ncore_init(); ncore_caiu_online(A53_CLUSTER0_CAIU); + ret = s32cc_init_early_clks(); + if (ret != 0) { + panic(); + } + + ret = s32g_mmap_siul2(); + if (ret != 0) { + panic(); + } + + linflex_config_pinctrl(); + console_s32g2_register(); + plat_s32g2_io_setup(); } From eb4d4185fa67edb6d137a5f7a0eb5e209b4e6299 Mon Sep 17 00:00:00 2001 From: Ghennadi Procopciuc Date: Tue, 26 Nov 2024 16:55:30 +0200 Subject: [PATCH 6/9] feat(s32g274a): enable MMU for BL2 stage Enable the MMU and add two entries to map the BL2 code and data regions. Additional mappings will be added dynamically, enhancing flexibility and modularity during the porting process. Change-Id: I107abf944dfdce9dcff47b08272a5001484de8a9 Signed-off-by: Ghennadi Procopciuc --- .../s32g274ardb2/include/s32cc-bl-common.h | 12 ++++++ .../nxp/s32/s32g274ardb2/plat_bl2_el3_setup.c | 8 ++++ plat/nxp/s32/s32g274ardb2/platform.mk | 1 + plat/nxp/s32/s32g274ardb2/s32cc_bl_common.c | 40 +++++++++++++++++++ 4 files changed, 61 insertions(+) create mode 100644 plat/nxp/s32/s32g274ardb2/include/s32cc-bl-common.h create mode 100644 plat/nxp/s32/s32g274ardb2/s32cc_bl_common.c diff --git a/plat/nxp/s32/s32g274ardb2/include/s32cc-bl-common.h b/plat/nxp/s32/s32g274ardb2/include/s32cc-bl-common.h new file mode 100644 index 000000000..0f0c8041c --- /dev/null +++ b/plat/nxp/s32/s32g274ardb2/include/s32cc-bl-common.h @@ -0,0 +1,12 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef S32CC_BL_COMMON_H +#define S32CC_BL_COMMON_H + +int s32cc_bl_mmu_setup(void); + +#endif /* S32CC_BL_COMMON_H */ diff --git a/plat/nxp/s32/s32g274ardb2/plat_bl2_el3_setup.c b/plat/nxp/s32/s32g274ardb2/plat_bl2_el3_setup.c index a8c283108..2254bf5ad 100644 --- a/plat/nxp/s32/s32g274ardb2/plat_bl2_el3_setup.c +++ b/plat/nxp/s32/s32g274ardb2/plat_bl2_el3_setup.c @@ -5,6 +5,7 @@ */ #include + #include #include #include @@ -12,7 +13,9 @@ #include #include #include + #include +#include #include #define SIUL20_BASE UL(0x4009C000) @@ -80,6 +83,11 @@ void bl2_el3_early_platform_setup(u_register_t arg0, u_register_t arg1, ncore_init(); ncore_caiu_online(A53_CLUSTER0_CAIU); + ret = s32cc_bl_mmu_setup(); + if (ret != 0) { + panic(); + } + ret = s32cc_init_early_clks(); if (ret != 0) { panic(); diff --git a/plat/nxp/s32/s32g274ardb2/platform.mk b/plat/nxp/s32/s32g274ardb2/platform.mk index e9e24181a..4ec7cd04f 100644 --- a/plat/nxp/s32/s32g274ardb2/platform.mk +++ b/plat/nxp/s32/s32g274ardb2/platform.mk @@ -50,6 +50,7 @@ include ${PLAT_DRIVERS_PATH}/drivers.mk BL_COMMON_SOURCES += \ ${PLAT_S32G274ARDB2}/plat_console.c \ ${PLAT_S32G274ARDB2}/plat_helpers.S \ + ${PLAT_S32G274ARDB2}/s32cc_bl_common.c \ ${XLAT_TABLES_LIB_SRCS} \ BL2_SOURCES += \ diff --git a/plat/nxp/s32/s32g274ardb2/s32cc_bl_common.c b/plat/nxp/s32/s32g274ardb2/s32cc_bl_common.c new file mode 100644 index 000000000..466443849 --- /dev/null +++ b/plat/nxp/s32/s32g274ardb2/s32cc_bl_common.c @@ -0,0 +1,40 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include + +#include +#include + +#include + +int s32cc_bl_mmu_setup(void) +{ + const unsigned long code_start = BL_CODE_BASE; + const unsigned long rw_start = BL_CODE_END; + unsigned long code_size; + unsigned long rw_size; + + if (code_start > BL_CODE_END) { + return -EINVAL; + } + + if (rw_start > BL_END) { + return -EINVAL; + } + + code_size = BL_CODE_END - code_start; + rw_size = BL_END - rw_start; + + mmap_add_region(code_start, code_start, code_size, + MT_RO | MT_MEMORY | MT_SECURE); + mmap_add_region(rw_start, rw_start, rw_size, + MT_RW | MT_MEMORY | MT_SECURE); + + init_xlat_tables(); + enable_mmu_el3(0); + + return 0; +} From 5680f81cecbbbb8a584dcf62bcb766a1cb25345f Mon Sep 17 00:00:00 2001 From: Ghennadi Procopciuc Date: Tue, 26 Nov 2024 17:05:31 +0200 Subject: [PATCH 7/9] feat(s32g274a): dynamically map GIC regions Dynamically add entries for the GIC distributor and all its redistributors for the cases when the platform is booted using enabled MMU. Change-Id: Ia810ec2329993057173e8fc25620a3df59b1e55d Signed-off-by: Ghennadi Procopciuc --- plat/nxp/s32/s32g274ardb2/plat_bl31_setup.c | 34 ++++++++++++++++++++- 1 file changed, 33 insertions(+), 1 deletion(-) diff --git a/plat/nxp/s32/s32g274ardb2/plat_bl31_setup.c b/plat/nxp/s32/s32g274ardb2/plat_bl31_setup.c index 03bf35cc1..ddd0e29bc 100644 --- a/plat/nxp/s32/s32g274ardb2/plat_bl31_setup.c +++ b/plat/nxp/s32/s32g274ardb2/plat_bl31_setup.c @@ -4,7 +4,9 @@ * SPDX-License-Identifier: BSD-3-Clause */ +#include #include +#include #include #include @@ -42,6 +44,31 @@ struct entry_point_info *bl31_plat_get_next_image_ep_info(uint32_t type) return &bl33_image_ep_info; } +static int mmap_gic(const gicv3_driver_data_t *gic_data) +{ + size_t gicr_size; + int ret; + + ret = mmap_add_dynamic_region(gic_data->gicd_base, + gic_data->gicd_base, + PAGE_SIZE_64KB, + MT_DEVICE | MT_RW | MT_SECURE); + if (ret != 0) { + return ret; + } + + gicr_size = gicv3_redist_size(0x0U); + ret = mmap_add_dynamic_region(gic_data->gicr_base, + gic_data->gicr_base, + gicr_size * gic_data->rdistif_num, + MT_DEVICE | MT_RW | MT_SECURE); + if (ret != 0) { + return ret; + } + + return 0; +} + void bl31_platform_setup(void) { static uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT]; @@ -52,8 +79,13 @@ void bl31_platform_setup(void) .rdistif_base_addrs = rdistif_base_addrs, .mpidr_to_core_pos = s32g2_mpidr_to_core_pos, }; - unsigned int pos = plat_my_core_pos(); + int ret; + + ret = mmap_gic(&plat_gic_data); + if (ret != 0) { + panic(); + } gicv3_driver_init(&plat_gic_data); gicv3_distif_init(); From e2ae6ceccc6fc96debbfbacfb4b288cbf78da0f2 Mon Sep 17 00:00:00 2001 From: Ghennadi Procopciuc Date: Tue, 26 Nov 2024 17:05:58 +0200 Subject: [PATCH 8/9] feat(s32g274a): enable MMU for BL31 stage Enable the MMU and add two entries to map the BL31 code and data regions. Additional mappings will be added dynamically, enhancing flexibility and modularity during the porting process. Change-Id: I333c34c58274a115f62f54730bba5b71165e3e36 Signed-off-by: Ghennadi Procopciuc --- plat/nxp/s32/s32g274ardb2/plat_bl31_setup.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/plat/nxp/s32/s32g274ardb2/plat_bl31_setup.c b/plat/nxp/s32/s32g274ardb2/plat_bl31_setup.c index ddd0e29bc..22c66b00e 100644 --- a/plat/nxp/s32/s32g274ardb2/plat_bl31_setup.c +++ b/plat/nxp/s32/s32g274ardb2/plat_bl31_setup.c @@ -10,6 +10,8 @@ #include #include +#include + static entry_point_info_t bl33_image_ep_info; static unsigned int s32g2_mpidr_to_core_pos(unsigned long mpidr); @@ -27,8 +29,6 @@ static uint32_t get_spsr_for_bl33_entry(void) void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3) { - console_s32g2_register(); - SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); bl33_image_ep_info.pc = BL33_BASE; bl33_image_ep_info.spsr = get_spsr_for_bl33_entry(); @@ -37,6 +37,14 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, void bl31_plat_arch_setup(void) { + int ret; + + ret = s32cc_bl_mmu_setup(); + if (ret != 0) { + panic(); + } + + console_s32g2_register(); } struct entry_point_info *bl31_plat_get_next_image_ep_info(uint32_t type) From 61b5ef21af8bcb38d3492e15d1d3d1fbecf3cf49 Mon Sep 17 00:00:00 2001 From: Ghennadi Procopciuc Date: Wed, 27 Nov 2024 12:33:26 +0200 Subject: [PATCH 9/9] feat(s32g274a): split early clock initialization Initializing all early clocks before the MMU is enabled can impact boot time. Therefore, splitting the setup into A53 clocks and peripheral clocks can be beneficial, with the peripheral clocks configured after fully initializing the MMU. Change-Id: I19644227b66effab8e2c43e64e057ea0c8625ebc Signed-off-by: Ghennadi Procopciuc --- drivers/nxp/clk/s32cc/s32cc_clk_drv.c | 8 ++++++-- drivers/nxp/clk/s32cc/s32cc_early_clks.c | 16 ++++++++++++++-- include/drivers/nxp/clk/s32cc/s32cc-clk-drv.h | 1 + include/drivers/nxp/clk/s32cc/s32cc-clk-utils.h | 3 ++- plat/nxp/s32/s32g274ardb2/plat_bl2_el3_setup.c | 5 +++++ 5 files changed, 28 insertions(+), 5 deletions(-) diff --git a/drivers/nxp/clk/s32cc/s32cc_clk_drv.c b/drivers/nxp/clk/s32cc/s32cc_clk_drv.c index ed331bf1c..235b9889a 100644 --- a/drivers/nxp/clk/s32cc/s32cc_clk_drv.c +++ b/drivers/nxp/clk/s32cc/s32cc_clk_drv.c @@ -1497,7 +1497,7 @@ static int s32cc_clk_mmap_regs(const struct s32cc_clk_drv *drv) return 0; } -int s32cc_clk_register_drv(void) +int s32cc_clk_register_drv(bool mmap_regs) { static const struct clk_ops s32cc_clk_ops = { .enable = s32cc_clk_enable, @@ -1517,6 +1517,10 @@ int s32cc_clk_register_drv(void) return -EINVAL; } - return s32cc_clk_mmap_regs(drv); + if (mmap_regs) { + return s32cc_clk_mmap_regs(drv); + } + + return 0; } diff --git a/drivers/nxp/clk/s32cc/s32cc_early_clks.c b/drivers/nxp/clk/s32cc/s32cc_early_clks.c index 06936a573..f001568f4 100644 --- a/drivers/nxp/clk/s32cc/s32cc_early_clks.c +++ b/drivers/nxp/clk/s32cc/s32cc_early_clks.c @@ -180,11 +180,11 @@ static int enable_ddr_clk(void) return ret; } -int s32cc_init_early_clks(void) +int s32cc_init_core_clocks(void) { int ret; - ret = s32cc_clk_register_drv(); + ret = s32cc_clk_register_drv(false); if (ret != 0) { return ret; } @@ -209,6 +209,18 @@ int s32cc_init_early_clks(void) return ret; } + return ret; +} + +int s32cc_init_early_clks(void) +{ + int ret; + + ret = s32cc_clk_register_drv(true); + if (ret != 0) { + return ret; + } + ret = setup_periph_pll(); if (ret != 0) { return ret; diff --git a/include/drivers/nxp/clk/s32cc/s32cc-clk-drv.h b/include/drivers/nxp/clk/s32cc/s32cc-clk-drv.h index d879f5bed..632b82fc1 100644 --- a/include/drivers/nxp/clk/s32cc/s32cc-clk-drv.h +++ b/include/drivers/nxp/clk/s32cc/s32cc-clk-drv.h @@ -6,6 +6,7 @@ #ifndef S32CC_CLK_DRV_H #define S32CC_CLK_DRV_H +int s32cc_init_core_clocks(void); int s32cc_init_early_clks(void); #endif diff --git a/include/drivers/nxp/clk/s32cc/s32cc-clk-utils.h b/include/drivers/nxp/clk/s32cc/s32cc-clk-utils.h index 1d08f736b..c6e90f056 100644 --- a/include/drivers/nxp/clk/s32cc/s32cc-clk-utils.h +++ b/include/drivers/nxp/clk/s32cc/s32cc-clk-utils.h @@ -5,6 +5,7 @@ #ifndef S32CC_CLK_UTILS_H #define S32CC_CLK_UTILS_H +#include #include struct s32cc_clk *s32cc_get_clk_from_table(const struct s32cc_clk_array *const *clk_arr, @@ -18,6 +19,6 @@ int s32cc_get_id_from_table(const struct s32cc_clk_array *const *clk_arr, struct s32cc_clk *s32cc_get_arch_clk(unsigned long id); int s32cc_get_clk_id(const struct s32cc_clk *clk, unsigned long *id); -int s32cc_clk_register_drv(void); +int s32cc_clk_register_drv(bool mmap_regs); #endif /* S32CC_CLK_UTILS_H */ diff --git a/plat/nxp/s32/s32g274ardb2/plat_bl2_el3_setup.c b/plat/nxp/s32/s32g274ardb2/plat_bl2_el3_setup.c index 2254bf5ad..0929f9d84 100644 --- a/plat/nxp/s32/s32g274ardb2/plat_bl2_el3_setup.c +++ b/plat/nxp/s32/s32g274ardb2/plat_bl2_el3_setup.c @@ -83,6 +83,11 @@ void bl2_el3_early_platform_setup(u_register_t arg0, u_register_t arg1, ncore_init(); ncore_caiu_online(A53_CLUSTER0_CAIU); + ret = s32cc_init_core_clocks(); + if (ret != 0) { + panic(); + } + ret = s32cc_bl_mmu_setup(); if (ret != 0) { panic();