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Merge pull request #1533 from jeenu-arm/mpam
AArch64: Enable MPAM for lower ELs
This commit is contained in:
commit
61e7c0542e
9 changed files with 100 additions and 0 deletions
2
Makefile
2
Makefile
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@ -550,6 +550,7 @@ $(eval $(call assert_boolean,DYN_DISABLE_AUTH))
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$(eval $(call assert_boolean,EL3_EXCEPTION_HANDLING))
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$(eval $(call assert_boolean,ENABLE_AMU))
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$(eval $(call assert_boolean,ENABLE_ASSERTIONS))
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$(eval $(call assert_boolean,ENABLE_MPAM_FOR_LOWER_ELS))
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$(eval $(call assert_boolean,ENABLE_PLAT_COMPAT))
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$(eval $(call assert_boolean,ENABLE_PMF))
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$(eval $(call assert_boolean,ENABLE_PSCI_STAT))
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@ -601,6 +602,7 @@ $(eval $(call add_define,CTX_INCLUDE_FPREGS))
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$(eval $(call add_define,EL3_EXCEPTION_HANDLING))
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$(eval $(call add_define,ENABLE_AMU))
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$(eval $(call add_define,ENABLE_ASSERTIONS))
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$(eval $(call add_define,ENABLE_MPAM_FOR_LOWER_ELS))
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$(eval $(call add_define,ENABLE_PLAT_COMPAT))
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$(eval $(call add_define,ENABLE_PMF))
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$(eval $(call add_define,ENABLE_PSCI_STAT))
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@ -64,6 +64,10 @@ ifeq (${ENABLE_SVE_FOR_NS},1)
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BL31_SOURCES += lib/extensions/sve/sve.c
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endif
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ifeq (${ENABLE_MPAM_FOR_LOWER_ELS},1)
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BL31_SOURCES += lib/extensions/mpam/mpam.c
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endif
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ifeq (${WORKAROUND_CVE_2017_5715},1)
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BL31_SOURCES += lib/cpus/aarch64/wa_cve_2017_5715_bpiall.S \
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lib/cpus/aarch64/wa_cve_2017_5715_mmu.S
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@ -351,6 +351,17 @@ Common build options
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that is only required for the assertion and does not fit in the assertion
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itself.
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- ``ENABLE_MPAM_FOR_LOWER_ELS``: Boolean option to enable lower ELs to use MPAM
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feature. MPAM is an optional Armv8.4 extension that enables various memory
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system components and resources to define partitions; software running at
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various ELs can assign themselves to desired partition to control their
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performance aspects.
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When this option is set to ``1``, EL3 allows lower ELs to access their own
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MPAM registers without trapping into EL3. This option doesn't make use of
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partitioning in EL3, however. Platform initialisation code should configure
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and use partitions in EL3 as required. This option defaults to ``0``.
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- ``ENABLE_PMF``: Boolean option to enable support for optional Performance
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Measurement Framework(PMF). Default is 0.
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@ -117,6 +117,8 @@
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#define ID_AA64PFR0_SVE_SHIFT U(32)
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#define ID_AA64PFR0_SVE_MASK ULL(0xf)
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#define ID_AA64PFR0_SVE_LENGTH U(4)
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#define ID_AA64PFR0_MPAM_SHIFT U(40)
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#define ID_AA64PFR0_MPAM_MASK ULL(0xf)
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#define ID_AA64PFR0_CSV2_SHIFT U(56)
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#define ID_AA64PFR0_CSV2_MASK ULL(0xf)
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#define ID_AA64PFR0_CSV2_LENGTH U(4)
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@ -657,6 +659,14 @@
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******************************************************************************/
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#define PMBLIMITR_EL1 S3_0_C9_C10_0
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/*******************************************************************************
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* Definitions for system register interface to MPAM
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******************************************************************************/
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#define MPAMIDR_EL1 S3_0_C10_C4_4
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#define MPAM2_EL2 S3_4_C10_C5_0
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#define MPAMHCR_EL2 S3_4_C10_C4_0
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#define MPAM3_EL3 S3_6_C10_C5_0
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/*******************************************************************************
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* Definitions for system register interface to AMU for ARMv8.4 onwards
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******************************************************************************/
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@ -722,6 +732,11 @@
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#define AMCGCR_EL0_CG1NC_LENGTH U(8)
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#define AMCGCR_EL0_CG1NC_MASK U(0xff)
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/* MPAM register definitions */
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#define MPAM3_EL3_MPAMEN_BIT (ULL(1) << 63)
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#define MPAMIDR_HAS_HCR_BIT (ULL(1) << 17)
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/*******************************************************************************
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* RAS system registers
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*******************************************************************************/
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@ -328,6 +328,11 @@ DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenset0_el0, AMCNTENSET0_EL0)
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DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenclr1_el0, AMCNTENCLR1_EL0)
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DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenset1_el0, AMCNTENSET1_EL0)
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DEFINE_RENAME_SYSREG_READ_FUNC(mpamidr_el1, MPAMIDR_EL1)
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DEFINE_RENAME_SYSREG_RW_FUNCS(mpam3_el3, MPAM3_EL3)
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DEFINE_RENAME_SYSREG_RW_FUNCS(mpam2_el2, MPAM2_EL2)
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DEFINE_RENAME_SYSREG_RW_FUNCS(mpamhcr_el2, MPAMHCR_EL2)
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DEFINE_RENAME_SYSREG_RW_FUNCS(pmblimitr_el1, PMBLIMITR_EL1)
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DEFINE_RENAME_SYSREG_WRITE_FUNC(zcr_el3, ZCR_EL3)
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15
include/lib/extensions/mpam.h
Normal file
15
include/lib/extensions/mpam.h
Normal file
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@ -0,0 +1,15 @@
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/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef MPAM_H
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#define MPAM_H
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#include <stdbool.h>
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bool mpam_supported(void);
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void mpam_enable(int el2_unused);
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#endif /* MPAM_H */
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@ -12,6 +12,7 @@
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#include <context.h>
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#include <context_mgmt.h>
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#include <interrupt_mgmt.h>
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#include <mpam.h>
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#include <platform.h>
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#include <platform_def.h>
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#include <pubsub_events.h>
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@ -244,6 +245,10 @@ static void enable_extensions_nonsecure(int el2_unused)
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#if ENABLE_SVE_FOR_NS
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sve_enable(el2_unused);
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#endif
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#if ENABLE_MPAM_FOR_LOWER_ELS
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mpam_enable(el2_unused);
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#endif
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#endif
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}
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40
lib/extensions/mpam/mpam.c
Normal file
40
lib/extensions/mpam/mpam.c
Normal file
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@ -0,0 +1,40 @@
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/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <arch_helpers.h>
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#include <mpam.h>
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#include <stdbool.h>
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bool mpam_supported(void)
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{
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uint64_t features = read_id_aa64dfr0_el1() >> ID_AA64PFR0_MPAM_SHIFT;
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return ((features & ID_AA64PFR0_MPAM_MASK) != 0U);
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}
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void mpam_enable(int el2_unused)
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{
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if (!mpam_supported())
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return;
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/*
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* Enable MPAM, and disable trapping to EL3 when lower ELs access their
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* own MPAM registers.
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*/
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write_mpam3_el3(MPAM3_EL3_MPAMEN_BIT);
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/*
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* If EL2 is implemented but unused, disable trapping to EL2 when lower
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* ELs access their own MPAM registers.
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*/
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if (el2_unused != 0) {
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write_mpam2_el2(0);
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if ((read_mpamidr_el1() & MPAMIDR_HAS_HCR_BIT) != 0U)
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write_mpamhcr_el2(0);
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}
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}
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@ -62,6 +62,9 @@ DEFAULT_PLAT := fvp
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# development platforms.
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DYN_DISABLE_AUTH := 0
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# Build option to enable MPAM for lower ELs
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ENABLE_MPAM_FOR_LOWER_ELS := 0
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# Flag to enable Performance Measurement Framework
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ENABLE_PMF := 0
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