Djam/arm-trusted-firmware
1
0
Fork 0
mirror of https://github.com/ARM-software/arm-trusted-firmware.git synced 2025-04-16 17:44:19 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

Merge "refactor(mte): deprecate CTX_INCLUDE_MTE_REGS" into integration

Browse source
This commit is contained in:
Manish V Badarkhe 2024-01-24 11:05:32 +01:00 • committed by TrustedFirmware Code Review
commit 61dfdfd4db
12 changed files with 48 additions and 72 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

12
Makefile
View file

@ -1,5 +1,5 @@
#
# Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
# Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@ -935,12 +935,6 @@ ifeq ($(CTX_INCLUDE_PAUTH_REGS),1)
endif
endif #(CTX_INCLUDE_PAUTH_REGS)
ifeq ($(CTX_INCLUDE_MTE_REGS),1)
ifneq (${ARCH},aarch64)
$(error CTX_INCLUDE_MTE_REGS requires AArch64)
endif
endif #(CTX_INCLUDE_MTE_REGS)
ifeq ($(PSA_FWU_SUPPORT),1)
$(info PSA_FWU_SUPPORT is an experimental feature)
endif #(PSA_FWU_SUPPORT)
@ -1254,7 +1248,6 @@ $(eval $(call assert_numerics,\
ARM_ARCH_MINOR \
BRANCH_PROTECTION \
CTX_INCLUDE_PAUTH_REGS \
CTX_INCLUDE_MTE_REGS \
CTX_INCLUDE_NEVE_REGS \
CRYPTO_SUPPORT \
DISABLE_MTPMU \
@ -1269,6 +1262,7 @@ $(eval $(call assert_numerics,\
ENABLE_FEAT_ECV \
ENABLE_FEAT_FGT \
ENABLE_FEAT_HCX \
ENABLE_FEAT_MTE \
ENABLE_FEAT_PAN \
ENABLE_FEAT_RNG \
ENABLE_FEAT_RNG_TRAP \
@ -1324,7 +1318,6 @@ $(eval $(call add_defines,\
CTX_INCLUDE_PAUTH_REGS \
CTX_INCLUDE_MPAM_REGS \
EL3_EXCEPTION_HANDLING \
CTX_INCLUDE_MTE_REGS \
CTX_INCLUDE_EL2_REGS \
CTX_INCLUDE_NEVE_REGS \
DECRYPTION_SUPPORT_${DECRYPTION_SUPPORT} \
@ -1427,6 +1420,7 @@ $(eval $(call add_defines,\
ENABLE_FEAT_S2POE \
ENABLE_FEAT_S1POE \
ENABLE_FEAT_GCS \
ENABLE_FEAT_MTE \
ENABLE_FEAT_MTE_PERM \
FEATURE_DETECTION \
TWED_DELAY \

4
bl32/tsp/tsp_main.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -238,7 +238,7 @@ smc_args_t *tsp_smc_handler(uint64_t func,
service_arg0 = (uint64_t)service_args;
service_arg1 = (uint64_t)(service_args >> 64U);
#if CTX_INCLUDE_MTE_REGS
#if ENABLE_FEAT_MTE
/*
* Write a dummy value to an MTE register, to simulate usage in the
* secure world

17
common/feat_detect.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2022-2023, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2022-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -70,18 +70,6 @@ static void read_feat_pauth(void)
#endif
}
/************************************************
* Feature : FEAT_MTE (Memory Tagging Extension)
***********************************************/
static void read_feat_mte(void)
{
#if (CTX_INCLUDE_MTE_REGS == FEAT_STATE_ALWAYS)
unsigned int mte = get_armv8_5_mte_support();
feat_detect_panic((mte != MTE_UNIMPLEMENTED), "MTE");
#endif
}
/****************************************************
* Feature : FEAT_BTI (Branch Target Identification)
***************************************************/
@ -179,7 +167,8 @@ void detect_arch_features(void)
"TRF", 1, 1);
/* v8.5 features */
read_feat_mte();
check_feature(ENABLE_FEAT_MTE, read_feat_mte_id_field(), "MTE",
MTE_IMPLEMENTED_EL0, MTE_IMPLEMENTED_ASY);
check_feature(ENABLE_FEAT_RNG, read_feat_rng_id_field(), "RNG", 1, 1);
read_feat_bti();
read_feat_rng_trap();

6
docs/components/secure-partition-manager.rst
View file

@ -215,7 +215,7 @@ implemented and the SPMC is located at S-EL2:
ARM_ARCH_MINOR=5 \
BRANCH_PROTECTION=1 \
CTX_INCLUDE_PAUTH_REGS=1 \
CTX_INCLUDE_MTE_REGS=1 \
ENABLE_FEAT_MTE=1 \
BL32=<path-to-hafnium-binary> \
BL33=<path-to-bl33-binary> \
SP_LAYOUT_FILE=sp_layout.json \
@ -233,7 +233,7 @@ implemented, the SPMC is located at S-EL2, and enabling secure boot:
ARM_ARCH_MINOR=5 \
BRANCH_PROTECTION=1 \
CTX_INCLUDE_PAUTH_REGS=1 \
CTX_INCLUDE_MTE_REGS=1 \
ENABLE_FEAT_MTE=1 \
BL32=<path-to-hafnium-binary> \
BL33=<path-to-bl33-binary> \
SP_LAYOUT_FILE=sp_layout.json \
@ -1670,4 +1670,4 @@ Client <https://developer.arm.com/documentation/den0006/d/>`__
--------------
*Copyright (c) 2020-2023, Arm Limited and Contributors. All rights reserved.*
*Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.*

4
docs/design/firmware-design.rst
View file

@ -2771,7 +2771,7 @@ Armv8.5-A
(at EL0 and S-EL0) if it is only supported at EL0. If instead it is
implemented at all ELs, it is unconditionally enabled for only the normal
world. To enable it for the secure world as well, the build option
``CTX_INCLUDE_MTE_REGS`` is required. If the hardware does not implement
``ENABLE_FEAT_MTE`` is required. If the hardware does not implement
MTE support at all, it is always disabled, no matter what build options
are used.
@ -2860,7 +2860,7 @@ kernel at boot time. These can be found in the ``fdts`` directory.
--------------
*Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.*
*Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.*
.. _SMCCC: https://developer.arm.com/docs/den0028/latest
.. _PSCI: https://developer.arm.com/documentation/den0022/latest/

13
docs/getting_started/build-options.rst
View file

@ -185,12 +185,6 @@ Common build options
registers to be included when saving and restoring the CPU context.
Default is '0'.
- ``CTX_INCLUDE_MTE_REGS``: Numeric value to include Memory Tagging Extension
registers in cpu context. This must be enabled, if the platform wants to use
this feature in the Secure world and MTE is enabled at ELX. This flag can
take values 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism.
Default value is 0.
- ``CTX_INCLUDE_NEVE_REGS``: Numeric value, when set will cause the Armv8.4-NV
registers to be saved/restored when entering/exiting an EL2 execution
context. This flag can take values 0 to 2, to align with the
@ -313,6 +307,11 @@ Common build options
flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION``
mechanism. Default value is ``0``.
- ``ENABLE_FEAT_MTE``: Numeric value to enable Memory Tagging Extension
if the platform wants to use this feature in the Secure world and MTE is
enabled at ELX. This flag can take values 0 to 2, to align with the
``FEATURE_DETECTION`` mechanism. Default value is ``0``.
- ``ENABLE_FEAT_MTE_PERM``: Numeric value to enable support for
``FEAT_MTE_PERM``, which introduces Allocation tag access permission to
memory region attributes. ``FEAT_MTE_PERM`` is a optional architectural
@ -1334,7 +1333,7 @@ Firmware update options
--------------
*Copyright (c) 2019-2023, Arm Limited. All rights reserved.*
*Copyright (c) 2019-2024, Arm Limited. All rights reserved.*
.. _DEN0115: https://developer.arm.com/docs/den0115/latest
.. _PSA FW update specification: https://developer.arm.com/documentation/den0118/a/

3
include/arch/aarch32/arch_features.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2019-2023, Arm Limited. All rights reserved.
* Copyright (c) 2019-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -147,6 +147,7 @@ static inline bool is_feat_tcr2_supported(void) { return false; }
static inline bool is_feat_spe_supported(void) { return false; }
static inline bool is_feat_rng_supported(void) { return false; }
static inline bool is_feat_gcs_supported(void) { return false; }
static inline bool is_feat_mte_supported(void) { return false; }
static inline bool is_feat_mpam_supported(void) { return false; }
static inline bool is_feat_hcx_supported(void) { return false; }
static inline bool is_feat_sve_supported(void) { return false; }

10
include/arch/aarch64/arch_features.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2019-2023, Arm Limited. All rights reserved.
* Copyright (c) 2019-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -89,12 +89,8 @@ static inline bool is_armv8_5_bti_present(void)
ID_AA64PFR1_EL1_BT_MASK) == BTI_IMPLEMENTED;
}
static inline unsigned int get_armv8_5_mte_support(void)
{
return ((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_MTE_SHIFT) &
ID_AA64PFR1_EL1_MTE_MASK);
}
CREATE_FEATURE_FUNCS(feat_mte, id_aa64pfr1_el1, ID_AA64PFR1_EL1_MTE_SHIFT,
ENABLE_FEAT_MTE)
CREATE_FEATURE_FUNCS(feat_sel2, id_aa64pfr0_el1, ID_AA64PFR0_SEL2_SHIFT,
ENABLE_FEAT_SEL2)
CREATE_FEATURE_FUNCS(feat_twed, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_TWED_SHIFT,

4
include/lib/el3_runtime/aarch64/context.h
View file

@ -140,7 +140,7 @@
#define CTX_TIMER_SYSREGS_END CTX_AARCH32_END
#endif /* NS_TIMER_SWITCH */
#if CTX_INCLUDE_MTE_REGS
#if ENABLE_FEAT_MTE
#define CTX_TFSRE0_EL1 (CTX_TIMER_SYSREGS_END + U(0x0))
#define CTX_TFSR_EL1 (CTX_TIMER_SYSREGS_END + U(0x8))
#define CTX_RGSR_EL1 (CTX_TIMER_SYSREGS_END + U(0x10))
@ -150,7 +150,7 @@
#define CTX_MTE_REGS_END (CTX_TIMER_SYSREGS_END + U(0x20))
#else
#define CTX_MTE_REGS_END CTX_TIMER_SYSREGS_END
#endif /* CTX_INCLUDE_MTE_REGS */
#endif /* ENABLE_FEAT_MTE */
/*
* End of system registers.

25
lib/el3_runtime/aarch64/context_mgmt.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2022, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@ -123,22 +123,10 @@ static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_in
scr_el3 |= get_scr_el3_from_routing_model(SECURE);
#endif
#if !CTX_INCLUDE_MTE_REGS || ENABLE_ASSERTIONS
/* Get Memory Tagging Extension support level */
unsigned int mte = get_armv8_5_mte_support();
#endif
/*
* Allow access to Allocation Tags when CTX_INCLUDE_MTE_REGS
* is set, or when MTE is only implemented at EL0.
*/
#if CTX_INCLUDE_MTE_REGS
assert((mte == MTE_IMPLEMENTED_ELX) || (mte == MTE_IMPLEMENTED_ASY));
scr_el3 |= SCR_ATA_BIT;
#else
if (mte == MTE_IMPLEMENTED_EL0) {
/* Allow access to Allocation Tags when mte is set*/
if (is_feat_mte_supported()) {
scr_el3 |= SCR_ATA_BIT;
}
#endif /* CTX_INCLUDE_MTE_REGS */
write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
@ -1267,9 +1255,10 @@ void cm_el2_sysregs_context_save(uint32_t security_state)
el2_sysregs_ctx = get_el2_sysregs_ctx(ctx);
el2_sysregs_context_save_common(el2_sysregs_ctx);
#if CTX_INCLUDE_MTE_REGS
write_ctx_reg(el2_sysregs_ctx, CTX_TFSR_EL2, read_tfsr_el2());
#endif
if (is_feat_mte_supported()) {
write_ctx_reg(el2_sysregs_ctx, CTX_TFSR_EL2, read_tfsr_el2());
}
#if CTX_INCLUDE_MPAM_REGS
if (is_feat_mpam_supported()) {

18
make_helpers/arch_features.mk
View file

@ -1,5 +1,5 @@
#
# Copyright (c) 2022-2023, Arm Limited. All rights reserved.
# Copyright (c) 2022-2024, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@ -239,10 +239,18 @@ CTX_INCLUDE_NEVE_REGS ?= 0
# registers, by setting SCR_EL3.TRNDR.
ENABLE_FEAT_RNG_TRAP ?= 0
# Include Memory Tagging Extension registers in cpu context. This must be set
# to 1 if the platform wants to use this feature in the Secure world and MTE is
# enabled at ELX.
CTX_INCLUDE_MTE_REGS ?= 0
# Enable Memory Tagging Extension. This must be set to 1 if the platform wants
# to use this feature in the Secure world and MTE is enabled at ELX.
ifeq ($(CTX_INCLUDE_MTE_REGS),1)
$(warning CTX_INCLUDE_MTE_REGS option is deprecated use ENABLE_FEAT_MTE, Enabling ENABLE_FEAT_MTE)
ENABLE_FEAT_MTE ?= 1
endif
ifeq (${ARCH},aarch32)
ifneq ($(or $(ENABLE_FEAT_MTE),0),0)
$(error ENABLE_FEAT_MTE is not supported for AArch32)
endif
endif
ENABLE_FEAT_MTE ?= 0
#----
# 8.6

4
services/std_svc/sdei/sdei_intr_mgmt.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -295,7 +295,7 @@ static void sdei_set_elr_spsr(sdei_entry_t *se, sdei_dispatch_context_t *disp_ct
}
/* If MTE is implemented in the client el set the TCO bit */
if (get_armv8_5_mte_support() >= MTE_IMPLEMENTED_ELX) {
if (is_feat_mte_supported()) {
sdei_spsr |= SPSR_TCO_BIT_AARCH64;
}