From 61b5ef21af8bcb38d3492e15d1d3d1fbecf3cf49 Mon Sep 17 00:00:00 2001 From: Ghennadi Procopciuc Date: Wed, 27 Nov 2024 12:33:26 +0200 Subject: [PATCH] feat(s32g274a): split early clock initialization Initializing all early clocks before the MMU is enabled can impact boot time. Therefore, splitting the setup into A53 clocks and peripheral clocks can be beneficial, with the peripheral clocks configured after fully initializing the MMU. Change-Id: I19644227b66effab8e2c43e64e057ea0c8625ebc Signed-off-by: Ghennadi Procopciuc --- drivers/nxp/clk/s32cc/s32cc_clk_drv.c | 8 ++++++-- drivers/nxp/clk/s32cc/s32cc_early_clks.c | 16 ++++++++++++++-- include/drivers/nxp/clk/s32cc/s32cc-clk-drv.h | 1 + include/drivers/nxp/clk/s32cc/s32cc-clk-utils.h | 3 ++- plat/nxp/s32/s32g274ardb2/plat_bl2_el3_setup.c | 5 +++++ 5 files changed, 28 insertions(+), 5 deletions(-) diff --git a/drivers/nxp/clk/s32cc/s32cc_clk_drv.c b/drivers/nxp/clk/s32cc/s32cc_clk_drv.c index ed331bf1c..235b9889a 100644 --- a/drivers/nxp/clk/s32cc/s32cc_clk_drv.c +++ b/drivers/nxp/clk/s32cc/s32cc_clk_drv.c @@ -1497,7 +1497,7 @@ static int s32cc_clk_mmap_regs(const struct s32cc_clk_drv *drv) return 0; } -int s32cc_clk_register_drv(void) +int s32cc_clk_register_drv(bool mmap_regs) { static const struct clk_ops s32cc_clk_ops = { .enable = s32cc_clk_enable, @@ -1517,6 +1517,10 @@ int s32cc_clk_register_drv(void) return -EINVAL; } - return s32cc_clk_mmap_regs(drv); + if (mmap_regs) { + return s32cc_clk_mmap_regs(drv); + } + + return 0; } diff --git a/drivers/nxp/clk/s32cc/s32cc_early_clks.c b/drivers/nxp/clk/s32cc/s32cc_early_clks.c index 06936a573..f001568f4 100644 --- a/drivers/nxp/clk/s32cc/s32cc_early_clks.c +++ b/drivers/nxp/clk/s32cc/s32cc_early_clks.c @@ -180,11 +180,11 @@ static int enable_ddr_clk(void) return ret; } -int s32cc_init_early_clks(void) +int s32cc_init_core_clocks(void) { int ret; - ret = s32cc_clk_register_drv(); + ret = s32cc_clk_register_drv(false); if (ret != 0) { return ret; } @@ -209,6 +209,18 @@ int s32cc_init_early_clks(void) return ret; } + return ret; +} + +int s32cc_init_early_clks(void) +{ + int ret; + + ret = s32cc_clk_register_drv(true); + if (ret != 0) { + return ret; + } + ret = setup_periph_pll(); if (ret != 0) { return ret; diff --git a/include/drivers/nxp/clk/s32cc/s32cc-clk-drv.h b/include/drivers/nxp/clk/s32cc/s32cc-clk-drv.h index d879f5bed..632b82fc1 100644 --- a/include/drivers/nxp/clk/s32cc/s32cc-clk-drv.h +++ b/include/drivers/nxp/clk/s32cc/s32cc-clk-drv.h @@ -6,6 +6,7 @@ #ifndef S32CC_CLK_DRV_H #define S32CC_CLK_DRV_H +int s32cc_init_core_clocks(void); int s32cc_init_early_clks(void); #endif diff --git a/include/drivers/nxp/clk/s32cc/s32cc-clk-utils.h b/include/drivers/nxp/clk/s32cc/s32cc-clk-utils.h index 1d08f736b..c6e90f056 100644 --- a/include/drivers/nxp/clk/s32cc/s32cc-clk-utils.h +++ b/include/drivers/nxp/clk/s32cc/s32cc-clk-utils.h @@ -5,6 +5,7 @@ #ifndef S32CC_CLK_UTILS_H #define S32CC_CLK_UTILS_H +#include #include struct s32cc_clk *s32cc_get_clk_from_table(const struct s32cc_clk_array *const *clk_arr, @@ -18,6 +19,6 @@ int s32cc_get_id_from_table(const struct s32cc_clk_array *const *clk_arr, struct s32cc_clk *s32cc_get_arch_clk(unsigned long id); int s32cc_get_clk_id(const struct s32cc_clk *clk, unsigned long *id); -int s32cc_clk_register_drv(void); +int s32cc_clk_register_drv(bool mmap_regs); #endif /* S32CC_CLK_UTILS_H */ diff --git a/plat/nxp/s32/s32g274ardb2/plat_bl2_el3_setup.c b/plat/nxp/s32/s32g274ardb2/plat_bl2_el3_setup.c index 2254bf5ad..0929f9d84 100644 --- a/plat/nxp/s32/s32g274ardb2/plat_bl2_el3_setup.c +++ b/plat/nxp/s32/s32g274ardb2/plat_bl2_el3_setup.c @@ -83,6 +83,11 @@ void bl2_el3_early_platform_setup(u_register_t arg0, u_register_t arg1, ncore_init(); ncore_caiu_online(A53_CLUSTER0_CAIU); + ret = s32cc_init_core_clocks(); + if (ret != 0) { + panic(); + } + ret = s32cc_bl_mmu_setup(); if (ret != 0) { panic();