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ble: ap807: improve PLL configuration sequence

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Update PLL configuration according to HW team guidelines.

Change-Id: I23cac4fb4a638e7416965a5399ce6947e08d0711
Signed-off-by: Alex Leibovich <alexl@marvell.com>
This commit is contained in:
Alex Leibovich 2019-02-25 13:13:48 +02:00 • committed by Marcin Wojtas
parent 85d2ed1501
commit 615d859b2e
1 changed files with 15 additions and 0 deletions
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15
drivers/marvell/ap807_clocks_init.c
View file

@ -39,14 +39,29 @@
#define AP807_CPU_PLL_PARAM(cluster) AP807_CPU_PLL_CTRL(cluster)
#define AP807_CPU_PLL_CFG(cluster) (AP807_CPU_PLL_CTRL(cluster) + 0x4)
#define AP807_CPU_PLL_CFG_BYPASS_MODE (0x1)
#define AP807_CPU_PLL_FRC_DSCHG (0x2)
#define AP807_CPU_PLL_CFG_USE_REG_FILE (0x1 << 9)
static void pll_set_freq(unsigned int freq_val)
{
int i;
if (freq_val != PLL_FREQ_2200)
return;
for (i = 0 ; i < AP807_CLUSTER_NUM ; i++) {
/* Set parameter of cluster i PLL to 2.2GHz */
mmio_write_32(AP807_CPU_PLL_PARAM(i), freq_val);
/* Set apll_lpf_frc_dschg - Control
* voltage of internal VCO is discharged
*/
mmio_write_32(AP807_CPU_PLL_CFG(i),
AP807_CPU_PLL_FRC_DSCHG);
/* Set use_rf_conf load PLL parameter from register */
mmio_write_32(AP807_CPU_PLL_CFG(i),
AP807_CPU_PLL_FRC_DSCHG |
AP807_CPU_PLL_CFG_USE_REG_FILE);
/* Un-set apll_lpf_frc_dschg */
mmio_write_32(AP807_CPU_PLL_CFG(i),
AP807_CPU_PLL_CFG_USE_REG_FILE);
}