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fix(fvp_ve): fdts: Fix vexpress,config-bus subnode names

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The arm,vexpress,config-bus DT binding restricts the possible (sub)node
names.
Adjust the current node names, to drop the unneeded address specifier,
and make the node names binding compliant.

Change-Id: Ic48c6969268c960ce92c8ec3a756ed1d89e61b08
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
This commit is contained in:
Andre Przywara 2022-08-23 10:45:54 +01:00
parent 0e3d88070f
commit 60da130a8c
1 changed files with 6 additions and 6 deletions
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12
fdts/fvp-ve-Cortex-A5x1.dts
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@ -77,7 +77,7 @@
};
mcc {
oscclk0: osc@0 {
oscclk0: oscclk0 {
/* CPU and internal AXI reference clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 0>;
@ -86,7 +86,7 @@
clock-output-names = "oscclk0";
};
oscclk1: osc@1 {
oscclk1: oscclk1 {
/* Multiplexed AXI master clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 1>;
@ -95,7 +95,7 @@
clock-output-names = "oscclk1";
};
osc@2 {
oscclk2 {
/* DDR2 */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 2>;
@ -104,7 +104,7 @@
clock-output-names = "oscclk2";
};
oscclk3: osc@3 {
oscclk3: oscclk3 {
/* HDLCD */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 3>;
@ -113,7 +113,7 @@
clock-output-names = "oscclk3";
};
osc@4 {
oscclk4 {
/* Test chip gate configuration */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 4>;
@ -122,7 +122,7 @@
clock-output-names = "oscclk4";
};
smbclk: osc@5 {
smbclk: oscclk5 {
/* SMB clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 5>;