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feat(rcar3): change MMU configurations

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Always enable MMU and control access protection.

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: I4ac997cda2985746b2bf97ab9e4e5ace600f43ca
This commit is contained in:
Toshiyuki Ogasahara 2021-07-12 18:33:42 +09:00 • committed by Marek Vasut
parent cfa466ab73
commit 5e8c2d8e23
3 changed files with 21 additions and 23 deletions
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7
plat/renesas/common/aarch64/plat_helpers.S
View file

@ -1,6 +1,6 @@
/* /*
* Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved. * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved. * Copyright (c) 2015-2023, Renesas Electronics Corporation. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -172,15 +172,16 @@ func bl2_enter_bl31
* BL31 will initialize the address space according to its * BL31 will initialize the address space according to its
* own requirement. * own requirement.
*/ */
#if RCAR_BL2_DCACHE == 1
/* Disable mmu and data cache */ /* Disable mmu and data cache */
bl disable_mmu_el3 bl disable_mmu_el3
#if RCAR_BL2_DCACHE == 1
/* Data cache clean and invalidate */ /* Data cache clean and invalidate */
mov x0, #DCCISW mov x0, #DCCISW
bl dcsw_op_all bl dcsw_op_all
#endif /* RCAR_BL2_DCACHE == 1 */
/* TLB invalidate all, EL3 */ /* TLB invalidate all, EL3 */
tlbi alle3 tlbi alle3
#endif /* RCAR_BL2_DCACHE == 1 */
bl disable_mmu_icache_el3 bl disable_mmu_icache_el3
/* Invalidate instruction cache */ /* Invalidate instruction cache */
ic iallu ic iallu

26
plat/renesas/common/aarch64/platform_common.c
View file

@ -1,6 +1,6 @@
/* /*
* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved. * Copyright (c) 2015-2023, Renesas Electronics Corporation. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -30,13 +30,19 @@ extern int32_t rcar_get_certificate(const int32_t name, uint32_t *cert);
const uint8_t version_of_renesas[VERSION_OF_RENESAS_MAXLEN] const uint8_t version_of_renesas[VERSION_OF_RENESAS_MAXLEN]
__attribute__ ((__section__(".ro"))) = VERSION_OF_RENESAS; __attribute__ ((__section__(".ro"))) = VERSION_OF_RENESAS;
#if (IMAGE_BL2) && (RCAR_BL2_DCACHE != 1)
#define RCAR_DCACHE MT_NON_CACHEABLE
#else
#define RCAR_DCACHE MT_MEMORY
#endif
#define MAP_SHARED_RAM MAP_REGION_FLAT(RCAR_SHARED_MEM_BASE, \ #define MAP_SHARED_RAM MAP_REGION_FLAT(RCAR_SHARED_MEM_BASE, \
RCAR_SHARED_MEM_SIZE, \ RCAR_SHARED_MEM_SIZE, \
MT_MEMORY | MT_RW | MT_SECURE) MT_MEMORY | MT_RW | MT_SECURE)
#define MAP_FLASH0 MAP_REGION_FLAT(FLASH0_BASE, \ #define MAP_FLASH0 MAP_REGION_FLAT(FLASH0_BASE, \
FLASH0_SIZE, \ FLASH0_SIZE, \
MT_MEMORY | MT_RO | MT_SECURE) RCAR_DCACHE | MT_RO | MT_SECURE)
#define MAP_DRAM1_NS MAP_REGION_FLAT(DRAM1_NS_BASE, \ #define MAP_DRAM1_NS MAP_REGION_FLAT(DRAM1_NS_BASE, \
DRAM1_NS_SIZE, \ DRAM1_NS_SIZE, \
@ -68,7 +74,7 @@ const uint8_t version_of_renesas[VERSION_OF_RENESAS_MAXLEN]
#if IMAGE_BL2 #if IMAGE_BL2
#define MAP_DRAM0 MAP_REGION_FLAT(DRAM1_BASE, \ #define MAP_DRAM0 MAP_REGION_FLAT(DRAM1_BASE, \
DRAM1_SIZE, \ DRAM1_SIZE, \
MT_MEMORY | MT_RW | MT_SECURE) RCAR_DCACHE | MT_RW | MT_SECURE)
#define MAP_REG0 MAP_REGION_FLAT(DEVICE_RCAR_BASE, \ #define MAP_REG0 MAP_REGION_FLAT(DEVICE_RCAR_BASE, \
DEVICE_RCAR_SIZE, \ DEVICE_RCAR_SIZE, \
@ -76,7 +82,7 @@ const uint8_t version_of_renesas[VERSION_OF_RENESAS_MAXLEN]
#define MAP_RAM0 MAP_REGION_FLAT(RCAR_SYSRAM_BASE, \ #define MAP_RAM0 MAP_REGION_FLAT(RCAR_SYSRAM_BASE, \
RCAR_SYSRAM_SIZE, \ RCAR_SYSRAM_SIZE, \
MT_MEMORY | MT_RW | MT_SECURE) RCAR_DCACHE | MT_RW | MT_SECURE)
#define MAP_REG1 MAP_REGION_FLAT(REG1_BASE, \ #define MAP_REG1 MAP_REGION_FLAT(REG1_BASE, \
REG1_SIZE, \ REG1_SIZE, \
@ -84,7 +90,7 @@ const uint8_t version_of_renesas[VERSION_OF_RENESAS_MAXLEN]
#define MAP_ROM MAP_REGION_FLAT(ROM0_BASE, \ #define MAP_ROM MAP_REGION_FLAT(ROM0_BASE, \
ROM0_SIZE, \ ROM0_SIZE, \
MT_MEMORY | MT_RO | MT_SECURE) RCAR_DCACHE | MT_RO | MT_SECURE)
#define MAP_REG2 MAP_REGION_FLAT(REG2_BASE, \ #define MAP_REG2 MAP_REGION_FLAT(REG2_BASE, \
REG2_SIZE, \ REG2_SIZE, \
@ -92,7 +98,7 @@ const uint8_t version_of_renesas[VERSION_OF_RENESAS_MAXLEN]
#define MAP_DRAM1 MAP_REGION_FLAT(DRAM_40BIT_BASE, \ #define MAP_DRAM1 MAP_REGION_FLAT(DRAM_40BIT_BASE, \
DRAM_40BIT_SIZE, \ DRAM_40BIT_SIZE, \
MT_MEMORY | MT_RW | MT_SECURE) RCAR_DCACHE | MT_RW | MT_SECURE)
#endif #endif
#ifdef BL32_BASE #ifdef BL32_BASE
@ -152,9 +158,9 @@ void rcar_configure_mmu_el3(unsigned long total_base,
unsigned long coh_limit) unsigned long coh_limit)
{ {
mmap_add_region(total_base, total_base, total_size, mmap_add_region(total_base, total_base, total_size,
MT_MEMORY | MT_RW | MT_SECURE); RCAR_DCACHE | MT_RW | MT_SECURE);
mmap_add_region(ro_start, ro_start, ro_limit - ro_start, mmap_add_region(ro_start, ro_start, ro_limit - ro_start,
MT_MEMORY | MT_RO | MT_SECURE); RCAR_DCACHE | MT_RO | MT_SECURE);
mmap_add_region(coh_start, coh_start, coh_limit - coh_start, mmap_add_region(coh_start, coh_start, coh_limit - coh_start,
MT_DEVICE | MT_RW | MT_SECURE); MT_DEVICE | MT_RW | MT_SECURE);
mmap_add(rcar_mmap); mmap_add(rcar_mmap);
@ -169,9 +175,9 @@ void rcar_configure_mmu_el3(unsigned long total_base,
unsigned long ro_limit) unsigned long ro_limit)
{ {
mmap_add_region(total_base, total_base, total_size, mmap_add_region(total_base, total_base, total_size,
MT_MEMORY | MT_RW | MT_SECURE); RCAR_DCACHE | MT_RW | MT_SECURE);
mmap_add_region(ro_start, ro_start, ro_limit - ro_start, mmap_add_region(ro_start, ro_start, ro_limit - ro_start,
MT_MEMORY | MT_RO | MT_SECURE); RCAR_DCACHE | MT_RO | MT_SECURE);
mmap_add(rcar_mmap); mmap_add(rcar_mmap);
init_xlat_tables(); init_xlat_tables();

11
plat/renesas/rcar/bl2_plat_setup.c
View file

@ -48,10 +48,8 @@
#include "rcar_version.h" #include "rcar_version.h"
#include "rom_api.h" #include "rom_api.h"
#if RCAR_BL2_DCACHE == 1
/* /*
* Following symbols are only used during plat_arch_setup() only * Following symbols are only used during plat_arch_setup()
* when RCAR_BL2_DCACHE is enabled.
*/ */
static const uint64_t BL2_RO_BASE = BL_CODE_BASE; static const uint64_t BL2_RO_BASE = BL_CODE_BASE;
static const uint64_t BL2_RO_LIMIT = BL_CODE_END; static const uint64_t BL2_RO_LIMIT = BL_CODE_END;
@ -61,8 +59,6 @@ static const uint64_t BL2_COHERENT_RAM_BASE = BL_COHERENT_RAM_BASE;
static const uint64_t BL2_COHERENT_RAM_LIMIT = BL_COHERENT_RAM_END; static const uint64_t BL2_COHERENT_RAM_LIMIT = BL_COHERENT_RAM_END;
#endif #endif
#endif
extern void plat_rcar_gic_driver_init(void); extern void plat_rcar_gic_driver_init(void);
extern void plat_rcar_gic_init(void); extern void plat_rcar_gic_init(void);
extern void bl2_enter_bl31(const struct entry_point_info *bl_ep_info); extern void bl2_enter_bl31(const struct entry_point_info *bl_ep_info);
@ -372,10 +368,8 @@ mmu:
rcar_swdt_release(); rcar_swdt_release();
bl2_system_cpg_init(); bl2_system_cpg_init();
#if RCAR_BL2_DCACHE == 1
/* Disable data cache (clean and invalidate) */ /* Disable data cache (clean and invalidate) */
disable_mmu_el3(); disable_mmu_el3();
#endif
} }
static uint32_t is_ddr_backup_mode(void) static uint32_t is_ddr_backup_mode(void)
@ -1274,8 +1268,6 @@ lcm_state:
void bl2_el3_plat_arch_setup(void) void bl2_el3_plat_arch_setup(void)
{ {
#if RCAR_BL2_DCACHE == 1
NOTICE("BL2: D-Cache enable\n");
rcar_configure_mmu_el3(BL2_BASE, rcar_configure_mmu_el3(BL2_BASE,
BL2_END - BL2_BASE, BL2_END - BL2_BASE,
BL2_RO_BASE, BL2_RO_LIMIT BL2_RO_BASE, BL2_RO_LIMIT
@ -1283,7 +1275,6 @@ void bl2_el3_plat_arch_setup(void)
, BL2_COHERENT_RAM_BASE, BL2_COHERENT_RAM_LIMIT , BL2_COHERENT_RAM_BASE, BL2_COHERENT_RAM_LIMIT
#endif #endif
); );
#endif
} }
void bl2_el3_plat_prepare_exit(void) void bl2_el3_plat_prepare_exit(void)