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plat: marvell: ap807: implement workaround for errata-id 3033912
ERRATA ID: RES-3033912 - Internal Address Space Init state causes a hang upon accesses to [0xf070_0000, 0xf07f_ffff] Workaround: Boot Firmware (ATF) should configure CCU_RGF_WIN(4) to split [0x6e_0000, 0xff_ffff] to values [0x6e_0000, 0x6f_ffff] and [0x80_0000, 0xff_ffff] that cause accesses to the segment of [0xf070_0000, 0xf07f_ffff] to act as RAZWI. Reuse common work-around code for both AP806 and AP807. Change-Id: Ia91a4802d02917d1682faa0c81571093d1687d97 Signed-off-by: Stefan Chulski <stefanc@marvell.com>
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4 changed files with 21 additions and 18 deletions
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@ -30,6 +30,9 @@
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((tgt) == DRAM_1_TID) || \
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((tgt) == RAR_TID)) ? 1 : 0)
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#define CCU_RGF(win) (MVEBU_CCU_BASE(MVEBU_AP0) + \
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0x90 + 4 * (win))
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/* For storage of CR, SCR, ALR, AHR abd GCR */
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static uint32_t ccu_regs_save[MVEBU_CCU_MAX_WINS * 4 + 1];
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@ -366,3 +369,17 @@ int init_ccu(int ap_index)
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return 0;
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}
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void errata_wa_init(void)
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{
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/*
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* EERATA ID: RES-3033912 - Internal Address Space Init state causes
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* a hang upon accesses to [0xf070_0000, 0xf07f_ffff]
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* Workaround: Boot Firmware (ATF) should configure CCU_RGF_WIN(4) to
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* split [0x6e_0000, 0xff_ffff] to values [0x6e_0000, 0x6f_ffff] and
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* [0x80_0000, 0xff_ffff] that cause accesses to the
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* segment of [0xf070_0000, 0xf07f_ffff] to act as RAZWI.
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*/
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mmio_write_32(CCU_RGF(4), 0x37f9b809);
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mmio_write_32(CCU_RGF(5), 0x7ffa0009);
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}
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@ -117,6 +117,8 @@ static void init_aurora2(void)
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reg |= (0x1 << CCU_SET_POC_OFFSET);
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mmio_write_32(CCU_HTC_CR, reg);
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#endif /* LLC_ENABLE */
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errata_wa_init();
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}
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@ -28,9 +28,6 @@
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0x200)
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#define CCU_SET_POC_OFFSET 5
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#define CCU_RGF(win) (MVEBU_CCU_BASE(MVEBU_AP0) + \
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0x90 + 4 * (win))
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#define DSS_CR0 (MVEBU_RFU_BASE + 0x100)
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#define DVM_48BIT_VA_ENABLE (1 << 21)
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@ -95,20 +92,6 @@ static void setup_smmu(void)
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mmio_write_32(SMMU_sACR, reg);
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}
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static void apn806_errata_wa_init(void)
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{
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/*
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* ERRATA ID: RES-3033912 - Internal Address Space Init state causes
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* a hang upon accesses to [0xf070_0000, 0xf07f_ffff]
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* Workaround: Boot Firmware (ATF) should configure CCU_RGF_WIN(4) to
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* split [0x6e_0000, 0xff_ffff] to values [0x6e_0000, 0x6f_ffff] and
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* [0x80_0000, 0xff_ffff] that cause accesses to the
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* segment of [0xf070_0000, 0xf07f_ffff] to act as RAZWI.
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*/
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mmio_write_32(CCU_RGF(4), 0x37f9b809);
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mmio_write_32(CCU_RGF(5), 0x7ffa0009);
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}
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static void init_aurora2(void)
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{
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uint32_t reg;
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@ -131,7 +114,7 @@ static void init_aurora2(void)
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mmio_write_32(CCU_HTC_CR, reg);
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#endif /* LLC_ENABLE */
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apn806_errata_wa_init();
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errata_wa_init();
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}
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@ -47,6 +47,7 @@ void ccu_dram_target_set(int ap_index, uint32_t target);
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void ccu_save_win_all(int ap_id);
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void ccu_restore_win_all(int ap_id);
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int ccu_is_win_enabled(int ap_index, uint32_t win_id);
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void errata_wa_init(void);
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#endif
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#endif /* CCU_H */
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