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Merge changes I713f6e93,Iac4fbf4d,I43d02c77,Iadecd544,Ib31f9c4a, ... into integration

Browse source 
* changes:
  build(intel): enable access to on-chip ram in BL31 for N5X
  fix(intel): make FPGA memory configurations platform specific
  fix(intel): fix ECC Double Bit Error handling
  build(intel): define a macro for SIMICS build
  build(intel): add N5X as a new Intel platform
  build(intel): initial commit for crypto driver
This commit is contained in:
Madhukar Pappireddy 2022-03-09 15:17:24 +01:00 • committed by TrustedFirmware Code Review
commit 5e29432ebe
21 changed files with 560 additions and 27 deletions
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5
Makefile
View file

@ -945,6 +945,9 @@ PRINT_MEMORY_MAP ?= ${PRINT_MEMORY_MAP_PATH}/print_memory_map.py
# Variables for use with documentation build using Sphinx tool
DOCS_PATH ?= docs
# Defination of SIMICS flag
SIMICS_BUILD ?= 0
################################################################################
# Include BL specific makefiles
################################################################################
@ -1055,6 +1058,7 @@ $(eval $(call assert_booleans,\
ENABLE_FEAT_FGT \
ENABLE_FEAT_AMUv1 \
ENABLE_FEAT_ECV \
SIMICS_BUILD \
)))
$(eval $(call assert_numerics,\
@ -1172,6 +1176,7 @@ $(eval $(call add_defines,\
ENABLE_FEAT_FGT \
ENABLE_FEAT_AMUv1 \
ENABLE_FEAT_ECV \
SIMICS_BUILD \
)))
ifeq (${SANITIZE_UB},trap)

8
plat/intel/soc/agilex/include/socfpga_plat_def.h
View file

@ -1,6 +1,6 @@
/*
* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2019, Intel Corporation. All rights reserved.
* Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -14,6 +14,10 @@
#define PLATFORM_MODEL PLAT_SOCFPGA_AGILEX
#define BOOT_SOURCE BOOT_SOURCE_SDMMC
/* FPGA config helpers */
#define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x400000
#define INTEL_SIP_SMC_FPGA_CONFIG_SIZE 0x2000000
/* Register Mapping */
#define SOCFPGA_MMC_REG_BASE 0xff808000

7
plat/intel/soc/agilex/platform.mk
View file

@ -1,6 +1,6 @@
#
# Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved.
# Copyright (c) 2019-2020, Intel Corporation. All rights reserved.
# Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved.
# Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@ -65,6 +65,8 @@ BL31_SOURCES += \
plat/intel/soc/common/socfpga_psci.c \
plat/intel/soc/common/socfpga_sip_svc.c \
plat/intel/soc/common/socfpga_topology.c \
plat/intel/soc/common/sip/socfpga_sip_ecc.c \
plat/intel/soc/common/sip/socfpga_sip_fcs.c \
plat/intel/soc/common/soc/socfpga_mailbox.c \
plat/intel/soc/common/soc/socfpga_reset_manager.c
@ -72,4 +74,5 @@ PROGRAMMABLE_RESET_ADDRESS := 0
BL2_AT_EL3 := 1
BL2_INV_DCACHE := 0
MULTI_CONSOLE_API := 1
SIMICS_BUILD := 0
USE_COHERENT_MEM := 1

13
plat/intel/soc/common/drivers/ccu/ncore_ccu.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, Intel Corporation. All rights reserved.
* Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -107,6 +107,17 @@ void bypass_ocram_firewall(void)
OCRAM_PRIVILEGED_MASK | OCRAM_SECURE_MASK);
}
void ncore_enable_ocram_firewall(void)
{
mmio_setbits_32(COH_CPU0_BYPASS_REG(NCORE_FW_OCRAM_BLK_CGF1),
OCRAM_PRIVILEGED_MASK | OCRAM_SECURE_MASK);
mmio_setbits_32(COH_CPU0_BYPASS_REG(NCORE_FW_OCRAM_BLK_CGF2),
OCRAM_PRIVILEGED_MASK | OCRAM_SECURE_MASK);
mmio_setbits_32(COH_CPU0_BYPASS_REG(NCORE_FW_OCRAM_BLK_CGF3),
OCRAM_PRIVILEGED_MASK | OCRAM_SECURE_MASK);
mmio_setbits_32(COH_CPU0_BYPASS_REG(NCORE_FW_OCRAM_BLK_CGF4),
OCRAM_PRIVILEGED_MASK | OCRAM_SECURE_MASK);
}
uint32_t init_ncore_ccu(void)
{
uint32_t status;

3
plat/intel/soc/common/drivers/ccu/ncore_ccu.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, Intel Corporation. All rights reserved.
* Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -104,5 +104,6 @@ typedef struct coh_ss_id {
} coh_ss_id_t;
uint32_t init_ncore_ccu(void);
void ncore_enable_ocram_firewall(void);
#endif

13
plat/intel/soc/common/include/platform_def.h
View file

@ -1,6 +1,6 @@
/*
* Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2019-2020, Intel Corporation. All rights reserved.
* Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -13,8 +13,10 @@
#include <common/tbbr/tbbr_img_def.h>
#include <plat/common/common_def.h>
/* Platform Type */
#define PLAT_SOCFPGA_STRATIX10 1
#define PLAT_SOCFPGA_AGILEX 2
#define PLAT_SOCFPGA_N5X 3
/* sysmgr.boot_scratch_cold4 & 5 used for CPU release address for SPL */
#define PLAT_CPU_RELEASE_ADDR 0xffd12210
@ -167,9 +169,16 @@
#define CRASH_CONSOLE_BASE PLAT_UART0_BASE
#ifndef SIMICS_BUILD
#define PLAT_BAUDRATE (115200)
#define PLAT_UART_CLOCK (100000000)
#else
#define PLAT_BAUDRATE (4800)
#define PLAT_UART_CLOCK (76800)
#endif
/*******************************************************************************
* PHY related constants
******************************************************************************/

41
plat/intel/soc/common/include/socfpga_fcs.h Normal file
View file

@ -0,0 +1,41 @@
/*
* Copyright (c) 2020-2022, Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef SOCFPGA_FCS_H
#define SOCFPGA_FCS_H
/* FCS Definitions */
#define FCS_RANDOM_WORD_SIZE 8U
#define FCS_PROV_DATA_WORD_SIZE 44U
#define FCS_RANDOM_BYTE_SIZE (FCS_RANDOM_WORD_SIZE * 4U)
#define FCS_PROV_DATA_BYTE_SIZE (FCS_PROV_DATA_WORD_SIZE * 4U)
#define FCS_CRYPTION_DATA_0 0x10100
/* FCS Payload Structure */
typedef struct fcs_crypt_payload_t {
uint32_t first_word;
uint32_t src_addr;
uint32_t src_size;
uint32_t dst_addr;
uint32_t dst_size;
} fcs_crypt_payload;
/* Functions Definitions */
uint32_t intel_fcs_random_number_gen(uint64_t addr, uint64_t *ret_size,
uint32_t *mbox_error);
uint32_t intel_fcs_send_cert(uint64_t addr, uint64_t size,
uint32_t *send_id);
uint32_t intel_fcs_get_provision_data(uint32_t *send_id);
uint32_t intel_fcs_cryption(uint32_t mode, uint32_t src_addr,
uint32_t src_size, uint32_t dst_addr,
uint32_t dst_size, uint32_t *send_id);
#endif /* SOCFPGA_FCS_H */

6
plat/intel/soc/common/include/socfpga_mailbox.h
View file

@ -40,6 +40,7 @@
#define MBOX_CMD_SYNC 0x01
#define MBOX_CMD_RESTART 0x02
#define MBOX_CMD_CANCEL 0x03
#define MBOX_CMD_VAB_SRC_CERT 0x0B
#define MBOX_CMD_GET_IDCODE 0x10
#define MBOX_CMD_REBOOT_HPS 0x47
@ -61,6 +62,11 @@
#define MBOX_RSU_UPDATE 0x5C
#define MBOX_HPS_STAGE_NOTIFY 0x5D
/* FCS Command */
#define MBOX_FCS_GET_PROVISION 0x7B
#define MBOX_FCS_ENCRYPT_REQ 0x7E
#define MBOX_FCS_DECRYPT_REQ 0x7F
#define MBOX_FCS_RANDOM_GEN 0x80
/* Mailbox Definitions */

2
plat/intel/soc/common/include/socfpga_reset_manager.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, Intel Corporation. All rights reserved.
* Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/

22
plat/intel/soc/common/include/socfpga_sip_svc.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2019-2020, Intel Corporation. All rights reserved.
* Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -15,6 +15,8 @@
#define INTEL_SIP_SMC_STATUS_ERROR 0x4
#define INTEL_SIP_SMC_RSU_ERROR 0x7
/* SiP mailbox error code */
#define GENERIC_RESPONSE_ERROR 0x3FF
/* SMC SiP service function identifier */
@ -35,6 +37,12 @@
#define INTEL_SIP_SMC_RSU_UPDATE 0xC200000C
#define INTEL_SIP_SMC_RSU_NOTIFY 0xC200000E
#define INTEL_SIP_SMC_RSU_RETRY_COUNTER 0xC200000F
#define INTEL_SIP_SMC_RSU_DCMF_VERSION 0xC2000010
#define INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION 0xC2000011
/* ECC */
#define INTEL_SIP_SMC_ECC_DBE 0xC200000D
/* Send Mailbox Command */
#define INTEL_SIP_SMC_MBOX_SEND_CMD 0xC200001E
@ -42,9 +50,11 @@
/* SiP Definitions */
/* FPGA config helpers */
#define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x400000
#define INTEL_SIP_SMC_FPGA_CONFIG_SIZE 0x2000000
/* ECC DBE */
#define WARM_RESET_WFI_FLAG BIT(31)
#define SYSMGR_ECC_DBE_COLD_RST_MASK (SYSMGR_ECC_OCRAM_MASK |\
SYSMGR_ECC_DDR0_MASK |\
SYSMGR_ECC_DDR1_MASK)
/* SMC function IDs for SiP Service queries */
#define SIP_SVC_CALL_COUNT 0x8200ff00
@ -70,4 +80,8 @@ struct fpga_config_info {
bool is_address_in_ddr_range(uint64_t addr, uint64_t size);
/* ECC DBE */
bool cold_reset_for_ecc_dbe(void);
uint32_t intel_ecc_dbe_notification(uint64_t dbe_value);
#endif /* SOCFPGA_SIP_SVC_H */

8
plat/intel/soc/common/include/socfpga_system_manager.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2019-2020, Intel Corporation. All rights reserved.
* Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -30,6 +30,8 @@
#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_0 0x200
#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_1 0x204
#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_2 0x208
#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_8 0x220
#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_9 0x224
/* Field Masking */
@ -47,6 +49,10 @@
| SCR_MPU_MASK)
#define DISABLE_BRIDGE_FIREWALL 0x0ffe0101
#define SYSMGR_ECC_OCRAM_MASK BIT(1)
#define SYSMGR_ECC_DDR0_MASK BIT(16)
#define SYSMGR_ECC_DDR1_MASK BIT(17)
/* Macros */
#define SOCFPGA_SYSMGR(_reg) (SOCFPGA_SYSMGR_REG_BASE \

46
plat/intel/soc/common/sip/socfpga_sip_ecc.c Normal file
View file

@ -0,0 +1,46 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2020-2022, ARM Limited and Contributors. All rights reserved.
*/
#include <assert.h>
#include <common/debug.h>
#include <common/runtime_svc.h>
#include <lib/mmio.h>
#include <tools_share/uuid.h>
#include "socfpga_fcs.h"
#include "socfpga_mailbox.h"
#include "socfpga_reset_manager.h"
#include "socfpga_sip_svc.h"
#include "socfpga_system_manager.h"
uint32_t intel_ecc_dbe_notification(uint64_t dbe_value)
{
dbe_value &= WARM_RESET_WFI_FLAG;
/* Trap CPUs in WFI if warm reset flag is set */
if (dbe_value > 0) {
while (1) {
wfi();
}
}
return INTEL_SIP_SMC_STATUS_OK;
}
bool cold_reset_for_ecc_dbe(void)
{
uint32_t dbe_int_status;
dbe_int_status = mmio_read_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_8));
/* Trigger cold reset only for error in critical memory (DDR/OCRAM) */
dbe_int_status &= SYSMGR_ECC_DBE_COLD_RST_MASK;
if (dbe_int_status > 0) {
return true;
}
return false;
}

120
plat/intel/soc/common/sip/socfpga_sip_fcs.c Normal file
View file

@ -0,0 +1,120 @@
/*
* Copyright (c) 2020-2022, Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch_helpers.h>
#include <lib/mmio.h>
#include "socfpga_fcs.h"
#include "socfpga_mailbox.h"
#include "socfpga_sip_svc.h"
uint32_t intel_fcs_random_number_gen(uint64_t addr, uint64_t *ret_size,
uint32_t *mbox_error)
{
int status;
unsigned int i;
unsigned int resp_len = FCS_RANDOM_WORD_SIZE;
uint32_t random_data[FCS_RANDOM_WORD_SIZE] = {0U};
if (!is_address_in_ddr_range(addr, FCS_RANDOM_BYTE_SIZE)) {
return INTEL_SIP_SMC_STATUS_REJECTED;
}
status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_FCS_RANDOM_GEN, NULL, 0U,
CMD_CASUAL, random_data, &resp_len);
if (status < 0) {
*mbox_error = -status;
return INTEL_SIP_SMC_STATUS_ERROR;
}
if (resp_len != FCS_RANDOM_WORD_SIZE) {
*mbox_error = GENERIC_RESPONSE_ERROR;
return INTEL_SIP_SMC_STATUS_ERROR;
}
*ret_size = FCS_RANDOM_BYTE_SIZE;
for (i = 0U; i < FCS_RANDOM_WORD_SIZE; i++) {
mmio_write_32(addr, random_data[i]);
addr += MBOX_WORD_BYTE;
}
flush_dcache_range(addr - *ret_size, *ret_size);
return INTEL_SIP_SMC_STATUS_OK;
}
uint32_t intel_fcs_send_cert(uint64_t addr, uint64_t size,
uint32_t *send_id)
{
int status;
if (!is_address_in_ddr_range(addr, size)) {
return INTEL_SIP_SMC_STATUS_REJECTED;
}
status = mailbox_send_cmd_async(send_id, MBOX_CMD_VAB_SRC_CERT,
(uint32_t *)addr, size / MBOX_WORD_BYTE,
CMD_DIRECT);
if (status < 0) {
return INTEL_SIP_SMC_STATUS_ERROR;
}
return INTEL_SIP_SMC_STATUS_OK;
}
uint32_t intel_fcs_get_provision_data(uint32_t *send_id)
{
int status;
status = mailbox_send_cmd_async(send_id, MBOX_FCS_GET_PROVISION,
NULL, 0U, CMD_DIRECT);
if (status < 0) {
return INTEL_SIP_SMC_STATUS_ERROR;
}
return INTEL_SIP_SMC_STATUS_OK;
}
uint32_t intel_fcs_cryption(uint32_t mode, uint32_t src_addr,
uint32_t src_size, uint32_t dst_addr,
uint32_t dst_size, uint32_t *send_id)
{
int status;
uint32_t cmd;
if (!is_address_in_ddr_range(src_addr, src_size) ||
!is_address_in_ddr_range(dst_addr, dst_size)) {
return INTEL_SIP_SMC_STATUS_REJECTED;
}
fcs_crypt_payload payload = {
FCS_CRYPTION_DATA_0,
src_addr,
src_size,
dst_addr,
dst_size };
if (mode != 0U) {
cmd = MBOX_FCS_ENCRYPT_REQ;
} else {
cmd = MBOX_FCS_DECRYPT_REQ;
}
status = mailbox_send_cmd_async(send_id, cmd, (uint32_t *) &payload,
sizeof(fcs_crypt_payload) / MBOX_WORD_BYTE,
CMD_INDIRECT);
inv_dcache_range(dst_addr, dst_size);
if (status < 0) {
return INTEL_SIP_SMC_STATUS_REJECTED;
}
return INTEL_SIP_SMC_STATUS_OK;
}

4
plat/intel/soc/common/soc/socfpga_reset_manager.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, Intel Corporation. All rights reserved.
* Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -134,7 +134,7 @@ int socfpga_bridges_disable(void)
#if PLATFORM_MODEL == PLAT_SOCFPGA_STRATIX10
mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST),
~(RSTMGR_FIELD(BRG, DDRSCH) | RSTMGR_FIELD(BRG, FPGA2SOC)));
#elif PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX
#else
mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST),
~(RSTMGR_FIELD(BRG, MPFE) | RSTMGR_FIELD(BRG, FPGA2SOC)));
#endif

7
plat/intel/soc/common/socfpga_psci.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -14,7 +14,7 @@
#include "socfpga_mailbox.h"
#include "socfpga_plat_def.h"
#include "socfpga_reset_manager.h"
#include "socfpga_sip_svc.h"
/*******************************************************************************
@ -151,6 +151,9 @@ static void __dead2 socfpga_system_reset(void)
static int socfpga_system_reset2(int is_vendor, int reset_type,
u_register_t cookie)
{
if (cold_reset_for_ecc_dbe()) {
mailbox_reset_cold();
}
/* disable cpuif */
gicv2_cpuif_disable();

19
plat/intel/soc/common/socfpga_sip_svc.c
View file

@ -10,6 +10,7 @@
#include <lib/mmio.h>
#include <tools_share/uuid.h>
#include "socfpga_fcs.h"
#include "socfpga_mailbox.h"
#include "socfpga_reset_manager.h"
#include "socfpga_sip_svc.h"
@ -139,21 +140,23 @@ static int intel_fpga_config_completed_write(uint32_t *completed_addr,
status = mailbox_read_response(job_id,
resp, &resp_len);
if (resp_len < 0)
if (status < 0) {
break;
}
max_blocks++;
if (mark_last_buffer_xfer_completed(
&completed_addr[*count]) == 0)
&completed_addr[*count]) == 0) {
*count = *count + 1;
else
} else {
break;
}
}
if (*count <= 0) {
if (resp_len != MBOX_NO_RESPONSE &&
resp_len != MBOX_TIMEOUT && resp_len != 0) {
if (status != MBOX_NO_RESPONSE &&
status != MBOX_TIMEOUT && resp_len != 0) {
mailbox_clear_response();
return INTEL_SIP_SMC_STATUS_ERROR;
}
@ -430,9 +433,9 @@ uintptr_t sip_smc_handler(uint32_t smc_fid,
u_register_t flags)
{
uint32_t retval = 0;
uint32_t status = INTEL_SIP_SMC_STATUS_OK;
uint32_t completed_addr[3];
uint64_t rsu_respbuf[9];
int status = INTEL_SIP_SMC_STATUS_OK;
int mbox_status;
unsigned int len_in_resp;
u_register_t x5, x6;
@ -527,6 +530,10 @@ uintptr_t sip_smc_handler(uint32_t smc_fid,
SMC_RET2(handle, status, retval);
}
case INTEL_SIP_SMC_ECC_DBE:
status = intel_ecc_dbe_notification(x1);
SMC_RET1(handle, status);
case INTEL_SIP_SMC_MBOX_SEND_CMD:
x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
x6 = SMC_GET_GP(handle, CTX_GPREG_X6);

165
plat/intel/soc/n5x/bl31_plat_setup.c Normal file
View file

@ -0,0 +1,165 @@
/*
* Copyright (c) 2020-2022, Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
#include <arch.h>
#include <arch_helpers.h>
#include <common/bl_common.h>
#include <drivers/arm/gicv2.h>
#include <drivers/ti/uart/uart_16550.h>
#include <lib/mmio.h>
#include <lib/xlat_tables/xlat_tables.h>
#include "ccu/ncore_ccu.h"
#include "socfpga_mailbox.h"
#include "socfpga_private.h"
static entry_point_info_t bl32_image_ep_info;
static entry_point_info_t bl33_image_ep_info;
entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
{
entry_point_info_t *next_image_info;
next_image_info = (type == NON_SECURE) ?
&bl33_image_ep_info : &bl32_image_ep_info;
/* None of the images on this platform can have 0x0 as the entrypoint */
if (next_image_info->pc) {
return next_image_info;
} else {
return NULL;
}
}
void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
static console_t console;
mmio_write_64(PLAT_SEC_ENTRY, 0);
console_16550_register(PLAT_UART0_BASE, PLAT_UART_CLOCK, PLAT_BAUDRATE,
&console);
/*
* Check params passed from BL31 should not be NULL,
*/
void *from_bl2 = (void *) arg0;
bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2;
assert(params_from_bl2 != NULL);
/*
* Copy BL32 (if populated by BL31) and BL33 entry point information.
* They are stored in Secure RAM, in BL31's address space.
*/
if (params_from_bl2->h.type == PARAM_BL_PARAMS &&
params_from_bl2->h.version >= VERSION_2) {
bl_params_node_t *bl_params = params_from_bl2->head;
while (bl_params != NULL) {
if (bl_params->image_id == BL33_IMAGE_ID)
bl33_image_ep_info = *bl_params->ep_info;
bl_params = bl_params->next_params_info;
}
} else {
struct socfpga_bl31_params *arg_from_bl2 =
(struct socfpga_bl31_params *) from_bl2;
assert(arg_from_bl2->h.type == PARAM_BL31);
assert(arg_from_bl2->h.version >= VERSION_1);
bl32_image_ep_info = *arg_from_bl2->bl32_ep_info;
bl33_image_ep_info = *arg_from_bl2->bl33_ep_info;
}
SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
}
static const interrupt_prop_t s10_interrupt_props[] = {
PLAT_INTEL_SOCFPGA_G1S_IRQ_PROPS(GICV2_INTR_GROUP0),
PLAT_INTEL_SOCFPGA_G0_IRQ_PROPS(GICV2_INTR_GROUP0)
};
static unsigned int target_mask_array[PLATFORM_CORE_COUNT];
static const gicv2_driver_data_t plat_gicv2_gic_data = {
.gicd_base = PLAT_INTEL_SOCFPGA_GICD_BASE,
.gicc_base = PLAT_INTEL_SOCFPGA_GICC_BASE,
.interrupt_props = s10_interrupt_props,
.interrupt_props_num = ARRAY_SIZE(s10_interrupt_props),
.target_masks = target_mask_array,
.target_masks_num = ARRAY_SIZE(target_mask_array),
};
/*******************************************************************************
* Perform any BL3-1 platform setup code
******************************************************************************/
void bl31_platform_setup(void)
{
socfpga_delay_timer_init();
/* Initialize the gic cpu and distributor interfaces */
gicv2_driver_init(&plat_gicv2_gic_data);
gicv2_distif_init();
gicv2_pcpu_distif_init();
gicv2_cpuif_enable();
/* Signal secondary CPUs to jump to BL31 (BL2 = U-boot SPL) */
mmio_write_64(PLAT_CPU_RELEASE_ADDR,
(uint64_t)plat_secondary_cpus_bl31_entry);
mailbox_hps_stage_notify(HPS_EXECUTION_STATE_SSBL);
ncore_enable_ocram_firewall();
}
const mmap_region_t plat_dm_mmap[] = {
MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE,
MT_MEMORY | MT_RW | MT_NS),
MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE,
MT_DEVICE | MT_RW | MT_NS),
MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE,
MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE,
MT_NON_CACHEABLE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(DEVICE3_BASE, DEVICE3_SIZE,
MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE,
MT_DEVICE | MT_RW | MT_NS),
MAP_REGION_FLAT(DEVICE4_BASE, DEVICE4_SIZE,
MT_DEVICE | MT_RW | MT_NS),
{0}
};
/*******************************************************************************
* Perform the very early platform specific architectural setup here. At the
* moment this is only intializes the mmu in a quick and dirty way.
******************************************************************************/
void bl31_plat_arch_setup(void)
{
const mmap_region_t bl_regions[] = {
MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE,
MT_MEMORY | MT_RW | MT_SECURE),
MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE,
MT_CODE | MT_SECURE),
MAP_REGION_FLAT(BL_RO_DATA_BASE,
BL_RO_DATA_END - BL_RO_DATA_BASE,
MT_RO_DATA | MT_SECURE),
#if USE_COHERENT_MEM
MAP_REGION_FLAT(BL_COHERENT_RAM_BASE,
BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
MT_DEVICE | MT_RW | MT_SECURE),
#endif
{0}
};
setup_page_tables(bl_regions, plat_dm_mmap);
enable_mmu_el3(0);
}

32
plat/intel/soc/n5x/include/socfpga_plat_def.h Normal file
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@ -0,0 +1,32 @@
/*
* Copyright (c) 2020-2022, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2020-2022, Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef PLAT_SOCFPGA_DEF_H
#define PLAT_SOCFPGA_DEF_H
#include <platform_def.h>
/* Platform Setting */
#define PLATFORM_MODEL PLAT_SOCFPGA_N5X
#define BOOT_SOURCE BOOT_SOURCE_SDMMC
/* FPGA config helpers */
#define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x400000
#define INTEL_SIP_SMC_FPGA_CONFIG_SIZE 0x2000000
/* Register Mapping */
#define SOCFPGA_MMC_REG_BASE U(0xff808000)
#define SOCFPGA_RSTMGR_REG_BASE U(0xffd11000)
#define SOCFPGA_SYSMGR_REG_BASE U(0xffd12000)
#define SOCFPGA_L4_PER_SCR_REG_BASE U(0xffd21000)
#define SOCFPGA_L4_SYS_SCR_REG_BASE U(0xffd21100)
#define SOCFPGA_SOC2FPGA_SCR_REG_BASE U(0xffd21200)
#define SOCFPGA_LWSOC2FPGA_SCR_REG_BASE U(0xffd21300)
#endif /* PLAT_SOCFPGA_DEF_H */

52
plat/intel/soc/n5x/platform.mk Normal file
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@ -0,0 +1,52 @@
#
# Copyright (c) 2020-2022, Intel Corporation. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
PLAT_INCLUDES := \
-Iplat/intel/soc/n5x/include/ \
-Iplat/intel/soc/common/drivers/ \
-Iplat/intel/soc/common/include/
# Include GICv2 driver files
include drivers/arm/gic/v2/gicv2.mk
DM_GICv2_SOURCES := \
${GICV2_SOURCES} \
plat/common/plat_gicv2.c
PLAT_BL_COMMON_SOURCES := \
${DM_GICv2_SOURCES} \
drivers/delay_timer/delay_timer.c \
drivers/delay_timer/generic_delay_timer.c \
drivers/ti/uart/aarch64/16550_console.S \
lib/xlat_tables/aarch64/xlat_tables.c \
lib/xlat_tables/xlat_tables_common.c \
plat/intel/soc/common/aarch64/platform_common.c \
plat/intel/soc/common/aarch64/plat_helpers.S \
plat/intel/soc/common/socfpga_delay_timer.c \
plat/intel/soc/common/drivers/ccu/ncore_ccu.c
BL2_SOURCES +=
BL31_SOURCES += \
drivers/arm/cci/cci.c \
lib/cpus/aarch64/aem_generic.S \
lib/cpus/aarch64/cortex_a53.S \
plat/common/plat_psci_common.c \
plat/intel/soc/n5x/bl31_plat_setup.c \
plat/intel/soc/common/socfpga_psci.c \
plat/intel/soc/common/socfpga_sip_svc.c \
plat/intel/soc/common/socfpga_topology.c \
plat/intel/soc/common/sip/socfpga_sip_ecc.c \
plat/intel/soc/common/sip/socfpga_sip_fcs.c \
plat/intel/soc/common/soc/socfpga_mailbox.c \
plat/intel/soc/common/soc/socfpga_reset_manager.c
PROGRAMMABLE_RESET_ADDRESS := 0
BL2_AT_EL3 := 1
BL2_INV_DCACHE := 0
MULTI_CONSOLE_API := 1
SIMICS_BUILD := 0
USE_COHERENT_MEM := 1

7
plat/intel/soc/stratix10/include/socfpga_plat_def.h
View file

@ -1,5 +1,6 @@
/*
* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -13,6 +14,10 @@
#define PLATFORM_MODEL PLAT_SOCFPGA_STRATIX10
#define BOOT_SOURCE BOOT_SOURCE_SDMMC
/* FPGA config helpers */
#define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x400000
#define INTEL_SIP_SMC_FPGA_CONFIG_SIZE 0x1000000
/* Register Mapping */
#define SOCFPGA_MMC_REG_BASE 0xff808000

7
plat/intel/soc/stratix10/platform.mk
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@ -1,6 +1,6 @@
#
# Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved.
# Copyright (c) 2019-2020, Intel Corporation. All rights reserved.
# Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved.
# Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@ -63,9 +63,12 @@ BL31_SOURCES += \
plat/intel/soc/common/socfpga_psci.c \
plat/intel/soc/common/socfpga_sip_svc.c \
plat/intel/soc/common/socfpga_topology.c \
plat/intel/soc/common/sip/socfpga_sip_ecc.c \
plat/intel/soc/common/sip/socfpga_sip_fcs.c \
plat/intel/soc/common/soc/socfpga_mailbox.c \
plat/intel/soc/common/soc/socfpga_reset_manager.c
PROGRAMMABLE_RESET_ADDRESS := 0
BL2_AT_EL3 := 1
SIMICS_BUILD := 0
USE_COHERENT_MEM := 1