Djam/arm-trusted-firmware
1
0
Fork 0
mirror of https://github.com/ARM-software/arm-trusted-firmware.git synced 2025-04-19 02:54:24 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

feat(st-ddr): add read valid training support

Browse source 
Add the read data eye training = training for optimal read valid placement
(RVTRN) when the built-in calibration is executed for LPDDR2 and LPDDR3.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: I7ac1c77c21ebc30315b532741f2f255c2312d5b2
This commit is contained in:
Nicolas Le Bayon 2021-09-10 12:03:38 +02:00 • committed by Yann Gautier
parent 26cf5cf6d6
commit 5def13eb01
2 changed files with 9 additions and 3 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

9
drivers/st/ddr/stm32mp1_ddr.c
View file

@ -868,9 +868,14 @@ void stm32mp1_ddr_init(struct ddr_info *priv,
/* /*
* 10. configure PUBL PIR register to specify which training step * 10. configure PUBL PIR register to specify which training step
* to run * to run
* Warning : RVTRN is not supported by this PUBL * RVTRN is executed only on LPDDR2/LPDDR3
*/ */
stm32mp1_ddrphy_init(priv->phy, DDRPHYC_PIR_QSTRN); pir = DDRPHYC_PIR_QSTRN;
if ((config->c_reg.mstr & DDRCTRL_MSTR_DDR3) == 0U) {
pir |= DDRPHYC_PIR_RVTRN;
}
stm32mp1_ddrphy_init(priv->phy, pir);
/* 11. monitor PUB PGSR.IDONE to poll cpmpletion of training sequence */ /* 11. monitor PUB PGSR.IDONE to poll cpmpletion of training sequence */
stm32mp1_ddrphy_idone_wait(priv->phy); stm32mp1_ddrphy_idone_wait(priv->phy);

3
include/drivers/st/stm32mp1_ddr_regs.h
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2017-2021, STMicroelectronics - All Rights Reserved * Copyright (c) 2017-2022, STMicroelectronics - All Rights Reserved
* *
* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
*/ */
@ -353,6 +353,7 @@ struct stm32mp1_ddrphy {
#define DDRPHYC_PIR_DRAMRST BIT(5) #define DDRPHYC_PIR_DRAMRST BIT(5)
#define DDRPHYC_PIR_DRAMINIT BIT(6) #define DDRPHYC_PIR_DRAMINIT BIT(6)
#define DDRPHYC_PIR_QSTRN BIT(7) #define DDRPHYC_PIR_QSTRN BIT(7)
#define DDRPHYC_PIR_RVTRN BIT(8)
#define DDRPHYC_PIR_ICPC BIT(16) #define DDRPHYC_PIR_ICPC BIT(16)
#define DDRPHYC_PIR_ZCALBYP BIT(30) #define DDRPHYC_PIR_ZCALBYP BIT(30)
#define DDRPHYC_PIR_INITSTEPS_MASK GENMASK(31, 7) #define DDRPHYC_PIR_INITSTEPS_MASK GENMASK(31, 7)