From 5de9d79bc4b2febe3b55db47039ab2004d8cd4af Mon Sep 17 00:00:00 2001
From: Jagdish Gediya <jagdish.gediya@arm.com>
Date: Mon, 1 Jul 2024 07:34:48 +0000
Subject: [PATCH] fix(tc): modify gpio controller base addr for TC4 FPGA

Modify gpio controller base addr for TC4 FPGA in dts to match
with its RoS configuration.

Change-Id: Id4ad925d23937d302adfb3e0d4b1573e5ec717c1
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>
---
 fdts/tc4.dts | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/fdts/tc4.dts b/fdts/tc4.dts
index ae9a0e529..14bd24170 100644
--- a/fdts/tc4.dts
+++ b/fdts/tc4.dts
@@ -23,13 +23,13 @@
 #define ETHERNET_ADDR			64000000
 #define ETHERNET_INT			799
 
-#define SYS_REGS_ADDR			60080000
-
 #if TARGET_FLAVOUR_FVP
+#define SYS_REGS_ADDR			60080000
 #define MMC_ADDR			600b0000
 #define MMC_INT_0			778
 #define MMC_INT_1			779
 #else /* TARGET_FLAVOUR_FPGA */
+#define SYS_REGS_ADDR			1c010000
 #define MMC_ADDR			1c050000
 #define MMC_INT_0			107
 #define MMC_INT_1			108