diff --git a/plat/intel/soc/agilex/include/socfpga_plat_def.h b/plat/intel/soc/agilex/include/socfpga_plat_def.h index 84124bd6d..72ffbe279 100644 --- a/plat/intel/soc/agilex/include/socfpga_plat_def.h +++ b/plat/intel/soc/agilex/include/socfpga_plat_def.h @@ -16,6 +16,11 @@ /* Platform Setting */ #define PLATFORM_MODEL PLAT_SOCFPGA_AGILEX #define BOOT_SOURCE BOOT_SOURCE_SDMMC +/* 1 = Flush cache, 0 = No cache flush. + * Default for Agilex is No cache flush. + * For Agilex FP8, set to Flush cache. + */ +#define CACHE_FLUSH 0 #define PLAT_PRIMARY_CPU 0 #define PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT MPIDR_AFF1_SHIFT #define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF0_SHIFT diff --git a/plat/intel/soc/agilex5/include/socfpga_plat_def.h b/plat/intel/soc/agilex5/include/socfpga_plat_def.h index d954406bd..ab6e2bcba 100644 --- a/plat/intel/soc/agilex5/include/socfpga_plat_def.h +++ b/plat/intel/soc/agilex5/include/socfpga_plat_def.h @@ -17,6 +17,10 @@ /* Platform Setting */ #define PLATFORM_MODEL PLAT_SOCFPGA_AGILEX5 #define BOOT_SOURCE BOOT_SOURCE_SDMMC +/* 1 = Flush cache, 0 = No cache flush. + * Default for Agilex5 is Cache flush. + */ +#define CACHE_FLUSH 1 #define MMC_DEVICE_TYPE 1 /* MMC = 0, SD = 1 */ #define XLAT_TABLES_V2 U(1) #define PLAT_PRIMARY_CPU_A55 0x000 diff --git a/plat/intel/soc/common/aarch64/plat_helpers.S b/plat/intel/soc/common/aarch64/plat_helpers.S index cbd012128..6ce4148a8 100644 --- a/plat/intel/soc/common/aarch64/plat_helpers.S +++ b/plat/intel/soc/common/aarch64/plat_helpers.S @@ -1,5 +1,7 @@ /* * Copyright (c) 2019-2023, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. + * Copyright (c) 2024, Altera Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -19,6 +21,7 @@ .globl plat_crash_console_flush .globl platform_mem_init .globl plat_secondary_cpus_bl31_entry + .globl invalidate_cache_low_el .globl plat_get_my_entrypoint @@ -213,3 +216,18 @@ func plat_secondary_cpus_bl31_entry _exception_vectors=runtime_exceptions \ _pie_fixup_size=BL31_LIMIT - BL31_BASE endfunc plat_secondary_cpus_bl31_entry + +/* -------------------------------------------------------- + * Invalidate for NS EL2 and EL1 + * -------------------------------------------------------- + */ +func invalidate_cache_low_el + mrs x0,SCR_EL3 + orr x1,x0,#SCR_NS_BIT + msr SCR_EL3, x1 + isb + tlbi ALLE2 + dsb sy + tlbi ALLE1 + dsb sy +endfunc invalidate_cache_low_el diff --git a/plat/intel/soc/common/drivers/ccu/ncore_ccu.c b/plat/intel/soc/common/drivers/ccu/ncore_ccu.c index ca76b6a4c..931ffcf95 100644 --- a/plat/intel/soc/common/drivers/ccu/ncore_ccu.c +++ b/plat/intel/soc/common/drivers/ccu/ncore_ccu.c @@ -1,10 +1,12 @@ /* * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. + * Copyright (c) 2024, Altera Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include #include +#include #include #include #include @@ -16,7 +18,24 @@ uint32_t poll_active_bit(uint32_t dir); -#define SMMU_DMI 1 +#define SMMU_DMI 1 +#define CCU_DMI0_DMIUSMCMCR SOCFPGA_CCU_NOC_REG_BASE + 0x7340 +#define CCU_DMI0_DMIUSMCMAR SOCFPGA_CCU_NOC_REG_BASE + 0x7344 +#define CCU_DMI0_DMIUSMCMCR_MNTOP GENMASK(3, 0) +#define MAX_DISTRIBUTED_MEM_INTERFACE 2 +#define FLUSH_ALL_ENTRIES 0x4 +#define CCU_DMI0_DMIUSMCMCR_ARRAY_ID GENMASK(21, 16) +#define ARRAY_ID_TAG 0x0 +#define ARRAY_ID_DATA 0x1 +#define CACHE_OPERATION_DONE BIT(0) +#define TIMEOUT_200MS 200 + +#define __bf_shf(x) (__builtin_ffsll(x) - 1) + +#define FIELD_PREP(_mask, _val) \ + ({ \ + ((typeof(_mask))(_val) << __bf_shf(_mask)) & (_mask); \ + }) #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 ncore_ccu_reg_t ncore_ccu_modules[] = { @@ -632,3 +651,61 @@ void setup_smmu_stream_id(void) mmio_write_32(SOCFPGA_SYSMGR(TSN_TBU_STREAM_CTRL_REG_3_TSN1), ENABLE_STREAMID); mmio_write_32(SOCFPGA_SYSMGR(TSN_TBU_STREAM_CTRL_REG_3_TSN2), ENABLE_STREAMID); } + +#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 +/* TODO: Temp added this here*/ +static int poll_idle_status(uint32_t addr, uint32_t mask, uint32_t match, uint32_t delay_ms) +{ + int time_out = delay_ms; + + while (time_out-- > 0) { + + if ((mmio_read_32(addr) & mask) == match) { + return 0; + } + udelay(1000); + } + + return -ETIMEDOUT; +} + +int flush_l3_dcache(void) +{ + int i; + int ret = 0; + + /* Flushing all entries in CCU system memory cache */ + for (i = 0; i < MAX_DISTRIBUTED_MEM_INTERFACE; i++) { + mmio_write_32(FIELD_PREP(CCU_DMI0_DMIUSMCMCR_MNTOP, FLUSH_ALL_ENTRIES) | + FIELD_PREP(CCU_DMI0_DMIUSMCMCR_ARRAY_ID, ARRAY_ID_TAG), + (uintptr_t)(CCU_DMI0_DMIUSMCMCR + (i * 0x1000))); + + /* Wait for cache maintenance operation done */ + ret = poll_idle_status((CCU_DMI0_DMIUSMCMAR + + (i * 0x1000)), CACHE_OPERATION_DONE, + CACHE_OPERATION_DONE, TIMEOUT_200MS); + + if (ret != 0) { + VERBOSE("%s: Timeout while waiting for flushing tag in DMI%d done\n", + __func__, i); + return ret; + } + + mmio_write_32(FIELD_PREP(CCU_DMI0_DMIUSMCMCR_MNTOP, FLUSH_ALL_ENTRIES) | + FIELD_PREP(CCU_DMI0_DMIUSMCMCR_ARRAY_ID, ARRAY_ID_DATA), + (uintptr_t)(CCU_DMI0_DMIUSMCMCR + (i * 0x1000))); + + /* Wait for cache maintenance operation done */ + ret = poll_idle_status((CCU_DMI0_DMIUSMCMAR + + (i * 0x1000)), CACHE_OPERATION_DONE, + CACHE_OPERATION_DONE, TIMEOUT_200MS); + + if (ret != 0) { + VERBOSE("%s: Timeout while waiting for flushing data in DMI%d done\n", + __func__, i); + } + } + + return ret; +} +#endif diff --git a/plat/intel/soc/common/drivers/ccu/ncore_ccu.h b/plat/intel/soc/common/drivers/ccu/ncore_ccu.h index e00c4b709..a89c098d6 100644 --- a/plat/intel/soc/common/drivers/ccu/ncore_ccu.h +++ b/plat/intel/soc/common/drivers/ccu/ncore_ccu.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. + * Copyright (c) 2024, Altera Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -452,5 +453,6 @@ typedef struct coh_ss_id { uint32_t init_ncore_ccu(void); void ncore_enable_ocram_firewall(void); void setup_smmu_stream_id(void); +int flush_l3_dcache(void); #endif diff --git a/plat/intel/soc/common/include/socfpga_private.h b/plat/intel/soc/common/include/socfpga_private.h index 041c282d3..b54b402f7 100644 --- a/plat/intel/soc/common/include/socfpga_private.h +++ b/plat/intel/soc/common/include/socfpga_private.h @@ -1,5 +1,6 @@ /* - * Copyright (c) 2019-2022, Intel Corporation. All rights reserved. + * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. + * Copyright (c) 2024, Altera Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -64,4 +65,6 @@ unsigned long socfpga_get_ns_image_entrypoint(void); void plat_secondary_cpus_bl31_entry(void); +void invalidate_cache_low_el(void); + #endif /* SOCFPGA_PRIVATE_H */ diff --git a/plat/intel/soc/common/socfpga_psci.c b/plat/intel/soc/common/socfpga_psci.c index 623843e3b..8baa8ddb4 100644 --- a/plat/intel/soc/common/socfpga_psci.c +++ b/plat/intel/soc/common/socfpga_psci.c @@ -17,8 +17,10 @@ #include #include #include +#include "ccu/ncore_ccu.h" #include "socfpga_mailbox.h" #include "socfpga_plat_def.h" +#include "socfpga_private.h" #include "socfpga_reset_manager.h" #include "socfpga_sip_svc.h" #include "socfpga_system_manager.h" @@ -190,6 +192,14 @@ static void __dead2 socfpga_system_reset(void) if (intel_rsu_update_address) { mailbox_rsu_update(addr_buf); } else { +#if CACHE_FLUSH + /* ATF Flush and Invalidate Cache */ + dcsw_op_all(DCCISW); + invalidate_cache_low_el(); +#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 + flush_l3_dcache(); +#endif +#endif mailbox_reset_cold(); } diff --git a/plat/intel/soc/stratix10/platform.mk b/plat/intel/soc/stratix10/platform.mk index afcf514f0..0a33c3d68 100644 --- a/plat/intel/soc/stratix10/platform.mk +++ b/plat/intel/soc/stratix10/platform.mk @@ -1,6 +1,7 @@ # # Copyright (c) 2019-2023, ARM Limited and Contributors. All rights reserved. -# Copyright (c) 2019-2022, Intel Corporation. All rights reserved. +# Copyright (c) 2019-2023, Intel Corporation. All rights reserved. +# Copyright (c) 2024, Altera Corporation. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -26,6 +27,7 @@ PLAT_BL_COMMON_SOURCES := \ lib/xlat_tables/xlat_tables_common.c \ plat/intel/soc/common/aarch64/platform_common.c \ plat/intel/soc/common/aarch64/plat_helpers.S \ + plat/intel/soc/common/drivers/ccu/ncore_ccu.c \ plat/intel/soc/common/socfpga_delay_timer.c \ plat/intel/soc/common/soc/socfpga_firewall.c