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https://github.com/ARM-software/arm-trusted-firmware.git
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plat/arm/juno: Add support to use hw_config in BL31
To make it possible to use the hw_config device tree for dynamic configuration in BL31 on the Arm Juno platform. A placeholder hw_config has been added that is included in the FIP and a Juno specific BL31 setup has been added to populate fconf with the hw_config. Juno's BL2 setup has been updated to align it with the new behavior implemented in the Arm FVP platform, where fw_config is passed in arg1 to BL31 instead of soc_fw_config. The BL31 setup is expected to use the fw_config passed in arg1 to find the hw_config. Signed-off-by: Mikael Olsson <mikael.olsson@arm.com> Change-Id: Ib3570faa6714f92ab8451e8f1e59779dcf19c0b6
This commit is contained in:
parent
a9e14e202f
commit
5d5fb10f9c
8 changed files with 142 additions and 8 deletions
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@ -1742,9 +1742,9 @@ In Arm standard platforms, the arguments received are :
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which is list of executable images following BL31,
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arg1 - Points to load address of SOC_FW_CONFIG if present
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except in case of Arm FVP platform.
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except in case of Arm FVP and Juno platform.
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In case of Arm FVP platform, Points to load address
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In case of Arm FVP and Juno platform, points to load address
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of FW_CONFIG.
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arg2 - Points to load address of HW_CONFIG if present
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11
fdts/juno.dts
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11
fdts/juno.dts
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@ -0,0 +1,11 @@
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/*
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* Copyright (c) 2021, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/dts-v1/;
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/ {
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};
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2019-2020, ARM Limited. All rights reserved.
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* Copyright (c) 2019-2021, ARM Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -17,5 +17,11 @@
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max-size = <0x200>;
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id = <TB_FW_CONFIG_ID>;
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};
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hw-config {
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load-address = <0x0 0x82000000>;
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max-size = <0x8000>;
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id = <HW_CONFIG_ID>;
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};
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};
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};
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -53,6 +53,14 @@
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#define PLAT_ARM_DRAM2_BASE ULL(0x880000000)
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#define PLAT_ARM_DRAM2_SIZE ULL(0x180000000)
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#define PLAT_HW_CONFIG_DTB_BASE ULL(0x82000000)
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#define PLAT_HW_CONFIG_DTB_SIZE ULL(0x00008000) /* 32KB */
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#define ARM_DTB_DRAM_NS MAP_REGION_FLAT( \
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PLAT_HW_CONFIG_DTB_BASE, \
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PLAT_HW_CONFIG_DTB_SIZE, \
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MT_MEMORY | MT_RO | MT_NS)
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/* virtual address used by dynamic mem_protect for chunk_base */
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#define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000)
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@ -108,7 +116,7 @@
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#ifdef IMAGE_BL31
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# define PLAT_ARM_MMAP_ENTRIES 7
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# define MAX_XLAT_TABLES 3
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# define MAX_XLAT_TABLES 5
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#endif
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#ifdef IMAGE_BL32
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2016-2017,2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -8,6 +8,9 @@
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#include <common/bl_common.h>
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#include <common/desc_image_load.h>
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#include <lib/fconf/fconf.h>
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#include <lib/fconf/fconf_dyn_cfg_getter.h>
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#include <plat/arm/common/plat_arm.h>
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#if JUNO_AARCH32_EL3_RUNTIME
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@ -30,4 +33,41 @@ int arm_bl2_plat_handle_post_image_load(unsigned int image_id)
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return err;
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}
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#else
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/*******************************************************************************
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* This function returns the list of executable images
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******************************************************************************/
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struct bl_params *plat_get_next_bl_params(void)
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{
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struct bl_params *arm_bl_params = arm_get_next_bl_params();
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#if __aarch64__
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const struct dyn_cfg_dtb_info_t *fw_config_info;
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bl_mem_params_node_t *param_node;
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uintptr_t fw_config_base = 0U;
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entry_point_info_t *ep_info;
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/* Get BL31 image node */
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param_node = get_bl_mem_params_node(BL31_IMAGE_ID);
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assert(param_node != NULL);
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/* Get fw_config load address */
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fw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, FW_CONFIG_ID);
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assert(fw_config_info != NULL);
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fw_config_base = fw_config_info->config_addr;
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assert(fw_config_base != 0U);
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/*
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* Get the entry point info of BL31 image and override
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* arg1 of entry point info with fw_config base address
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*/
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ep_info = ¶m_node->ep_info;
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ep_info->args.arg1 = (uint32_t)fw_config_base;
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#endif /* __aarch64__ */
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return arm_bl_params;
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}
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#endif /* JUNO_AARCH32_EL3_RUNTIME */
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60
plat/arm/board/juno/juno_bl31_setup.c
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60
plat/arm/board/juno/juno_bl31_setup.c
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@ -0,0 +1,60 @@
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/*
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* Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <common/debug.h>
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#include <lib/fconf/fconf.h>
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#include <lib/fconf/fconf_dyn_cfg_getter.h>
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#include <plat/arm/common/plat_arm.h>
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void __init bl31_early_platform_setup2(u_register_t arg0,
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u_register_t arg1, u_register_t arg2, u_register_t arg3)
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{
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const struct dyn_cfg_dtb_info_t *soc_fw_config_info;
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INFO("BL31 FCONF: FW_CONFIG address = %lx\n", (uintptr_t)arg1);
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/* Fill the properties struct with the info from the config dtb */
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fconf_populate("FW_CONFIG", arg1);
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soc_fw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, SOC_FW_CONFIG_ID);
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if (soc_fw_config_info != NULL) {
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arg1 = soc_fw_config_info->config_addr;
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}
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arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
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/*
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* Initialize Interconnect for this cluster during cold boot.
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* No need for locks as no other CPU is active.
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*/
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plat_arm_interconnect_init();
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/*
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* Enable Interconnect coherency for the primary CPU's cluster.
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* Earlier bootloader stages might already do this (e.g. Trusted
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* Firmware's BL1 does it) but we can't assume so. There is no harm in
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* executing this code twice anyway.
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* Platform specific PSCI code will enable coherency for other
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* clusters.
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*/
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plat_arm_interconnect_enter_coherency();
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}
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void __init bl31_plat_arch_setup(void)
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{
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arm_bl31_plat_arch_setup();
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/* HW_CONFIG was also loaded by BL2 */
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const struct dyn_cfg_dtb_info_t *hw_config_info;
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hw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, HW_CONFIG_ID);
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assert(hw_config_info != NULL);
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fconf_populate("HW_CONFIG", hw_config_info->config_addr);
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}
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -75,6 +75,7 @@ const mmap_region_t plat_arm_mmap[] = {
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ARM_V2M_MAP_MEM_PROTECT,
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#endif
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SOC_CSS_MAP_DEVICE,
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ARM_DTB_DRAM_NS,
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{0}
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};
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#endif
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@ -83,6 +83,10 @@ BL31_SOURCES += drivers/cfi/v2m/v2m_flash.c \
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lib/cpus/aarch64/cortex_a57.S \
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lib/cpus/aarch64/cortex_a72.S \
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lib/utils/mem_region.c \
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common/fdt_wrappers.c \
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lib/fconf/fconf.c \
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lib/fconf/fconf_dyn_cfg_getter.c \
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plat/arm/board/juno/juno_bl31_setup.c \
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plat/arm/board/juno/juno_pm.c \
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plat/arm/board/juno/juno_topology.c \
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plat/arm/common/arm_nor_psci_mem_protect.c \
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@ -174,15 +178,19 @@ BL32_CPPFLAGS += -march=armv8-a+crc
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# Add the FDT_SOURCES and options for Dynamic Config
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FDT_SOURCES += plat/arm/board/juno/fdts/${PLAT}_fw_config.dts \
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plat/arm/board/juno/fdts/${PLAT}_tb_fw_config.dts
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plat/arm/board/juno/fdts/${PLAT}_tb_fw_config.dts \
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fdts/${PLAT}.dts
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FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb
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TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb
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HW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}.dtb
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# Add the FW_CONFIG to FIP and specify the same to certtool
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$(eval $(call TOOL_ADD_PAYLOAD,${FW_CONFIG},--fw-config,${FW_CONFIG}))
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# Add the TB_FW_CONFIG to FIP and specify the same to certtool
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$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG}))
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# Add the HW_CONFIG to FIP and specify the same to certtool
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$(eval $(call TOOL_ADD_PAYLOAD,${HW_CONFIG},--hw-config,${HW_CONFIG}))
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include plat/arm/board/common/board_common.mk
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include plat/arm/common/arm_common.mk
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