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Merge "feat(intel): update BL2 platform specific functions" into integration

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Mark Dykes 2024-10-24 22:18:49 +02:00 • committed by TrustedFirmware Code Review
commit 5d23325e6b
3 changed files with 32 additions and 7 deletions
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31
plat/intel/soc/agilex5/bl2_plat_setup.c
View file

@ -68,8 +68,10 @@ const mmap_region_t agilex_plat_mmap[] = {
boot_source_type boot_source = BOOT_SOURCE; boot_source_type boot_source = BOOT_SOURCE;
void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1, void bl2_el3_early_platform_setup(u_register_t x0 __unused,
u_register_t x2, u_register_t x4) u_register_t x1 __unused,
u_register_t x2 __unused,
u_register_t x3 __unused)
{ {
static console_t console; static console_t console;
handoff reverse_handoff_ptr; handoff reverse_handoff_ptr;
@ -94,22 +96,41 @@ void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1,
/* Get the handoff data */ /* Get the handoff data */
if ((socfpga_get_handoff(&reverse_handoff_ptr)) != 0) { if ((socfpga_get_handoff(&reverse_handoff_ptr)) != 0) {
ERROR("BL2: Failed to get the correct handoff data\n"); ERROR("SOCFPGA: Failed to get the correct handoff data\n");
panic();
}
/* Configure the pinmux */
config_pinmux(&reverse_handoff_ptr);
/* Configure the clock manager */
if ((config_clkmgr_handoff(&reverse_handoff_ptr)) != 0) {
ERROR("SOCFPGA: Failed to initialize the clock manager\n");
panic(); panic();
} }
config_clkmgr_handoff(&reverse_handoff_ptr);
/* Configure power manager PSS SRAM power gate */ /* Configure power manager PSS SRAM power gate */
config_pwrmgr_handoff(&reverse_handoff_ptr); config_pwrmgr_handoff(&reverse_handoff_ptr);
/* Initialize the mailbox to enable communication between HPS and SDM */ /* Initialize the mailbox to enable communication between HPS and SDM */
mailbox_init(); mailbox_init();
/* Perform a handshake with certain peripherals before issuing a reset */
config_hps_hs_before_warm_reset();
/* TODO: watchdog init */
//watchdog_init(clkmgr_get_rate(CLKMGR_WDT_CLK_ID));
/* Initialize the CCU module for hardware cache coherency */
init_ncore_ccu();
socfpga_emac_init();
/* DDR and IOSSM driver init */ /* DDR and IOSSM driver init */
agilex5_ddr_init(&reverse_handoff_ptr); agilex5_ddr_init(&reverse_handoff_ptr);
if (combo_phy_init(&reverse_handoff_ptr) != 0) { if (combo_phy_init(&reverse_handoff_ptr) != 0) {
ERROR("Combo Phy initialization failed\n"); ERROR("SOCFPGA: Combo Phy initialization failed\n");
} }
/* Enable FPGA bridges as required */ /* Enable FPGA bridges as required */

3
plat/intel/soc/agilex5/include/agilex5_clock_manager.h
View file

@ -1,5 +1,6 @@
/* /*
* Copyright (c) 2019-2022, Intel Corporation. All rights reserved. * Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
* Copyright (c) 2024, Altera Corporation. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -142,7 +143,7 @@ typedef struct {
uint32_t clk_freq_of_cb_intosc_ls; uint32_t clk_freq_of_cb_intosc_ls;
} CLOCK_SOURCE_CONFIG; } CLOCK_SOURCE_CONFIG;
void config_clkmgr_handoff(handoff *hoff_ptr); int config_clkmgr_handoff(handoff *hoff_ptr);
uint32_t get_wdt_clk(void); uint32_t get_wdt_clk(void);
uint32_t get_uart_clk(void); uint32_t get_uart_clk(void);
uint32_t get_mmc_clk(void); uint32_t get_mmc_clk(void);

5
plat/intel/soc/agilex5/soc/agilex5_clock_manager.c
View file

@ -1,5 +1,6 @@
/* /*
* Copyright (c) 2019-2023, Intel Corporation. All rights reserved. * Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
* Copyright (c) 2024, Altera Corporation. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -93,7 +94,7 @@ uint32_t pll_source_sync_read(uint32_t pll_mem_offset)
return rdata; return rdata;
} }
void config_clkmgr_handoff(handoff *hoff_ptr) int config_clkmgr_handoff(handoff *hoff_ptr)
{ {
/* Take both PLL out of reset and power up */ /* Take both PLL out of reset and power up */
@ -129,6 +130,8 @@ void config_clkmgr_handoff(handoff *hoff_ptr)
CLKMGR_MAINPLL_EN_RESET); CLKMGR_MAINPLL_EN_RESET);
mmio_write_32(CLKMGR_PERPLL + CLKMGR_PERPLL_EN, mmio_write_32(CLKMGR_PERPLL + CLKMGR_PERPLL_EN,
CLKMGR_PERPLL_EN_RESET); CLKMGR_PERPLL_EN_RESET);
return 0;
} }
/* Extract reference clock from platform clock source */ /* Extract reference clock from platform clock source */