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fix(cpus): workaround for Cortex-X3 erratum 2742421

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Cortex-X3 erratum 2742421 is a Cat B erratum that applies to
all revisions <= r1p1 and is fixed in r1p2. The workaround is to
set CPUACTLR5_EL1[56:55] to 2'b01.

SDEN documentation:
https://developer.arm.com/documentation/2055130/latest

Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
Change-Id: Idadd323e419739fe909b9b68ea2dbe857846666b
This commit is contained in:
Sona Mathew 2023-09-05 14:10:03 -05:00
parent 9c16521606
commit 5b0e4438d0
5 changed files with 26 additions and 2 deletions
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4
docs/design/cpu-specific-build-macros.rst
View file

@ -715,6 +715,10 @@ For Cortex-X3, the following errata build flags are defined :
CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1 of the
CPU, it is still open.
- ``ERRATA_X3_2742421``: This applies errata 2742421 workaround to
Cortex-X3 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
r1p1. It is fixed in r1p2.
For Cortex-A510, the following errata build flags are defined :
- ``ERRATA_A510_1922240``: This applies errata 1922240 workaround to

9
include/lib/cpus/aarch64/cortex_x3.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2021-2022, Arm Limited. All rights reserved.
* Copyright (c) 2021-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -31,4 +31,11 @@
#define CORTEX_X3_CPUACTLR2_EL1 S3_0_C15_C1_1
#define CORTEX_X3_CPUACTLR2_EL1_BIT_36 (ULL(1) << 36)
/*******************************************************************************
* CPU Auxiliary Control register 5 specific definitions.
******************************************************************************/
#define CORTEX_X3_CPUACTLR5_EL1 S3_0_C15_C8_0
#define CORTEX_X3_CPUACTLR5_EL1_BIT_55 (ULL(1) << 55)
#define CORTEX_X3_CPUACTLR5_EL1_BIT_56 (ULL(1) << 56)
#endif /* CORTEX_X3_H */

8
lib/cpus/aarch64/cortex_x3.S
View file

@ -42,6 +42,14 @@ workaround_reset_end cortex_x3, ERRATUM(2615812)
check_erratum_ls cortex_x3, ERRATUM(2615812), CPU_REV(1, 1)
workaround_reset_start cortex_x3, ERRATUM(2742421), ERRATA_X3_2742421
/* Set CPUACTLR5_EL1[56:55] to 2'b01 */
sysreg_bit_set CORTEX_X3_CPUACTLR5_EL1, CORTEX_X3_CPUACTLR5_EL1_BIT_55
sysreg_bit_clear CORTEX_X3_CPUACTLR5_EL1, CORTEX_X3_CPUACTLR5_EL1_BIT_56
workaround_reset_end cortex_x3, ERRATUM(2742421)
check_erratum_ls cortex_x3, ERRATUM(2742421), CPU_REV(1, 1)
workaround_reset_start cortex_x3, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
#if IMAGE_BL31
override_vector_table wa_cve_vbar_cortex_x3

4
lib/cpus/cpu-ops.mk
View file

@ -738,6 +738,10 @@ CPU_FLAG_LIST += ERRATA_X3_2313909
# to revisions r0p0, r1p0, r1p1 of the Cortex-X3 cpu, it is still open.
CPU_FLAG_LIST += ERRATA_X3_2615812
# Flag to apply erratum 2742421 workaround on reset. This erratum applies
# to revisions r0p0, r1p0 and r1p1 of the Cortex-X3 cpu, it is fixed in r1p2.
CPU_FLAG_LIST += ERRATA_X3_2742421
# Flag to apply erratum 1922240 workaround during reset. This erratum applies
# to revision r0p0 of the Cortex-A510 cpu and is fixed in r0p1.
CPU_FLAG_LIST += ERRATA_A510_1922240

3
services/std_svc/errata_abi/errata_abi_main.c
View file

@ -424,7 +424,8 @@ struct em_cpu_list cpu_list[] = {
.cpu_errata_list = {
[0] = {2313909, 0x00, 0x10, ERRATA_X3_2313909},
[1] = {2615812, 0x00, 0x11, ERRATA_X3_2615812},
[2 ... ERRATA_LIST_END] = UNDEF_ERRATA,
[2] = {2742421, 0x00, 0x11, ERRATA_X3_2742421},
[3 ... ERRATA_LIST_END] = UNDEF_ERRATA,
}
},
#endif /* CORTEX_X3_H_INC */