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https://github.com/ARM-software/arm-trusted-firmware.git
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stm32mp1: update platform files
Move print_reset_reason function to bl2_plat_setup.c Put __unused attribute for unused bl2_el3_early_platform_setup args. Rename dt_dev_info to dt_uart_info. Put MMU configuration earlier. Remove unused macros. Use U() or ULL() macros where needed. Use device tree to configure GIC. Use GIC helper function. Change-Id: I34620c421cc6967a668bca318f7689fd74fa78a6 Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
This commit is contained in:
Yann Gautier
parent
4156d4daa8
commit
59a1cdf16a
10 changed files with 244 additions and 203 deletions
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -58,13 +58,26 @@ static const io_block_dev_spec_t mmc_block_dev_spec = {
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static uintptr_t storage_dev_handle;
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static const io_dev_connector_t *mmc_dev_con;
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#define IMG_IDX_BL33 0
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static const io_block_spec_t bl32_block_spec = {
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.offset = BL32_BASE,
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.length = STM32MP1_BL32_SIZE
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};
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static const io_block_spec_t bl2_block_spec = {
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.offset = BL2_BASE,
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.length = STM32MP1_BL2_SIZE,
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};
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static const struct stm32image_part_info bl33_partition_spec = {
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.name = BL33_IMAGE_NAME,
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.binary_type = BL33_BINARY_TYPE,
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};
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enum {
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IMG_IDX_BL33,
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IMG_IDX_NUM
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};
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static struct stm32image_device_info stm32image_dev_info_spec = {
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.lba_size = MMC_BLOCK_SIZE,
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.part_info[IMG_IDX_BL33] = {
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@ -73,20 +86,13 @@ static struct stm32image_device_info stm32image_dev_info_spec = {
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},
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};
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static io_block_spec_t stm32image_block_spec;
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static io_block_spec_t stm32image_block_spec = {
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.offset = 0,
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.length = 0,
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};
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static const io_dev_connector_t *stm32image_dev_con;
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static const io_block_spec_t bl32_block_spec = {
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.offset = BL32_BASE,
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.length = STM32MP1_BL32_SIZE
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};
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static const io_block_spec_t bl2_block_spec = {
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.offset = BL2_BASE,
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.length = STM32MP1_BL2_SIZE,
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};
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static int open_dummy(const uintptr_t spec);
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static int open_image(const uintptr_t spec);
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static int open_storage(const uintptr_t spec);
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@ -160,83 +166,18 @@ static void print_boot_device(boot_api_context_t *boot_context)
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}
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}
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static void print_reset_reason(void)
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{
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uint32_t rstsr = mmio_read_32(RCC_BASE + RCC_MP_RSTSCLRR);
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if (rstsr == 0U) {
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WARN("Reset reason unknown\n");
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return;
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}
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INFO("Reset reason (0x%x):\n", rstsr);
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if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) == 0U) {
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if ((rstsr & RCC_MP_RSTSCLRR_STDBYRSTF) != 0U) {
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INFO("System exits from STANDBY\n");
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return;
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}
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if ((rstsr & RCC_MP_RSTSCLRR_CSTDBYRSTF) != 0U) {
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INFO("MPU exits from CSTANDBY\n");
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return;
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}
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}
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if ((rstsr & RCC_MP_RSTSCLRR_PORRSTF) != 0U) {
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INFO(" Power-on Reset (rst_por)\n");
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return;
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}
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if ((rstsr & RCC_MP_RSTSCLRR_BORRSTF) != 0U) {
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INFO(" Brownout Reset (rst_bor)\n");
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return;
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}
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if ((rstsr & RCC_MP_RSTSCLRR_MPSYSRSTF) != 0U) {
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INFO(" System reset generated by MPU (MPSYSRST)\n");
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return;
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}
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if ((rstsr & RCC_MP_RSTSCLRR_HCSSRSTF) != 0U) {
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INFO(" Reset due to a clock failure on HSE\n");
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return;
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}
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if ((rstsr & RCC_MP_RSTSCLRR_IWDG1RSTF) != 0U) {
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INFO(" IWDG1 Reset (rst_iwdg1)\n");
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return;
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}
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if ((rstsr & RCC_MP_RSTSCLRR_IWDG2RSTF) != 0U) {
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INFO(" IWDG2 Reset (rst_iwdg2)\n");
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return;
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}
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if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) {
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INFO(" Pad Reset from NRST\n");
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return;
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}
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if ((rstsr & RCC_MP_RSTSCLRR_VCORERSTF) != 0U) {
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INFO(" Reset due to a failure of VDD_CORE\n");
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return;
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}
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ERROR(" Unidentified reset reason\n");
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}
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void stm32mp1_io_setup(void)
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{
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int io_result __unused;
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uint8_t idx;
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struct stm32image_part_info *part;
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struct stm32_sdmmc2_params params;
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struct mmc_device_info device_info;
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uintptr_t mmc_default_instance;
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const partition_entry_t *entry;
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boot_api_context_t *boot_context =
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(boot_api_context_t *)stm32mp1_get_boot_ctx_address();
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print_reset_reason();
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print_boot_device(boot_context);
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if ((boot_context->boot_partition_used_toboot == 1U) ||
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@ -255,7 +196,7 @@ void stm32mp1_io_setup(void)
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switch (boot_context->boot_interface_selected) {
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case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD:
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case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC:
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dmb();
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dmbsy();
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memset(¶ms, 0, sizeof(struct stm32_sdmmc2_params));
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@ -309,14 +250,19 @@ void stm32mp1_io_setup(void)
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stm32image_dev_info_spec.device_size =
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stm32_sdmmc2_mmc_get_device_size();
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stm32image_dev_info_spec.part_info[IMG_IDX_BL33].part_offset =
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get_partition_entry(BL33_IMAGE_NAME)->start;
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stm32image_dev_info_spec.part_info[IMG_IDX_BL33].bkp_offset =
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get_partition_entry(BL33_IMAGE_NAME)->length;
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stm32image_block_spec.offset = 0;
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stm32image_block_spec.length =
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get_partition_entry(BL33_IMAGE_NAME)->length;
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for (idx = 0U; idx < IMG_IDX_NUM; idx++) {
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part = &stm32image_dev_info_spec.part_info[idx];
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entry = get_partition_entry(part->name);
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if (entry == NULL) {
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ERROR("Partition %s not found\n",
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part->name);
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panic();
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}
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part->part_offset = entry->start;
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part->bkp_offset = 0U;
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}
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/*
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* Re-open MMC with io_mmc, for better perfs compared to
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@ -33,8 +33,95 @@
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static struct console_stm32 console;
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void bl2_el3_early_platform_setup(u_register_t arg0, u_register_t arg1,
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u_register_t arg2, u_register_t arg3)
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static void print_reset_reason(void)
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{
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uint32_t rstsr = mmio_read_32(RCC_BASE + RCC_MP_RSTSCLRR);
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if (rstsr == 0U) {
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WARN("Reset reason unknown\n");
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return;
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}
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INFO("Reset reason (0x%x):\n", rstsr);
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if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) == 0U) {
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if ((rstsr & RCC_MP_RSTSCLRR_STDBYRSTF) != 0U) {
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INFO("System exits from STANDBY\n");
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return;
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}
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if ((rstsr & RCC_MP_RSTSCLRR_CSTDBYRSTF) != 0U) {
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INFO("MPU exits from CSTANDBY\n");
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return;
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}
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}
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if ((rstsr & RCC_MP_RSTSCLRR_PORRSTF) != 0U) {
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INFO(" Power-on Reset (rst_por)\n");
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return;
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}
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if ((rstsr & RCC_MP_RSTSCLRR_BORRSTF) != 0U) {
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INFO(" Brownout Reset (rst_bor)\n");
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return;
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}
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if ((rstsr & RCC_MP_RSTSCLRR_MCSYSRSTF) != 0U) {
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if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) {
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INFO(" System reset generated by MCU (MCSYSRST)\n");
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} else {
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INFO(" Local reset generated by MCU (MCSYSRST)\n");
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}
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return;
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}
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if ((rstsr & RCC_MP_RSTSCLRR_MPSYSRSTF) != 0U) {
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INFO(" System reset generated by MPU (MPSYSRST)\n");
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return;
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}
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if ((rstsr & RCC_MP_RSTSCLRR_HCSSRSTF) != 0U) {
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INFO(" Reset due to a clock failure on HSE\n");
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return;
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}
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if ((rstsr & RCC_MP_RSTSCLRR_IWDG1RSTF) != 0U) {
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INFO(" IWDG1 Reset (rst_iwdg1)\n");
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return;
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}
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if ((rstsr & RCC_MP_RSTSCLRR_IWDG2RSTF) != 0U) {
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INFO(" IWDG2 Reset (rst_iwdg2)\n");
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return;
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}
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if ((rstsr & RCC_MP_RSTSCLRR_MPUP0RSTF) != 0U) {
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INFO(" MPU Processor 0 Reset\n");
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return;
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}
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if ((rstsr & RCC_MP_RSTSCLRR_MPUP1RSTF) != 0U) {
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INFO(" MPU Processor 1 Reset\n");
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return;
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}
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if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) {
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INFO(" Pad Reset from NRST\n");
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return;
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}
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if ((rstsr & RCC_MP_RSTSCLRR_VCORERSTF) != 0U) {
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INFO(" Reset due to a failure of VDD_CORE\n");
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return;
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}
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ERROR(" Unidentified reset reason\n");
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}
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void bl2_el3_early_platform_setup(u_register_t arg0,
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u_register_t arg1 __unused,
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u_register_t arg2 __unused,
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u_register_t arg3 __unused)
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{
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stm32mp1_save_boot_ctx_address(arg0);
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}
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@ -59,12 +146,38 @@ void bl2_platform_setup(void)
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void bl2_el3_plat_arch_setup(void)
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{
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int32_t result;
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struct dt_node_info dt_dev_info;
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struct dt_node_info dt_uart_info;
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const char *board_model;
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boot_api_context_t *boot_context =
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(boot_api_context_t *)stm32mp1_get_boot_ctx_address();
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uint32_t clk_rate;
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mmap_add_region(BL_CODE_BASE, BL_CODE_BASE,
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BL_CODE_END - BL_CODE_BASE,
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MT_CODE | MT_SECURE);
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/* Prevent corruption of preloaded BL32 */
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mmap_add_region(BL32_BASE, BL32_BASE,
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BL32_LIMIT - BL32_BASE,
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MT_MEMORY | MT_RO | MT_SECURE);
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/* Map non secure DDR for BL33 load and DDR training area restore */
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mmap_add_region(STM32MP1_DDR_BASE,
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STM32MP1_DDR_BASE,
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STM32MP1_DDR_MAX_SIZE,
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MT_MEMORY | MT_RW | MT_NS);
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/* Prevent corruption of preloaded Device Tree */
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mmap_add_region(DTB_BASE, DTB_BASE,
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DTB_LIMIT - DTB_BASE,
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MT_MEMORY | MT_RO | MT_SECURE);
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configure_mmu();
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if (dt_open_and_check() < 0) {
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panic();
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}
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/*
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* Disable the backup domain write protection.
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* The protection is enable at each reset by hardware
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@ -88,28 +201,8 @@ void bl2_el3_plat_arch_setup(void)
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mmio_clrbits_32(RCC_BASE + RCC_BDCR, RCC_BDCR_VSWRST);
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}
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mmap_add_region(BL_CODE_BASE, BL_CODE_BASE,
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BL_CODE_END - BL_CODE_BASE,
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MT_CODE | MT_SECURE);
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/* Prevent corruption of preloaded BL32 */
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mmap_add_region(BL32_BASE, BL32_BASE,
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BL32_LIMIT - BL32_BASE,
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MT_MEMORY | MT_RO | MT_SECURE);
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/* Prevent corruption of preloaded Device Tree */
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mmap_add_region(DTB_BASE, DTB_BASE,
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DTB_LIMIT - DTB_BASE,
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MT_MEMORY | MT_RO | MT_SECURE);
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configure_mmu();
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generic_delay_timer_init();
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if (dt_open_and_check() < 0) {
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panic();
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}
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if (stm32mp1_clk_probe() < 0) {
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panic();
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}
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@ -118,12 +211,12 @@ void bl2_el3_plat_arch_setup(void)
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panic();
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}
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result = dt_get_stdout_uart_info(&dt_dev_info);
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result = dt_get_stdout_uart_info(&dt_uart_info);
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if ((result <= 0) ||
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(dt_dev_info.status == 0U) ||
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(dt_dev_info.clock < 0) ||
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(dt_dev_info.reset < 0)) {
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(dt_uart_info.status == 0U) ||
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(dt_uart_info.clock < 0) ||
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(dt_uart_info.reset < 0)) {
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goto skip_console_init;
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}
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@ -131,25 +224,25 @@ void bl2_el3_plat_arch_setup(void)
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goto skip_console_init;
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}
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if (stm32mp1_clk_enable((unsigned long)dt_dev_info.clock) != 0) {
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if (stm32mp1_clk_enable((unsigned long)dt_uart_info.clock) != 0) {
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goto skip_console_init;
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}
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stm32mp1_reset_assert((uint32_t)dt_dev_info.reset);
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stm32mp1_reset_assert((uint32_t)dt_uart_info.reset);
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udelay(2);
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stm32mp1_reset_deassert((uint32_t)dt_dev_info.reset);
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stm32mp1_reset_deassert((uint32_t)dt_uart_info.reset);
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mdelay(1);
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clk_rate = stm32mp1_clk_get_rate((unsigned long)dt_dev_info.clock);
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clk_rate = stm32mp1_clk_get_rate((unsigned long)dt_uart_info.clock);
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if (console_stm32_register(dt_dev_info.base, clk_rate,
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if (console_stm32_register(dt_uart_info.base, clk_rate,
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STM32MP1_UART_BAUDRATE, &console) == 0) {
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panic();
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}
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board_model = dt_get_board_model();
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if (board_model != NULL) {
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NOTICE("%s\n", board_model);
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NOTICE("Model: %s\n", board_model);
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}
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skip_console_init:
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@ -162,5 +255,7 @@ skip_console_init:
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stm32mp1_arch_security_setup();
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print_reset_reason();
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stm32mp1_io_setup();
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}
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|
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@ -1,5 +1,5 @@
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/*
|
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* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
|
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* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
|
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*
|
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -30,8 +30,8 @@
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#define BL33_BINARY_TYPE U(0x0)
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#define STM32MP1_PRIMARY_CPU U(0x0)
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#define STM32MP1_SECONDARY_CPU U(0x1)
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#define PLATFORM_CACHE_LINE_SIZE 64
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#define PLATFORM_CLUSTER_COUNT ULL(1)
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#define PLATFORM_CLUSTER0_CORE_COUNT U(2)
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#define PLATFORM_CLUSTER1_CORE_COUNT U(0)
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|
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@ -39,9 +39,9 @@
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PLATFORM_CLUSTER0_CORE_COUNT)
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#define PLATFORM_MAX_CPUS_PER_CLUSTER 2
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|
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#define MAX_IO_DEVICES 4
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#define MAX_IO_HANDLES 4
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#define MAX_IO_BLOCK_DEVICES 1
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#define MAX_IO_DEVICES U(4)
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#define MAX_IO_HANDLES U(4)
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#define MAX_IO_BLOCK_DEVICES U(1)
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/*******************************************************************************
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* BL2 specific defines.
|
||||
|
|
@ -81,8 +81,8 @@
|
|||
/*******************************************************************************
|
||||
* Platform specific page table and MMU setup constants
|
||||
******************************************************************************/
|
||||
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
|
||||
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
|
||||
#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 32)
|
||||
#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 32)
|
||||
|
||||
/*******************************************************************************
|
||||
* Declarations and constants to access the mailboxes safely. Each mailbox is
|
||||
|
|
@ -123,9 +123,6 @@
|
|||
INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, \
|
||||
GIC_HIGHEST_SEC_PRIORITY, \
|
||||
grp, GIC_INTR_CFG_LEVEL), \
|
||||
INTR_PROP_DESC(STM32MP1_IRQ_TAMPSERRS, \
|
||||
GIC_HIGHEST_SEC_PRIORITY, \
|
||||
grp, GIC_INTR_CFG_LEVEL), \
|
||||
INTR_PROP_DESC(STM32MP1_IRQ_AXIERRIRQ, \
|
||||
GIC_HIGHEST_SEC_PRIORITY, \
|
||||
grp, GIC_INTR_CFG_LEVEL), \
|
||||
|
|
|
|||
|
|
@ -24,8 +24,8 @@ $(eval $(call add_define,PLAT_PARTITION_MAX_ENTRIES))
|
|||
PLAT_INCLUDES := -Iplat/st/stm32mp1/include/
|
||||
|
||||
# Device tree
|
||||
STM32_DTB_FILE_NAME ?= stm32mp157c-ev1.dtb
|
||||
FDT_SOURCES := $(addprefix fdts/, $(patsubst %.dtb,%.dts,$(STM32_DTB_FILE_NAME)))
|
||||
DTB_FILE_NAME ?= stm32mp157c-ev1.dtb
|
||||
FDT_SOURCES := $(addprefix fdts/, $(patsubst %.dtb,%.dts,$(DTB_FILE_NAME)))
|
||||
DTC_FLAGS += -Wno-unit_address_vs_reg
|
||||
|
||||
include lib/libfdt/libfdt.mk
|
||||
|
|
@ -82,13 +82,13 @@ BL2_SOURCES += common/desc_image_load.c \
|
|||
|
||||
# Macros and rules to build TF binary
|
||||
STM32_TF_ELF_LDFLAGS := --hash-style=gnu --as-needed
|
||||
STM32_DT_BASENAME := $(STM32_DTB_FILE_NAME:.dtb=)
|
||||
STM32_DT_BASENAME := $(DTB_FILE_NAME:.dtb=)
|
||||
STM32_TF_STM32 := ${BUILD_PLAT}/tf-a-${STM32_DT_BASENAME}.stm32
|
||||
STM32_TF_BINARY := $(STM32_TF_STM32:.stm32=.bin)
|
||||
STM32_TF_MAPFILE := $(STM32_TF_STM32:.stm32=.map)
|
||||
STM32_TF_LINKERFILE := $(STM32_TF_STM32:.stm32=.ld)
|
||||
STM32_TF_ELF := $(STM32_TF_STM32:.stm32=.elf)
|
||||
STM32_TF_DTBFILE := ${BUILD_PLAT}/fdts/${STM32_DTB_FILE_NAME}
|
||||
STM32_TF_DTBFILE := ${BUILD_PLAT}/fdts/${DTB_FILE_NAME}
|
||||
STM32_TF_OBJS := ${BUILD_PLAT}/stm32mp1.o
|
||||
|
||||
# Variables for use with stm32image
|
||||
|
|
@ -131,7 +131,7 @@ ${STM32_TF_OBJS}: plat/st/stm32mp1/stm32mp1.S bl2 ${BL32_DEP} ${STM32_TF_DTBFILE
|
|||
-DDTB_BIN_PATH=\"${STM32_TF_DTBFILE}\" \
|
||||
-c plat/st/stm32mp1/stm32mp1.S -o $@
|
||||
|
||||
${STM32_TF_LINKERFILE}: plat/st/stm32mp1/stm32mp1.ld.S
|
||||
${STM32_TF_LINKERFILE}: plat/st/stm32mp1/stm32mp1.ld.S ${BUILD_PLAT}
|
||||
@echo " LDS $<"
|
||||
${Q}${AS} ${ASFLAGS} ${TF_CFLAGS} -P -E $< -o $@
|
||||
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
|
||||
* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
|
@ -13,6 +13,7 @@
|
|||
#include <common/bl_common.h>
|
||||
#include <common/debug.h>
|
||||
#include <context.h>
|
||||
#include <drivers/arm/gicv2.h>
|
||||
#include <drivers/arm/tzc400.h>
|
||||
#include <drivers/generic_delay_timer.h>
|
||||
#include <drivers/st/stm32_console.h>
|
||||
|
|
@ -40,7 +41,7 @@ static struct console_stm32 console;
|
|||
******************************************************************************/
|
||||
void sp_min_plat_fiq_handler(uint32_t id)
|
||||
{
|
||||
switch (id) {
|
||||
switch (id & INT_ID_MASK) {
|
||||
case STM32MP1_IRQ_TZC400:
|
||||
ERROR("STM32MP1_IRQ_TZC400 generated\n");
|
||||
panic();
|
||||
|
|
@ -50,7 +51,7 @@ void sp_min_plat_fiq_handler(uint32_t id)
|
|||
panic();
|
||||
break;
|
||||
default:
|
||||
ERROR("SECURE IT handler not define for it : %i", id);
|
||||
ERROR("SECURE IT handler not define for it : %u", id);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
|
@ -80,7 +81,7 @@ entry_point_info_t *sp_min_plat_get_bl33_ep_info(void)
|
|||
void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1,
|
||||
u_register_t arg2, u_register_t arg3)
|
||||
{
|
||||
struct dt_node_info dt_dev_info;
|
||||
struct dt_node_info dt_uart_info;
|
||||
int result;
|
||||
bl_params_t *params_from_bl2 = (bl_params_t *)arg0;
|
||||
|
||||
|
|
@ -114,10 +115,10 @@ void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1,
|
|||
panic();
|
||||
}
|
||||
|
||||
result = dt_get_stdout_uart_info(&dt_dev_info);
|
||||
result = dt_get_stdout_uart_info(&dt_uart_info);
|
||||
|
||||
if ((result > 0) && dt_dev_info.status) {
|
||||
if (console_stm32_register(dt_dev_info.base, 0,
|
||||
if ((result > 0) && dt_uart_info.status) {
|
||||
if (console_stm32_register(dt_uart_info.base, 0,
|
||||
STM32MP1_UART_BAUDRATE, &console) ==
|
||||
0) {
|
||||
panic();
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
|
||||
* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
|
@ -39,26 +39,11 @@
|
|||
MT_SECURE | \
|
||||
MT_EXECUTE_NEVER)
|
||||
|
||||
#define MAP_DDR MAP_REGION_FLAT(STM32MP1_DDR_BASE, \
|
||||
STM32MP1_DDR_MAX_SIZE, \
|
||||
MT_MEMORY | \
|
||||
MT_RW | \
|
||||
MT_SECURE | \
|
||||
MT_EXECUTE_NEVER)
|
||||
|
||||
#define MAP_DDR_NS MAP_REGION_FLAT(STM32MP1_DDR_BASE, \
|
||||
STM32MP1_DDR_MAX_SIZE, \
|
||||
MT_MEMORY | \
|
||||
MT_RW | \
|
||||
MT_NS | \
|
||||
MT_EXECUTE_NEVER)
|
||||
|
||||
#if defined(IMAGE_BL2)
|
||||
static const mmap_region_t stm32mp1_mmap[] = {
|
||||
MAP_SRAM,
|
||||
MAP_DEVICE1,
|
||||
MAP_DEVICE2,
|
||||
MAP_DDR,
|
||||
{0}
|
||||
};
|
||||
#endif
|
||||
|
|
@ -67,7 +52,6 @@ static const mmap_region_t stm32mp1_mmap[] = {
|
|||
MAP_SRAM,
|
||||
MAP_DEVICE1,
|
||||
MAP_DEVICE2,
|
||||
MAP_DDR_NS,
|
||||
{0}
|
||||
};
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
|
||||
* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
|
@ -125,14 +125,6 @@ enum ddr_type {
|
|||
#define STM32MP1_DEBUG_USART_BASE UART4_BASE
|
||||
#define STM32MP1_UART_BAUDRATE 115200
|
||||
|
||||
/*******************************************************************************
|
||||
* STM32MP1 GIC-400
|
||||
******************************************************************************/
|
||||
#define STM32MP1_GICD_BASE U(0xA0021000)
|
||||
#define STM32MP1_GICC_BASE U(0xA0022000)
|
||||
#define STM32MP1_GICH_BASE U(0xA0024000)
|
||||
#define STM32MP1_GICV_BASE U(0xA0026000)
|
||||
|
||||
/*******************************************************************************
|
||||
* STM32MP1 TZC (TZ400)
|
||||
******************************************************************************/
|
||||
|
|
@ -149,10 +141,7 @@ enum ddr_type {
|
|||
#define STM32MP1_TZC_ETH_ID U(10)
|
||||
#define STM32MP1_TZC_DAP_ID U(15)
|
||||
|
||||
#define STM32MP1_MEMORY_NS 0
|
||||
#define STM32MP1_MEMORY_SECURE 1
|
||||
|
||||
#define STM32MP1_FILTER_BIT_ALL 3
|
||||
#define STM32MP1_FILTER_BIT_ALL U(3)
|
||||
|
||||
/*******************************************************************************
|
||||
* STM32MP1 SDMMC
|
||||
|
|
|
|||
|
|
@ -1,18 +1,28 @@
|
|||
/*
|
||||
* Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
|
||||
* Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <libfdt.h>
|
||||
|
||||
#include <platform_def.h>
|
||||
|
||||
#include <common/bl_common.h>
|
||||
#include <common/debug.h>
|
||||
#include <drivers/arm/gicv2.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <lib/utils.h>
|
||||
#include <plat/common/platform.h>
|
||||
|
||||
#include <stm32mp1_dt.h>
|
||||
#include <stm32mp1_private.h>
|
||||
|
||||
struct stm32_gic_instance {
|
||||
uint32_t cells;
|
||||
uint32_t phandle_node;
|
||||
};
|
||||
|
||||
/******************************************************************************
|
||||
* On a GICv2 system, the Group 1 secure interrupts are treated as Group 0
|
||||
* interrupts.
|
||||
|
|
@ -22,19 +32,55 @@ static const interrupt_prop_t stm32mp1_interrupt_props[] = {
|
|||
PLATFORM_G0_PROPS(GICV2_INTR_GROUP0)
|
||||
};
|
||||
|
||||
static unsigned int target_mask_array[PLATFORM_CORE_COUNT];
|
||||
/* Fix target_mask_array as secondary core is not able to initialize it */
|
||||
static unsigned int target_mask_array[PLATFORM_CORE_COUNT] = {1, 2};
|
||||
|
||||
static const gicv2_driver_data_t platform_gic_data = {
|
||||
.gicd_base = STM32MP1_GICD_BASE,
|
||||
.gicc_base = STM32MP1_GICC_BASE,
|
||||
static gicv2_driver_data_t platform_gic_data = {
|
||||
.interrupt_props = stm32mp1_interrupt_props,
|
||||
.interrupt_props_num = ARRAY_SIZE(stm32mp1_interrupt_props),
|
||||
.target_masks = target_mask_array,
|
||||
.target_masks_num = ARRAY_SIZE(target_mask_array),
|
||||
};
|
||||
|
||||
static struct stm32_gic_instance stm32_gic;
|
||||
|
||||
void stm32mp1_gic_init(void)
|
||||
{
|
||||
int node;
|
||||
void *fdt;
|
||||
const fdt32_t *cuint;
|
||||
struct dt_node_info dt_gic;
|
||||
|
||||
if (fdt_get_address(&fdt) == 0) {
|
||||
panic();
|
||||
}
|
||||
|
||||
node = dt_get_node(&dt_gic, -1, "arm,cortex-a7-gic");
|
||||
if (node < 0) {
|
||||
panic();
|
||||
}
|
||||
|
||||
platform_gic_data.gicd_base = dt_gic.base;
|
||||
|
||||
cuint = fdt_getprop(fdt, node, "reg", NULL);
|
||||
if (cuint == NULL) {
|
||||
panic();
|
||||
}
|
||||
|
||||
platform_gic_data.gicc_base = fdt32_to_cpu(*(cuint + 2));
|
||||
|
||||
cuint = fdt_getprop(fdt, node, "#interrupt-cells", NULL);
|
||||
if (cuint == NULL) {
|
||||
panic();
|
||||
}
|
||||
|
||||
stm32_gic.cells = fdt32_to_cpu(*cuint);
|
||||
|
||||
stm32_gic.phandle_node = fdt_get_phandle(fdt, node);
|
||||
if (stm32_gic.phandle_node == 0U) {
|
||||
panic();
|
||||
}
|
||||
|
||||
gicv2_driver_init(&platform_gic_data);
|
||||
gicv2_distif_init();
|
||||
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
|
||||
* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
|
@ -23,11 +23,9 @@
|
|||
#include <boot_api.h>
|
||||
#include <stm32mp1_private.h>
|
||||
|
||||
static uint32_t stm32_sec_entrypoint;
|
||||
static uintptr_t stm32_sec_entrypoint;
|
||||
static uint32_t cntfrq_core0;
|
||||
|
||||
#define SEND_SECURE_IT_TO_CORE_1 0x20000U
|
||||
|
||||
/*******************************************************************************
|
||||
* STM32MP1 handler called when a CPU is about to enter standby.
|
||||
* call by core 1 to enter in wfi
|
||||
|
|
@ -42,6 +40,7 @@ static void stm32_cpu_standby(plat_local_state_t cpu_state)
|
|||
* Enter standby state
|
||||
* dsb is good practice before using wfi to enter low power states
|
||||
*/
|
||||
isb();
|
||||
dsb();
|
||||
while (interrupt == GIC_SPURIOUS_INTERRUPT) {
|
||||
wfi();
|
||||
|
|
@ -102,8 +101,7 @@ static int stm32_pwr_domain_on(u_register_t mpidr)
|
|||
}
|
||||
|
||||
/* Generate an IT to core 1 */
|
||||
mmio_write_32(STM32MP1_GICD_BASE + GICD_SGIR,
|
||||
SEND_SECURE_IT_TO_CORE_1 | ARM_IRQ_SEC_SGI_0);
|
||||
gicv2_raise_sgi(ARM_IRQ_SEC_SGI_0, STM32MP1_SECONDARY_CPU);
|
||||
|
||||
return PSCI_E_SUCCESS;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
|
||||
* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
|
@ -65,22 +65,6 @@ static void init_tzc400(void)
|
|||
******************************************************************************/
|
||||
static void early_init_tzc400(void)
|
||||
{
|
||||
uint32_t rstsr, rst_standby;
|
||||
|
||||
rstsr = mmio_read_32(RCC_BASE + RCC_MP_RSTSCLRR);
|
||||
|
||||
/* No warning if return from (C)STANDBY */
|
||||
rst_standby = rstsr &
|
||||
(RCC_MP_RSTSCLRR_STDBYRSTF | RCC_MP_RSTSCLRR_CSTDBYRSTF);
|
||||
|
||||
if (stm32mp1_clk_is_enabled(TZC1) && (rst_standby == 0U)) {
|
||||
WARN("TZC400 port 1 clock already enable\n");
|
||||
}
|
||||
|
||||
if (stm32mp1_clk_is_enabled(TZC2) && (rst_standby == 0U)) {
|
||||
WARN("TZC400 port 2 clock already enable\n");
|
||||
}
|
||||
|
||||
if (stm32mp1_clk_enable(TZC1) != 0) {
|
||||
ERROR("Cannot enable TZC1 clock\n");
|
||||
panic();
|
||||
|
|
@ -103,6 +87,7 @@ static void early_init_tzc400(void)
|
|||
STM32MP1_DDR_BASE +
|
||||
(STM32MP1_DDR_MAX_SIZE - 1U),
|
||||
TZC_REGION_S_RDWR,
|
||||
TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_A7_ID) |
|
||||
TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_SDMMC_ID));
|
||||
|
||||
/* Raise an exception if a NS device tries to access secure memory */
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue