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Migrate ARM standard platforms to the refactored TZC driver

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This patch migrates ARM Standard platforms to the refactored TZC driver.

Change-Id: I2a2f60b645f73e14d8f416740c4551cec87cb1fb
This commit is contained in:
Soby Mathew 2016-02-26 14:23:19 +00:00
parent 6b47706375
commit 57f782019a
8 changed files with 18 additions and 18 deletions
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2
include/plat/arm/common/plat_arm.h
View file

@ -130,7 +130,7 @@ void arm_configure_mmu_el3(unsigned long total_base,
void arm_io_setup(void);
/* Security utility functions */
void arm_tzc_setup(void);
void arm_tzc400_setup(void);
/* Systimer utility function */
void arm_configure_sys_timer(void);

2
include/plat/arm/css/common/css_def.h
View file

@ -143,7 +143,7 @@
#define PLAT_ARM_NS_IMAGE_OFFSET 0xE0000000
/* TZC related constants */
#define PLAT_ARM_TZC_FILTERS REG_ATTR_FILTER_BIT_ALL
#define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT_ALL
/* Trusted mailbox base address common to all CSS */
#define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE

2
plat/arm/board/fvp/fvp_security.c
View file

@ -46,5 +46,5 @@ void plat_arm_security_setup(void)
*/
if (get_arm_config()->flags & ARM_CONFIG_HAS_TZC)
arm_tzc_setup();
arm_tzc400_setup();
}

2
plat/arm/board/fvp/include/platform_def.h
View file

@ -113,7 +113,7 @@
* would normally use the default ID so allow that too.
*/
#define PLAT_ARM_TZC_BASE 0x2a4a0000
#define PLAT_ARM_TZC_FILTERS REG_ATTR_FILTER_BIT(0)
#define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0)
#define PLAT_ARM_TZC_NS_DEV_ACCESS ( \
TZC_REGION_ACCESS_RDWR(FVP_NSAID_DEFAULT) | \

2
plat/arm/board/fvp/platform.mk
View file

@ -65,7 +65,7 @@ endif
FVP_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c \
plat/arm/common/arm_cci.c
FVP_SECURITY_SOURCES := drivers/arm/tzc400/tzc400.c \
FVP_SECURITY_SOURCES := drivers/arm/tzc/tzc400.c \
plat/arm/board/fvp/fvp_security.c \
plat/arm/common/arm_tzc400.c

2
plat/arm/board/juno/juno_security.c
View file

@ -65,7 +65,7 @@ static void css_init_nic400(void)
void plat_arm_security_setup(void)
{
/* Initialize the TrustZone Controller */
arm_tzc_setup();
arm_tzc400_setup();
/* Do ARM CSS internal NIC setup */
css_init_nic400();
/* Do ARM CSS SoC security setup */

2
plat/arm/board/juno/platform.mk
View file

@ -37,7 +37,7 @@ JUNO_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
JUNO_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c \
plat/arm/common/arm_cci.c
JUNO_SECURITY_SOURCES := drivers/arm/tzc400/tzc400.c \
JUNO_SECURITY_SOURCES := drivers/arm/tzc/tzc400.c \
plat/arm/board/juno/juno_security.c \
plat/arm/common/arm_tzc400.c

22
plat/arm/common/arm_tzc400.c
View file

@ -48,53 +48,53 @@
* When booting an EL3 payload, this is simplified: we configure region 0 with
* secure access only and do not enable any other region.
******************************************************************************/
void arm_tzc_setup(void)
void arm_tzc400_setup(void)
{
INFO("Configuring TrustZone Controller\n");
tzc_init(PLAT_ARM_TZC_BASE);
tzc400_init(PLAT_ARM_TZC_BASE);
/* Disable filters. */
tzc_disable_filters();
tzc400_disable_filters();
#ifndef EL3_PAYLOAD_BASE
/* Region 0 set to no access by default */
tzc_configure_region0(TZC_REGION_S_NONE, 0);
tzc400_configure_region0(TZC_REGION_S_NONE, 0);
/* Region 1 set to cover Secure part of DRAM */
tzc_configure_region(PLAT_ARM_TZC_FILTERS, 1,
tzc400_configure_region(PLAT_ARM_TZC_FILTERS, 1,
ARM_AP_TZC_DRAM1_BASE, ARM_AP_TZC_DRAM1_END,
TZC_REGION_S_RDWR,
0);
/* Region 2 set to cover Non-Secure access to 1st DRAM address range.
* Apply the same configuration to given filters in the TZC. */
tzc_configure_region(PLAT_ARM_TZC_FILTERS, 2,
tzc400_configure_region(PLAT_ARM_TZC_FILTERS, 2,
ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END,
TZC_REGION_S_NONE,
PLAT_ARM_TZC_NS_DEV_ACCESS);
/* Region 3 set to cover Non-Secure access to 2nd DRAM address range */
tzc_configure_region(PLAT_ARM_TZC_FILTERS, 3,
tzc400_configure_region(PLAT_ARM_TZC_FILTERS, 3,
ARM_DRAM2_BASE, ARM_DRAM2_END,
TZC_REGION_S_NONE,
PLAT_ARM_TZC_NS_DEV_ACCESS);
#else
/* Allow secure access only to DRAM for EL3 payloads. */
tzc_configure_region0(TZC_REGION_S_RDWR, 0);
tzc400_configure_region0(TZC_REGION_S_RDWR, 0);
#endif /* EL3_PAYLOAD_BASE */
/*
* Raise an exception if a NS device tries to access secure memory
* TODO: Add interrupt handling support.
*/
tzc_set_action(TZC_ACTION_ERR);
tzc400_set_action(TZC_ACTION_ERR);
/* Enable filters. */
tzc_enable_filters();
tzc400_enable_filters();
}
void plat_arm_security_setup(void)
{
arm_tzc_setup();
arm_tzc400_setup();
}