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https://github.com/ARM-software/arm-trusted-firmware.git
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stm32mp1: Add support for SPI-NAND boot device
STM32MP1 platform is able to boot from SPI-NAND devices. These modifications add this support using the new SPI-NAND framework. Change-Id: I0d5448bdc4bde153c1209e8043846c0f935ae5ba Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
This commit is contained in:
Lionel Debieve
parent
0581a88778
commit
5704422814
6 changed files with 147 additions and 24 deletions
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@ -19,9 +19,11 @@
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#include <drivers/mmc.h>
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#include <drivers/partition/partition.h>
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#include <drivers/raw_nand.h>
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#include <drivers/spi_nand.h>
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#include <drivers/st/io_mmc.h>
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#include <drivers/st/io_stm32image.h>
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#include <drivers/st/stm32_fmc2_nand.h>
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#include <drivers/st/stm32_qspi.h>
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#include <drivers/st/stm32_sdmmc2.h>
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#include <lib/mmio.h>
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#include <lib/utils.h>
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@ -70,6 +72,17 @@ static io_mtd_dev_spec_t nand_dev_spec = {
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static const io_dev_connector_t *nand_dev_con;
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#endif
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#if STM32MP_SPI_NAND
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static io_mtd_dev_spec_t spi_nand_dev_spec = {
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.ops = {
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.init = spi_nand_init,
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.read = nand_read,
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},
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};
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static const io_dev_connector_t *spi_dev_con;
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#endif
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#ifdef AARCH32_SP_OPTEE
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static const struct stm32image_part_info optee_header_partition_spec = {
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.name = OPTEE_HEADER_IMAGE_NAME,
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@ -226,6 +239,9 @@ static void print_boot_device(boot_api_context_t *boot_context)
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case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC:
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INFO("Using FMC NAND\n");
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break;
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case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_QSPI:
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INFO("Using SPI NAND\n");
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break;
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default:
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ERROR("Boot interface not found\n");
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panic();
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@ -382,6 +398,60 @@ static void boot_fmc2_nand(boot_api_context_t *boot_context)
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}
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#endif /* STM32MP_RAW_NAND */
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#if STM32MP_SPI_NAND
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static void boot_spi_nand(boot_api_context_t *boot_context)
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{
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int io_result __unused;
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uint8_t idx;
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struct stm32image_part_info *part;
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io_result = stm32_qspi_init();
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assert(io_result == 0);
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io_result = register_io_dev_mtd(&spi_dev_con);
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assert(io_result == 0);
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/* Open connections to device */
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io_result = io_dev_open(spi_dev_con,
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(uintptr_t)&spi_nand_dev_spec,
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&storage_dev_handle);
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assert(io_result == 0);
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stm32image_dev_info_spec.device_size =
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spi_nand_dev_spec.device_size;
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idx = IMG_IDX_BL33;
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part = &stm32image_dev_info_spec.part_info[idx];
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part->part_offset = STM32MP_NAND_BL33_OFFSET;
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part->bkp_offset = spi_nand_dev_spec.erase_size;
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#ifdef AARCH32_SP_OPTEE
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idx = IMG_IDX_OPTEE_HEADER;
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part = &stm32image_dev_info_spec.part_info[idx];
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part->part_offset = STM32MP_NAND_TEEH_OFFSET;
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part->bkp_offset = spi_nand_dev_spec.erase_size;
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idx = IMG_IDX_OPTEE_PAGED;
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part = &stm32image_dev_info_spec.part_info[idx];
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part->part_offset = STM32MP_NAND_TEED_OFFSET;
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part->bkp_offset = spi_nand_dev_spec.erase_size;
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idx = IMG_IDX_OPTEE_PAGER;
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part = &stm32image_dev_info_spec.part_info[idx];
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part->part_offset = STM32MP_NAND_TEEX_OFFSET;
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part->bkp_offset = spi_nand_dev_spec.erase_size;
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#endif
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io_result = register_io_dev_stm32image(&stm32image_dev_con);
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assert(io_result == 0);
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io_result = io_dev_open(stm32image_dev_con,
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(uintptr_t)&stm32image_dev_info_spec,
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&image_dev_handle);
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assert(io_result == 0);
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}
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#endif /* STM32MP_SPI_NAND */
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void stm32mp_io_setup(void)
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{
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int io_result __unused;
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@ -422,6 +492,12 @@ void stm32mp_io_setup(void)
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boot_fmc2_nand(boot_context);
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break;
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#endif
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#if STM32MP_SPI_NAND
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case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_QSPI:
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dmbsy();
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boot_spi_nand(boot_context);
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break;
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#endif
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default:
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ERROR("Boot interface %d not supported\n",
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@ -36,6 +36,9 @@
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/* Boot occurred on FMC */
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#define BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC 0x3U
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/* Boot occurred on QSPI NAND */
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#define BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_QSPI 0x7U
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/**
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* @brief Possible value of boot context field 'EmmcXferStatus'
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*/
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@ -8,7 +8,9 @@
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#define STM32MP1_BOOT_DEVICE_H
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#include <drivers/raw_nand.h>
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#include <drivers/spi_nand.h>
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int plat_get_raw_nand_data(struct rawnand_device *device);
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int plat_get_spi_nand_data(struct spinand_device *device);
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#endif /* STM32MP1_BOOT_DEVICE_H */
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@ -28,17 +28,21 @@ $(eval $(call add_define,PLAT_PARTITION_MAX_ENTRIES))
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STM32MP_EMMC ?= 0
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STM32MP_SDMMC ?= 0
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STM32MP_RAW_NAND ?= 0
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STM32MP_SPI_NAND ?= 0
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ifeq ($(filter 1,${STM32MP_EMMC} ${STM32MP_SDMMC} ${STM32MP_RAW_NAND}),)
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ifeq ($(filter 1,${STM32MP_EMMC} ${STM32MP_SDMMC} ${STM32MP_RAW_NAND} \
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${STM32MP_SPI_NAND}),)
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$(error "No boot device driver is enabled")
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endif
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$(eval $(call assert_boolean,STM32MP_EMMC))
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$(eval $(call assert_boolean,STM32MP_SDMMC))
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$(eval $(call assert_boolean,STM32MP_RAW_NAND))
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$(eval $(call assert_boolean,STM32MP_SPI_NAND))
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$(eval $(call add_define,STM32MP_EMMC))
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$(eval $(call add_define,STM32MP_SDMMC))
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$(eval $(call add_define,STM32MP_RAW_NAND))
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$(eval $(call add_define,STM32MP_SPI_NAND))
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PLAT_INCLUDES := -Iplat/st/common/include/
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PLAT_INCLUDES += -Iplat/st/stm32mp1/include/
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@ -108,7 +112,16 @@ BL2_SOURCES += drivers/mtd/nand/raw_nand.c \
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drivers/st/fmc/stm32_fmc2_nand.c
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endif
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ifneq ($(filter 1,${STM32MP_RAW_NAND}),)
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ifeq (${STM32MP_SPI_NAND},1)
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BL2_SOURCES += drivers/mtd/nand/spi_nand.c
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endif
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ifeq (${STM32MP_SPI_NAND},1)
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BL2_SOURCES += drivers/mtd/spi-mem/spi_mem.c \
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drivers/st/spi/stm32_qspi.c
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endif
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ifneq ($(filter 1,${STM32MP_RAW_NAND} ${STM32MP_SPI_NAND}),)
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BL2_SOURCES += drivers/mtd/nand/core.c \
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plat/st/stm32mp1/stm32mp1_boot_device.c
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endif
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@ -12,8 +12,8 @@
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#define SZ_512 0x200U
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#if STM32MP_RAW_NAND
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static int get_data_from_otp(struct nand_device *nand_dev)
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#if STM32MP_RAW_NAND || STM32MP_SPI_NAND
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static int get_data_from_otp(struct nand_device *nand_dev, bool is_slc)
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{
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int result;
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uint32_t nand_param;
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@ -81,28 +81,37 @@ static int get_data_from_otp(struct nand_device *nand_dev)
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NAND_BLOCK_NB_UNIT * nand_dev->block_size;
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ecc:
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switch ((nand_param & NAND_ECC_BIT_NB_MASK) >>
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NAND_ECC_BIT_NB_SHIFT) {
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case NAND_ECC_BIT_NB_1_BITS:
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nand_dev->ecc.max_bit_corr = 1U;
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break;
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if (is_slc) {
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switch ((nand_param & NAND_ECC_BIT_NB_MASK) >>
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NAND_ECC_BIT_NB_SHIFT) {
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case NAND_ECC_BIT_NB_1_BITS:
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nand_dev->ecc.max_bit_corr = 1U;
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break;
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case NAND_ECC_BIT_NB_4_BITS:
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nand_dev->ecc.max_bit_corr = 4U;
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break;
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case NAND_ECC_BIT_NB_4_BITS:
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nand_dev->ecc.max_bit_corr = 4U;
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break;
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case NAND_ECC_BIT_NB_8_BITS:
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nand_dev->ecc.max_bit_corr = 8U;
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break;
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case NAND_ECC_BIT_NB_8_BITS:
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nand_dev->ecc.max_bit_corr = 8U;
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break;
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case NAND_ECC_ON_DIE:
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nand_dev->ecc.mode = NAND_ECC_ONDIE;
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break;
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case NAND_ECC_ON_DIE:
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nand_dev->ecc.mode = NAND_ECC_ONDIE;
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break;
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default:
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if (nand_dev->ecc.max_bit_corr == 0U) {
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ERROR("No valid eccbit number\n");
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return -EINVAL;
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default:
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if (nand_dev->ecc.max_bit_corr == 0U) {
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ERROR("No valid eccbit number\n");
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return -EINVAL;
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}
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}
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} else {
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/* Selected multiple plane NAND */
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if ((nand_param & NAND_PLANE_BIT_NB_MASK) != 0U) {
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nand_dev->nb_planes = 2U;
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} else {
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nand_dev->nb_planes = 1U;
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}
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}
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@ -111,7 +120,7 @@ ecc:
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return 0;
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}
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#endif
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#endif /* STM32MP_RAW_NAND || STM32MP_SPI_NAND */
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#if STM32MP_RAW_NAND
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int plat_get_raw_nand_data(struct rawnand_device *device)
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@ -119,7 +128,24 @@ int plat_get_raw_nand_data(struct rawnand_device *device)
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device->nand_dev->ecc.mode = NAND_ECC_HW;
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device->nand_dev->ecc.size = SZ_512;
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return get_data_from_otp(device->nand_dev);
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return get_data_from_otp(device->nand_dev, true);
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}
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#endif
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#if STM32MP_SPI_NAND
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int plat_get_spi_nand_data(struct spinand_device *device)
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{
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zeromem(&device->spi_read_cache_op, sizeof(struct spi_mem_op));
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device->spi_read_cache_op.cmd.opcode = SPI_NAND_OP_READ_FROM_CACHE_4X;
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device->spi_read_cache_op.cmd.buswidth = SPI_MEM_BUSWIDTH_1_LINE;
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device->spi_read_cache_op.addr.nbytes = 2U;
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device->spi_read_cache_op.addr.buswidth = SPI_MEM_BUSWIDTH_1_LINE;
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device->spi_read_cache_op.dummy.nbytes = 1U;
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device->spi_read_cache_op.dummy.buswidth = SPI_MEM_BUSWIDTH_1_LINE;
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device->spi_read_cache_op.data.buswidth = SPI_MEM_BUSWIDTH_4_LINE;
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device->spi_read_cache_op.data.dir = SPI_MEM_DATA_IN;
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return get_data_from_otp(device->nand_dev, false);
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}
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#endif
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@ -340,6 +340,9 @@ enum ddr_type {
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#define NAND_ECC_BIT_NB_8_BITS U(3)
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#define NAND_ECC_ON_DIE U(4)
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/* NAND number of planes */
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#define NAND_PLANE_BIT_NB_MASK BIT(14)
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/*******************************************************************************
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* STM32MP1 TAMP
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******************************************************************************/
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