mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-19 02:54:24 +00:00
feat(mt8196): add SPM common version support
This patch provides common APIs for communication with other subsystems as well as common APIs for collecting the clock and power status of each subsystem. Signed-off-by: Wenzhen Yu <wenzhen.yu@mediatek.com> Change-Id: I1b907256f53578a58d74d66beec7140edf41f687
This commit is contained in:
Wenzhen Yu
parent
a24b53e0e5
commit
5532feb70c
7 changed files with 369 additions and 2 deletions
74
plat/mediatek/drivers/spm/version/inc/mt_spm_ver.h
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74
plat/mediatek/drivers/spm/version/inc/mt_spm_ver.h
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@ -0,0 +1,74 @@
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/*
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* Copyright (c) 2025, Mediatek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef MT_SPM_VER_H
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#define MT_SPM_VER_H
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#include <stdint.h>
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enum mt_plat_dram_to_spm_type {
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SPMFW_DEFAULT_TYPE = 0,
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SPMFW_LP4_2CH_3200,
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SPMFW_LP4X_2CH_3600,
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SPMFW_LP3_1CH_1866,
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SPMFW_LP4X_2CH_3733,
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SPMFW_LP4X_2CH_4266,
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SPMFW_LP4X_2CH_3200,
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SPMFW_LP5_2CH_6400,
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SPMFW_LP5X_4CH_7500,
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SPMFW_TYPE_NOT_FOUND,
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};
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enum pwrctrl_selection {
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SPM_INIT_PWRCTRL = 0,
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SPM_VCOREDVFS_PWRCTRL,
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SPM_IDLE_PWRCTRL,
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SPM_SUSPEND_PWRCTRL,
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SPM_PWRCTRL_MAX,
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};
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struct pcm_desc {
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const char *version; /* PCM code version */
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uint32_t *base; /* Binary array base */
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uintptr_t base_dma; /* DMA addr of base */
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uint32_t pmem_words;
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uint32_t total_words;
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uint32_t pmem_start;
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uint32_t dmem_start;
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};
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#define DYNA_LOAD_PCM_PATH_SIZE 128
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#define PCM_FIRMWARE_VERSION_SIZE 128
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struct dyna_load_pcm_t {
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char path[DYNA_LOAD_PCM_PATH_SIZE];
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char version[PCM_FIRMWARE_VERSION_SIZE];
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char *buf;
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struct pcm_desc desc;
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int ready;
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};
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struct load_pcm_fw_t {
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unsigned int fw_max_num;
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char **pcm_name_str;
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struct dyna_load_pcm_t *dyna_load_pcm;
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unsigned int (*is_fw_running)(void);
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unsigned int (*get_fw_index)(unsigned int fw_type);
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int (*fw_init)(struct pcm_desc *desc);
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int (*fw_run)(unsigned int first, void *pwrctrl);
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};
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/* SPM firmware restart definition */
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#define SPM_FW_FORCE_RESET BIT(0)
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#define SPM_FW_FORCE_RESUME BIT(1)
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int spm_firmware_restart(unsigned int force, void *pwrctrl);
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int spm_firmware_type_get(void);
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void spm_firmware_type_probe(unsigned int type);
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void spm_firmware_init(uint64_t addr, uint64_t size);
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uint64_t spm_load_firmware_status(void);
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void register_load_fw(struct load_pcm_fw_t *info);
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#endif /* MT_SPM_VER_H */
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2023, MediaTek Inc. All rights reserved.
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* Copyright (c) 2025, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -10,7 +10,9 @@
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enum mt_spm_sspm_notify_id {
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MT_SPM_NOTIFY_LP_ENTER = 0,
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MT_SPM_NOTIFY_LP_LEAVE,
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MT_SPM_NOTIFY_SUSPEND_VCORE_VOLTAGE,
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MT_SPM_NOTIFY_SUSPEND_VCORE,
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MT_SPM_NOTIFY_IDLE_ENTER,
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MT_SPM_NOTIFY_IDLE_LEAVE,
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};
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#ifdef MTK_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
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@ -0,0 +1,23 @@
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/*
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* Copyright (c) 2025, Mediatek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef MT_SPM_SSPM_INTC_H
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#define MT_SPM_SSPM_INTC_H
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#define MT_SPM_SSPM_INTC_SEL_0 0x10
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#define MT_SPM_SSPM_INTC_SEL_1 0x20
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#define MT_SPM_SSPM_INTC_SEL_2 0x40
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#define MT_SPM_SSPM_INTC_SEL_3 0x80
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#define MT_SPM_SSPM_INTC_TRIGGER(id, sg) \
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(((0x10 << (id)) | ((sg) << (id))) & 0xFF)
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#define SSPM_CFGREG_ADDR(ofs) (SSPM_CFGREG_BASE + (ofs))
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#define AP_SSPM_IRQ SSPM_CFGREG_ADDR(0x018)
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#define DO_SPM_SSPM_LP_NOTIFY() mmio_write_32(AP_SSPM_IRQ, 1)
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#endif /* MT_SPM_SSPM_INTC_H */
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@ -0,0 +1,131 @@
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/*
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* Copyright (c) 2025, Mediatek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <lib/libc/errno.h>
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#include <lib/mmio.h>
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#include <platform_def.h>
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#include <mtk_mmap_pool.h>
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#include <notifier/inc/mt_spm_notifier.h>
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#include <notifier/v4/mt_spm_sspm_intc.h>
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#define MT_SPM_SSPM_MBOX_OFF(x) (SSPM_MBOX_3_BASE + x)
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#define MT_SPM_MBOX(slot) MT_SPM_SSPM_MBOX_OFF((slot<<2UL))
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/* LOOKUP SSPM_MBOX_SPM_LP1 */
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#define SSPM_MBOX_SPM_LP_LOOKUP1 MT_SPM_MBOX(0)
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/* LOOKUP SSPM_MBOX_SPM_LP2 */
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#define SSPM_MBOX_SPM_LP_LOOKUP2 MT_SPM_MBOX(1)
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#define SSPM_MBOX_SPM_LP1 MT_SPM_MBOX(2)
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#define SSPM_MBOX_SPM_LP2 MT_SPM_MBOX(3)
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#define SSPM_MBOX_SPM_SIZE 16
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/* 4 mbox is in usage */
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#define MT_SPM_MBOX_OFFSET(slot) MT_SPM_MBOX((slot + 4))
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enum SSPM_SLEEP_CMD {
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SLP_TASK_NONE = 0,
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SLP_TASK_AP_SUSPEND,
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SLP_TASK_AP_RESUME,
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SLP_TASK_APSRC_OFF,
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SLP_TASK_APSRC_ON,
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SLP_TASK_INFRA_OFF,
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SLP_TASK_INFRA_ON,
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SLP_TASK_VCORE_OFF,
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SLP_TASK_VCORE_ON,
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SLP_TASK_IDLE_OFF,
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SLP_TASK_IDLE_ON,
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SLP_TASK_INFRA_noPERI_OFF,
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SLP_TASK_INFRA_noPERI_ON,
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SLP_TASK_ERR = 32,
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};
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static unsigned int cur_mbox_index;
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static int __mt_spm_is_available_index(int cur_idx)
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{
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unsigned int val;
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val = mmio_read_32(MT_SPM_MBOX_OFFSET(cur_idx));
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val = (val >> 30);
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if (val == 0 || val == 3)
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return 1;
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return 0;
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}
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static int __mt_spm_get_available_index(void)
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{
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unsigned int idx = cur_mbox_index;
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int i = 0;
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for (i = 0 ; i < SSPM_MBOX_SPM_SIZE ; i++) {
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if (__mt_spm_is_available_index(idx)) {
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cur_mbox_index = (idx + 1) % SSPM_MBOX_SPM_SIZE;
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return idx;
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}
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idx = (idx + 1) % SSPM_MBOX_SPM_SIZE;
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}
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return -EBUSY;
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}
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static int __mt_spm_sspm_write_cmd_queue(int idx, int value)
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{
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unsigned int val;
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val = mmio_read_32(MT_SPM_MBOX_OFFSET(idx));
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val = val ^ BIT(31);
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val = (value & 0x3fffffff) | (val & 0xc0000000);
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mmio_write_32(MT_SPM_MBOX_OFFSET(idx), val);
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return 0;
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}
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void mt_spm_sspm_cmd_enqueue(int cmd)
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{
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int idx;
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idx = __mt_spm_get_available_index();
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/* Block when queue full */
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if (idx == -EBUSY) {
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while (!__mt_spm_is_available_index(cur_mbox_index))
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;
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idx = cur_mbox_index;
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cur_mbox_index = (cur_mbox_index+1) % SSPM_MBOX_SPM_SIZE;
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}
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__mt_spm_sspm_write_cmd_queue(idx, cmd);
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}
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int mt_spm_sspm_notify_u32(int type, unsigned int val)
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{
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switch (type) {
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case MT_SPM_NOTIFY_LP_ENTER:
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mmio_write_32(SSPM_MBOX_SPM_LP1, val);
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mt_spm_sspm_cmd_enqueue(SLP_TASK_AP_SUSPEND);
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DO_SPM_SSPM_LP_NOTIFY();
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break;
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case MT_SPM_NOTIFY_LP_LEAVE:
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mmio_write_32(SSPM_MBOX_SPM_LP1, val);
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mt_spm_sspm_cmd_enqueue(SLP_TASK_AP_RESUME);
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DO_SPM_SSPM_LP_NOTIFY();
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break;
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case MT_SPM_NOTIFY_IDLE_ENTER:
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mmio_write_32(SSPM_MBOX_SPM_LP1, val);
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mt_spm_sspm_cmd_enqueue(SLP_TASK_IDLE_OFF);
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DO_SPM_SSPM_LP_NOTIFY();
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break;
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case MT_SPM_NOTIFY_IDLE_LEAVE:
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mmio_write_32(SSPM_MBOX_SPM_LP1, val);
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mt_spm_sspm_cmd_enqueue(SLP_TASK_IDLE_ON);
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DO_SPM_SSPM_LP_NOTIFY();
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break;
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default:
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break;
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}
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return 0;
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}
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/*
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* Copyright (c) 2025, Mediatek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef MT_SPM_PMIC_WRAP_H
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#define MT_SPM_PMIC_WRAP_H
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struct pmic_wrap_cmd_setting {
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uint32_t spm_pwrap_addr;
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uint32_t cmd_addr;
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uint32_t cmd_data;
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};
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struct pmic_wrap_phase_setting {
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struct pmic_wrap_cmd_setting *cmd;
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unsigned int nr_idx;
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};
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struct pmic_wrap_setting {
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struct pmic_wrap_phase_setting *phase;
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const unsigned int phase_nr_idx;
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};
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int mt_spm_pmic_wrap_set_phase(unsigned int phase);
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int mt_spm_pmic_wrap_set_cmd(unsigned int phase,
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unsigned int idx, unsigned int cmd_data);
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unsigned long mt_spm_pmic_wrap_get_cmd(unsigned int phase, unsigned int idx);
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void mt_spm_pmic_wrap_set_table(struct pmic_wrap_setting *pw);
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#endif /* MT_SPM_PMIC_WRAP_H */
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/*
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* Copyright (c) 2025, Mediatek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <lib/libc/errno.h>
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#include <lib/mmio.h>
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#include <pmic_wrap/inc/mt_spm_pmic_wrap.h>
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#define SPM_DATA_SHIFT 16
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static struct pmic_wrap_setting *pmic_wrap;
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int mt_spm_pmic_wrap_set_phase(unsigned int phase)
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{
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int idx;
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uint32_t cmd_addr, cmd_data;
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struct pmic_wrap_phase_setting *current_phase;
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if (!pmic_wrap)
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return -ENODEV;
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if (phase >= pmic_wrap->phase_nr_idx)
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return -EINVAL;
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current_phase = &pmic_wrap->phase[phase];
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for (idx = 0; idx < current_phase->nr_idx; idx++) {
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cmd_addr = current_phase->cmd[idx].cmd_addr;
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cmd_data = current_phase->cmd[idx].cmd_data;
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mmio_write_32(current_phase->cmd[idx].spm_pwrap_addr,
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(cmd_addr << SPM_DATA_SHIFT) | cmd_data);
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}
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return 0;
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}
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int mt_spm_pmic_wrap_set_cmd(unsigned int phase,
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unsigned int idx, unsigned int cmd_data)
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{
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uint32_t cmd_addr;
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struct pmic_wrap_phase_setting *current_phase;
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if (!pmic_wrap)
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return -ENODEV;
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if (phase >= pmic_wrap->phase_nr_idx)
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return -EINVAL;
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if (idx >= pmic_wrap->phase[phase].nr_idx)
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return -EINVAL;
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current_phase = &pmic_wrap->phase[phase];
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current_phase->cmd[idx].cmd_data = cmd_data;
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cmd_addr = current_phase->cmd[idx].cmd_addr;
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mmio_write_32(current_phase->cmd[idx].spm_pwrap_addr,
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(cmd_addr << SPM_DATA_SHIFT) | cmd_data);
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return 0;
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}
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unsigned long mt_spm_pmic_wrap_get_cmd(unsigned int phase, unsigned int idx)
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{
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if (!pmic_wrap)
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return 0;
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if (phase >= pmic_wrap->phase_nr_idx)
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return 0;
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if (idx >= pmic_wrap->phase[phase].nr_idx)
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return 0;
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return pmic_wrap->phase[phase].cmd[idx].cmd_data;
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}
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void mt_spm_pmic_wrap_set_table(struct pmic_wrap_setting *pw)
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{
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pmic_wrap = pw;
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}
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23
plat/mediatek/drivers/spm/version/rules.mk
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23
plat/mediatek/drivers/spm/version/rules.mk
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@ -0,0 +1,23 @@
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#
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# Copyright (c) 2025, MediaTek Inc. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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LOCAL_DIR := $(call GET_LOCAL_DIR)
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MODULE := spm_version
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LOCAL_SRCS-y :=
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ifneq (${NOTIFIER_VER},)
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LOCAL_SRCS-y += ${LOCAL_DIR}/notifier/${NOTIFIER_VER}/mt_spm_sspm_notifier.c
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endif
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ifneq (${PMIC_GS_DUMP_VER},)
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LOCAL_SRCS-y += ${LOCAL_DIR}/pmic_gs/${PMIC_GS_DUMP_VER}/mt_spm_pmic_gs_dump.c
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endif
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ifneq (${PMIC_WRAP_VER},)
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LOCAL_SRCS-y += ${LOCAL_DIR}/pmic_wrap/${PMIC_WRAP_VER}/mt_spm_pmic_wrap.c
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endif
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$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))
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$(eval $(call add_defined_option,CONFIG_MTK_VCOREDVFS_SUPPORT))
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