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fix(ti): align static device region addresses to reduce MMU table count

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Align our device memory regions to the next highest MMU table level (LV2).
This allows the xlat_tables library code to use a single entry in the
higher order table, vs having to create a new table for LV3 entries.

This reduces our tables to just 4: 2 LV2 and 1 LV3 plus 1 spare in case
alignment changes ever cause one to be split. This saves 24KB of our
128KB total TF-A SRAM (~18%!).

While here, as USE_COHERENT_MEM does not change MAX_XLAT_TABLES but
does change our total MAX_MMAP_REGIONS, move that check accordingly.

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: I4cb8e3b2cc3d05c6c9a84d887dd6ec56bde7a786
This commit is contained in:
Andrew Davis 2023-10-25 16:42:27 -05:00
parent 0e1dc0f2bc
commit 53a868f676
2 changed files with 17 additions and 11 deletions
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18
plat/ti/k3/common/k3_bl31_setup.c
View file

@ -20,14 +20,20 @@
#include <k3_gicv3.h>
#include <ti_sci.h>
#define ADDR_DOWN(_adr) (_adr & XLAT_ADDR_MASK(2U))
#define SIZE_UP(_adr, _sz) (round_up((_adr + _sz), XLAT_BLOCK_SIZE(2U)) - ADDR_DOWN(_adr))
#define K3_MAP_REGION_FLAT(_adr, _sz, _attr) \
MAP_REGION_FLAT(ADDR_DOWN(_adr), SIZE_UP(_adr, _sz), _attr)
/* Table of regions to map using the MMU */
const mmap_region_t plat_k3_mmap[] = {
MAP_REGION_FLAT(K3_USART_BASE, K3_USART_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(K3_GIC_BASE, K3_GIC_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(K3_GTC_BASE, K3_GTC_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(SEC_PROXY_RT_BASE, SEC_PROXY_RT_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(SEC_PROXY_SCFG_BASE, SEC_PROXY_SCFG_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(SEC_PROXY_DATA_BASE, SEC_PROXY_DATA_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
K3_MAP_REGION_FLAT(K3_USART_BASE, K3_USART_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
K3_MAP_REGION_FLAT(K3_GIC_BASE, K3_GIC_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
K3_MAP_REGION_FLAT(K3_GTC_BASE, K3_GTC_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
K3_MAP_REGION_FLAT(SEC_PROXY_RT_BASE, SEC_PROXY_RT_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
K3_MAP_REGION_FLAT(SEC_PROXY_SCFG_BASE, SEC_PROXY_SCFG_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
K3_MAP_REGION_FLAT(SEC_PROXY_DATA_BASE, SEC_PROXY_DATA_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
{ /* sentinel */ }
};

10
plat/ti/k3/include/platform_def.h
View file

@ -70,11 +70,7 @@
* used, choose the smallest value needed to map the required virtual addresses
* for each BL stage.
*/
#if USE_COHERENT_MEM
#define MAX_XLAT_TABLES 10
#else
#define MAX_XLAT_TABLES 9
#endif
#define MAX_XLAT_TABLES 4
/*
* Defines the maximum number of regions that are allocated by the translation
@ -86,7 +82,11 @@
* runtime memory used, choose the smallest value needed to register the
* required regions for each BL stage.
*/
#if USE_COHERENT_MEM
#define MAX_MMAP_REGIONS 11
#else
#define MAX_MMAP_REGIONS 10
#endif
/*
* Defines the total size of the address space in bytes. For example, for a 32